1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 27d7d1bf1SArnaldo Carvalho de Melo #ifndef _ASM_X86_CPUFEATURES_H 37d7d1bf1SArnaldo Carvalho de Melo #define _ASM_X86_CPUFEATURES_H 47d7d1bf1SArnaldo Carvalho de Melo 57d7d1bf1SArnaldo Carvalho de Melo #ifndef _ASM_X86_REQUIRED_FEATURES_H 67d7d1bf1SArnaldo Carvalho de Melo #include <asm/required-features.h> 77d7d1bf1SArnaldo Carvalho de Melo #endif 87d7d1bf1SArnaldo Carvalho de Melo 97d7d1bf1SArnaldo Carvalho de Melo #ifndef _ASM_X86_DISABLED_FEATURES_H 107d7d1bf1SArnaldo Carvalho de Melo #include <asm/disabled-features.h> 117d7d1bf1SArnaldo Carvalho de Melo #endif 127d7d1bf1SArnaldo Carvalho de Melo 137d7d1bf1SArnaldo Carvalho de Melo /* 147d7d1bf1SArnaldo Carvalho de Melo * Defines x86 CPU feature bits 157d7d1bf1SArnaldo Carvalho de Melo */ 161a9bcaddSArnaldo Carvalho de Melo #define NCAPINTS 20 /* N 32-bit words worth of info */ 177d7d1bf1SArnaldo Carvalho de Melo #define NBUGINTS 1 /* N 32-bit bug flags */ 187d7d1bf1SArnaldo Carvalho de Melo 197d7d1bf1SArnaldo Carvalho de Melo /* 207d7d1bf1SArnaldo Carvalho de Melo * Note: If the comment begins with a quoted string, that string is used 217d7d1bf1SArnaldo Carvalho de Melo * in /proc/cpuinfo instead of the macro name. If the string is "", 227d7d1bf1SArnaldo Carvalho de Melo * this feature bit is not displayed in /proc/cpuinfo at all. 230b44cfb8SIngo Molnar * 240b44cfb8SIngo Molnar * When adding new features here that depend on other features, 250b44cfb8SIngo Molnar * please update the table in kernel/cpu/cpuid-deps.c as well. 267d7d1bf1SArnaldo Carvalho de Melo */ 277d7d1bf1SArnaldo Carvalho de Melo 280b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ 297d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ 307d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ 317d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ 327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ 337d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ 347d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ 357d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ 367d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ 377d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ 387d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ 397d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ 407d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ 417d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ 427d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ 430b44cfb8SIngo Molnar #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ 447d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ 457d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ 467d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ 477d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ 487d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ 497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ 507d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ 517d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ 527d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ 537d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ 547d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ 557d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ 567d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ 577d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ 587d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ 597d7d1bf1SArnaldo Carvalho de Melo 607d7d1bf1SArnaldo Carvalho de Melo /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 617d7d1bf1SArnaldo Carvalho de Melo /* Don't duplicate feature flags which are redundant with Intel! */ 627d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ 630b44cfb8SIngo Molnar #define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ 647d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ 657d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ 667d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ 677d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ 687d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ 690b44cfb8SIngo Molnar #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ 700b44cfb8SIngo Molnar #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ 710b44cfb8SIngo Molnar #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ 727d7d1bf1SArnaldo Carvalho de Melo 737d7d1bf1SArnaldo Carvalho de Melo /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ 747d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ 757d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ 767d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ 777d7d1bf1SArnaldo Carvalho de Melo 787d7d1bf1SArnaldo Carvalho de Melo /* Other features, Linux-defined mapping, word 3 */ 797d7d1bf1SArnaldo Carvalho de Melo /* This range is used for feature bits which conflict or are synthesized */ 807d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ 817d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ 827d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 837d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ 840b44cfb8SIngo Molnar 850b44cfb8SIngo Molnar /* CPU types for specific tunings: */ 867d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ 876faf64f5SArnaldo Carvalho de Melo /* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */ 887d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ 897d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ 907d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ 910b44cfb8SIngo Molnar #define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ 920b44cfb8SIngo Molnar #define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ 937d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ 947d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ 957d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ 960b44cfb8SIngo Molnar #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ 970b44cfb8SIngo Molnar #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ 980b44cfb8SIngo Molnar #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ 99*74455fd7SArnaldo Carvalho de Melo #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ 1000b44cfb8SIngo Molnar #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ 1017d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ 1027d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ 1037d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ 1040b44cfb8SIngo Molnar #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ 1057d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ 1067d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ 10774beb09aSArnaldo Carvalho de Melo #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ 1080b44cfb8SIngo Molnar #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ 1090b44cfb8SIngo Molnar #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ 1100b44cfb8SIngo Molnar #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ 111cc200a7dSArnaldo Carvalho de Melo #define X86_FEATURE_RAPL ( 3*32+29) /* AMD/Hygon RAPL interface */ 1127d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ 113c0621acfSIngo Molnar #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ 1147d7d1bf1SArnaldo Carvalho de Melo 1150b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ 1167d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ 1177d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ 1187d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ 1190b44cfb8SIngo Molnar #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ 1200b44cfb8SIngo Molnar #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ 1217d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ 1220b44cfb8SIngo Molnar #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ 1237d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ 1247d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ 1257d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ 1267d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ 1277d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ 1287d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ 1290b44cfb8SIngo Molnar #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ 1307d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ 1310b44cfb8SIngo Molnar #define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ 1327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ 1337d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ 1347d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ 1357d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ 1360b44cfb8SIngo Molnar #define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ 1377d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ 1387d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ 1390b44cfb8SIngo Molnar #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ 1407d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ 1410b44cfb8SIngo Molnar #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ 1420b44cfb8SIngo Molnar #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ 1437d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ 1440b44cfb8SIngo Molnar #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ 1450b44cfb8SIngo Molnar #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ 1467d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ 1477d7d1bf1SArnaldo Carvalho de Melo 1487d7d1bf1SArnaldo Carvalho de Melo /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 1497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ 1507d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ 1517d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ 1527d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ 1537d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ 1547d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ 1557d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ 1567d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ 1577d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ 1587d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ 1597d7d1bf1SArnaldo Carvalho de Melo 1600b44cfb8SIngo Molnar /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ 1617d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ 1627d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ 1630b44cfb8SIngo Molnar #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ 1647d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ 1657d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ 1667d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ 1677d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ 1687d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ 1697d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ 1707d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ 1717d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ 1727d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ 1737d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ 1747d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ 1757d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ 1767d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ 1770b44cfb8SIngo Molnar #define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ 1787d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ 1790b44cfb8SIngo Molnar #define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ 1800b44cfb8SIngo Molnar #define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ 1810b44cfb8SIngo Molnar #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ 1827d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ 1830b44cfb8SIngo Molnar #define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ 1840b44cfb8SIngo Molnar #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ 185a2105f8aSArnaldo Carvalho de Melo #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ 1860b44cfb8SIngo Molnar #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ 1877d7d1bf1SArnaldo Carvalho de Melo 1887d7d1bf1SArnaldo Carvalho de Melo /* 1897d7d1bf1SArnaldo Carvalho de Melo * Auxiliary flags: Linux defined - For features scattered in various 1907d7d1bf1SArnaldo Carvalho de Melo * CPUID levels like 0x6, 0xA etc, word 7. 1917d7d1bf1SArnaldo Carvalho de Melo * 1927d7d1bf1SArnaldo Carvalho de Melo * Reuse free bits when adding new feature flags! 1937d7d1bf1SArnaldo Carvalho de Melo */ 1940b44cfb8SIngo Molnar #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ 195fb7b7561SArnaldo Carvalho de Melo #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ 1967d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ 1977d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ 198c0621acfSIngo Molnar #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ 199c0621acfSIngo Molnar #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ 200c0621acfSIngo Molnar #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ 2015d64db29SArnaldo Carvalho de Melo #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */ 2027d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ 2037d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ 2044b3f7644SArnaldo Carvalho de Melo #define X86_FEATURE_XCOMPACTED ( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */ 2055d64db29SArnaldo Carvalho de Melo #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ 206f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */ 207f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */ 208c0621acfSIngo Molnar #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ 2094053717aSArnaldo Carvalho de Melo #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ 210a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ 211a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */ 2126e30437bSIngo Molnar #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ 2134053717aSArnaldo Carvalho de Melo #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ 2144b3f7644SArnaldo Carvalho de Melo #define X86_FEATURE_PERFMON_V2 ( 7*32+20) /* AMD Performance Monitoring Version 2 */ 2154053717aSArnaldo Carvalho de Melo #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ 2164caea057SArnaldo Carvalho de Melo #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */ 217a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */ 218a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */ 219a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ 220a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ 221a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ 22262ed93d1SArnaldo Carvalho de Melo #define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */ 223e24f14b0SDavid Woodhouse #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ 224d207ea8eSLinus Torvalds #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ 22571dd6528SArnaldo Carvalho de Melo #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */ 2266e30437bSIngo Molnar 2277d7d1bf1SArnaldo Carvalho de Melo /* Virtualization flags: Linux defined, word 8 */ 2287d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ 2297d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ 2307d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ 2317d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ 2327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ 2337d7d1bf1SArnaldo Carvalho de Melo 2340b44cfb8SIngo Molnar #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ 2357d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ 236252df177SArnaldo Carvalho de Melo #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */ 23740f1c039SArnaldo Carvalho de Melo #define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */ 23840f1c039SArnaldo Carvalho de Melo #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */ 2396faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_PVUNLOCK ( 8*32+20) /* "" PV unlock function */ 2406faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* "" PV vcpu_is_preempted function */ 2414b3f7644SArnaldo Carvalho de Melo #define X86_FEATURE_TDX_GUEST ( 8*32+22) /* Intel Trust Domain Extensions Guest */ 2427d7d1bf1SArnaldo Carvalho de Melo 2430b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ 2440b44cfb8SIngo Molnar #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ 2450b44cfb8SIngo Molnar #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ 246f93c789aSArnaldo Carvalho de Melo #define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */ 2477d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ 2487d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ 2497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ 250686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */ 2517d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ 2527d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ 2530b44cfb8SIngo Molnar #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ 2547d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ 2557d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ 2567d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ 257686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */ 2587d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ 259c0621acfSIngo Molnar #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ 2607d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ 2617d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ 2620b44cfb8SIngo Molnar #define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ 2630b44cfb8SIngo Molnar #define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ 2647d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ 265c0621acfSIngo Molnar #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ 2667d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ 2677d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ 2684053717aSArnaldo Carvalho de Melo #define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */ 2697d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ 2707d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ 2717d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ 2727d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ 2737d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ 2747d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ 2757d7d1bf1SArnaldo Carvalho de Melo 2760b44cfb8SIngo Molnar /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ 2770b44cfb8SIngo Molnar #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ 2780b44cfb8SIngo Molnar #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ 2790b44cfb8SIngo Molnar #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ 2800b44cfb8SIngo Molnar #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ 281b075c1d8SArnaldo Carvalho de Melo #define X86_FEATURE_XFD (10*32+ 4) /* "" eXtended Feature Disabling */ 2827d7d1bf1SArnaldo Carvalho de Melo 283686cbe9eSArnaldo Carvalho de Melo /* 284686cbe9eSArnaldo Carvalho de Melo * Extended auxiliary flags: Linux defined - for features scattered in various 285686cbe9eSArnaldo Carvalho de Melo * CPUID levels like 0xf, etc. 286686cbe9eSArnaldo Carvalho de Melo * 287686cbe9eSArnaldo Carvalho de Melo * Reuse free bits when adding new feature flags! 288686cbe9eSArnaldo Carvalho de Melo */ 289686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */ 290686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */ 291686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */ 292686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */ 2930ac10d87SArnaldo Carvalho de Melo #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */ 2940ac10d87SArnaldo Carvalho de Melo #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ 295e00a2d90SArnaldo Carvalho de Melo #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */ 29640a6bbf5SArnaldo Carvalho de Melo #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */ 2976faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */ 2986faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */ 299f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */ 300f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */ 301f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ 302f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */ 303f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */ 304f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ 305553de6e1SArnaldo Carvalho de Melo #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */ 30662ed93d1SArnaldo Carvalho de Melo #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ 3077d7d1bf1SArnaldo Carvalho de Melo 308686cbe9eSArnaldo Carvalho de Melo /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ 3091a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ 310686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ 3117d7d1bf1SArnaldo Carvalho de Melo 3120b44cfb8SIngo Molnar /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ 3137d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ 3147d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ 315643e345cSIngo Molnar #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ 316a717ab38SArnaldo Carvalho de Melo #define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */ 31786c22ab7SArnaldo Carvalho de Melo #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ 318a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ 319a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ 320a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ 32186c22ab7SArnaldo Carvalho de Melo #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */ 322e00a2d90SArnaldo Carvalho de Melo #define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */ 32332fdbd90SIngo Molnar #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ 324a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ 32532fdbd90SIngo Molnar #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ 326486e5ed8SArnaldo Carvalho de Melo #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ 327f098addbSArnaldo Carvalho de Melo #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ 3284b3f7644SArnaldo Carvalho de Melo #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ 3297d7d1bf1SArnaldo Carvalho de Melo 3300b44cfb8SIngo Molnar /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ 3317d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ 3327d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ 3337d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ 3347d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ 3357d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ 3367d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ 3377d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ 3387d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ 3397d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ 3407d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ 341d16d30f4SArnaldo Carvalho de Melo #define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */ 3427d7d1bf1SArnaldo Carvalho de Melo 3430b44cfb8SIngo Molnar /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ 3447d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ 3457d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ 3467d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ 3477d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ 3487d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ 3497d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ 3507d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ 3517d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ 3527d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ 3537d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ 3547d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ 355a2105f8aSArnaldo Carvalho de Melo #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ 356549a3976SIngo Molnar #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ 35762ed93d1SArnaldo Carvalho de Melo #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */ 3586faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ 3591a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */ 3607d7d1bf1SArnaldo Carvalho de Melo 3610b44cfb8SIngo Molnar /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ 362c0621acfSIngo Molnar #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ 3630b44cfb8SIngo Molnar #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ 3647d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ 3657d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ 366686cbe9eSArnaldo Carvalho de Melo #define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */ 3670b44cfb8SIngo Molnar #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ 3680b44cfb8SIngo Molnar #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ 3690b44cfb8SIngo Molnar #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ 3700b44cfb8SIngo Molnar #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ 3710b44cfb8SIngo Molnar #define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ 3720b44cfb8SIngo Molnar #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ 3735e2a146bSArnaldo Carvalho de Melo #define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */ 37406b35d93SPiotr Luc #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ 375f2ba3ee0SArnaldo Carvalho de Melo #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ 376c0621acfSIngo Molnar #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ 3776faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_BUS_LOCK_DETECT (16*32+24) /* Bus Lock detect */ 378605e71cdSArnaldo Carvalho de Melo #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */ 37965e259d5SArnaldo Carvalho de Melo #define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */ 38065e259d5SArnaldo Carvalho de Melo #define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */ 38140a6bbf5SArnaldo Carvalho de Melo #define X86_FEATURE_ENQCMD (16*32+29) /* ENQCMD and ENQCMDS instructions */ 382f93c789aSArnaldo Carvalho de Melo #define X86_FEATURE_SGX_LC (16*32+30) /* Software Guard Extensions Launch Control */ 3837d7d1bf1SArnaldo Carvalho de Melo 3840b44cfb8SIngo Molnar /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ 3857d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ 3867d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ 3877d7d1bf1SArnaldo Carvalho de Melo #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ 3887d7d1bf1SArnaldo Carvalho de Melo 3894053717aSArnaldo Carvalho de Melo /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ 3904053717aSArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ 3914053717aSArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ 39271dd6528SArnaldo Carvalho de Melo #define X86_FEATURE_FSRM (18*32+ 4) /* Fast Short Rep Mov */ 39340f1c039SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */ 39425ca7e5cSArnaldo Carvalho de Melo #define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */ 395b979540aSArnaldo Carvalho de Melo #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ 396cc200a7dSArnaldo Carvalho de Melo #define X86_FEATURE_RTM_ALWAYS_ABORT (18*32+11) /* "" RTM transaction always aborts */ 397949af89aSArnaldo Carvalho de Melo #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ 398dd4a5c22SArnaldo Carvalho de Melo #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ 3996faf64f5SArnaldo Carvalho de Melo #define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has CPUs of more than one type */ 40040a6bbf5SArnaldo Carvalho de Melo #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ 4015e2a146bSArnaldo Carvalho de Melo #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ 402dd4a5c22SArnaldo Carvalho de Melo #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ 4035ced8124SArnaldo Carvalho de Melo #define X86_FEATURE_IBT (18*32+20) /* Indirect Branch Tracking */ 404d16d30f4SArnaldo Carvalho de Melo #define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */ 4057f3905f0SArnaldo Carvalho de Melo #define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */ 406d16d30f4SArnaldo Carvalho de Melo #define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */ 407d16d30f4SArnaldo Carvalho de Melo #define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */ 4084053717aSArnaldo Carvalho de Melo #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ 4094053717aSArnaldo Carvalho de Melo #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ 410e24f14b0SDavid Woodhouse #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ 4114053717aSArnaldo Carvalho de Melo #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ 412e00a2d90SArnaldo Carvalho de Melo #define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */ 413a20d23bbSArnaldo Carvalho de Melo #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ 4144053717aSArnaldo Carvalho de Melo 4151a9bcaddSArnaldo Carvalho de Melo /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */ 4161a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_SME (19*32+ 0) /* AMD Secure Memory Encryption */ 4171a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ 4181a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ 4191a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ 4204b3f7644SArnaldo Carvalho de Melo #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ 4211a9bcaddSArnaldo Carvalho de Melo #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ 4221a9bcaddSArnaldo Carvalho de Melo 4237d7d1bf1SArnaldo Carvalho de Melo /* 4247d7d1bf1SArnaldo Carvalho de Melo * BUG word(s) 4257d7d1bf1SArnaldo Carvalho de Melo */ 4267d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG(x) (NCAPINTS*32 + (x)) 4277d7d1bf1SArnaldo Carvalho de Melo 4287d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ 4297d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ 4307d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ 4317d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ 4327d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ 4337d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ 4347d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ 4357d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ 4367d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ 4377d7d1bf1SArnaldo Carvalho de Melo #ifdef CONFIG_X86_32 4387d7d1bf1SArnaldo Carvalho de Melo /* 4397d7d1bf1SArnaldo Carvalho de Melo * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional 4407d7d1bf1SArnaldo Carvalho de Melo * to avoid confusion. 4417d7d1bf1SArnaldo Carvalho de Melo */ 4427d7d1bf1SArnaldo Carvalho de Melo #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ 4437d7d1bf1SArnaldo Carvalho de Melo #endif 444bebfb730SArnaldo Carvalho de Melo #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ 445bebfb730SArnaldo Carvalho de Melo #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ 446bebfb730SArnaldo Carvalho de Melo #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ 447c0621acfSIngo Molnar #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ 4485d64db29SArnaldo Carvalho de Melo #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ 4494053717aSArnaldo Carvalho de Melo #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ 4504053717aSArnaldo Carvalho de Melo #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ 451a20d23bbSArnaldo Carvalho de Melo #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ 452e24f14b0SDavid Woodhouse #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ 453b979540aSArnaldo Carvalho de Melo #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ 454b979540aSArnaldo Carvalho de Melo #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ 4550ac10d87SArnaldo Carvalho de Melo #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ 456a717ab38SArnaldo Carvalho de Melo #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ 457a717ab38SArnaldo Carvalho de Melo #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ 45825ca7e5cSArnaldo Carvalho de Melo #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */ 45951802186SPawan Gupta #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */ 460356edecaSArnaldo Carvalho de Melo #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */ 461356edecaSArnaldo Carvalho de Melo #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */ 462356edecaSArnaldo Carvalho de Melo #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */ 4630b44cfb8SIngo Molnar 4647d7d1bf1SArnaldo Carvalho de Melo #endif /* _ASM_X86_CPUFEATURES_H */ 465