1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * From PPR Vol 1 for AMD Family 19h Model 01h B1 4 * 55898 Rev 0.35 - Feb 5, 2021 5 */ 6 7 #include "msr-index.h" 8 9 /* 10 * IBS Hardware MSRs 11 */ 12 13 /* MSR 0xc0011030: IBS Fetch Control */ 14 union ibs_fetch_ctl { 15 __u64 val; 16 struct { 17 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */ 18 fetch_cnt:16, /* 16-31: instruction fetch count */ 19 fetch_lat:16, /* 32-47: instruction fetch latency */ 20 fetch_en:1, /* 48: instruction fetch enable */ 21 fetch_val:1, /* 49: instruction fetch valid */ 22 fetch_comp:1, /* 50: instruction fetch complete */ 23 ic_miss:1, /* 51: i-cache miss */ 24 phy_addr_valid:1,/* 52: physical address valid */ 25 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size 26 * (needs IbsPhyAddrValid) */ 27 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */ 28 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */ 29 rand_en:1, /* 57: random tagging enable */ 30 fetch_l2_miss:1,/* 58: L2 miss for sampled fetch 31 * (needs IbsFetchComp) */ 32 l3_miss_only:1, /* 59: Collect L3 miss samples only */ 33 fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */ 34 fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */ 35 reserved:2; /* 62-63: reserved */ 36 }; 37 }; 38 39 /* MSR 0xc0011033: IBS Execution Control */ 40 union ibs_op_ctl { 41 __u64 val; 42 struct { 43 __u64 opmaxcnt:16, /* 0-15: periodic op max. count */ 44 l3_miss_only:1, /* 16: Collect L3 miss samples only */ 45 op_en:1, /* 17: op sampling enable */ 46 op_val:1, /* 18: op sample valid */ 47 cnt_ctl:1, /* 19: periodic op counter control */ 48 opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */ 49 reserved0:5, /* 27-31: reserved */ 50 opcurcnt:27, /* 32-58: periodic op counter current count */ 51 reserved1:5; /* 59-63: reserved */ 52 }; 53 }; 54 55 /* MSR 0xc0011035: IBS Op Data 1 */ 56 union ibs_op_data { 57 __u64 val; 58 struct { 59 __u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */ 60 tag_to_ret_ctr:16, /* 15-31: op tag to retire count */ 61 reserved1:2, /* 32-33: reserved */ 62 op_return:1, /* 34: return op */ 63 op_brn_taken:1, /* 35: taken branch op */ 64 op_brn_misp:1, /* 36: mispredicted branch op */ 65 op_brn_ret:1, /* 37: branch op retired */ 66 op_rip_invalid:1, /* 38: RIP is invalid */ 67 op_brn_fuse:1, /* 39: fused branch op */ 68 op_microcode:1, /* 40: microcode op */ 69 reserved2:23; /* 41-63: reserved */ 70 }; 71 }; 72 73 /* MSR 0xc0011036: IBS Op Data 2 */ 74 union ibs_op_data2 { 75 __u64 val; 76 struct { 77 __u64 data_src_lo:3, /* 0-2: data source low */ 78 reserved0:1, /* 3: reserved */ 79 rmt_node:1, /* 4: destination node */ 80 cache_hit_st:1, /* 5: cache hit state */ 81 data_src_hi:2, /* 6-7: data source high */ 82 reserved1:56; /* 8-63: reserved */ 83 }; 84 }; 85 86 /* MSR 0xc0011037: IBS Op Data 3 */ 87 union ibs_op_data3 { 88 __u64 val; 89 struct { 90 __u64 ld_op:1, /* 0: load op */ 91 st_op:1, /* 1: store op */ 92 dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */ 93 dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */ 94 dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */ 95 dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */ 96 dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */ 97 dc_miss:1, /* 7: data cache miss */ 98 dc_mis_acc:1, /* 8: misaligned access */ 99 reserved:4, /* 9-12: reserved */ 100 dc_wc_mem_acc:1, /* 13: write combining memory access */ 101 dc_uc_mem_acc:1, /* 14: uncacheable memory access */ 102 dc_locked_op:1, /* 15: locked operation */ 103 dc_miss_no_mab_alloc:1, /* 16: DC miss with no MAB allocated */ 104 dc_lin_addr_valid:1, /* 17: data cache linear address valid */ 105 dc_phy_addr_valid:1, /* 18: data cache physical address valid */ 106 dc_l2_tlb_hit_1g:1, /* 19: data cache L2 hit in 1GB page */ 107 l2_miss:1, /* 20: L2 cache miss */ 108 sw_pf:1, /* 21: software prefetch */ 109 op_mem_width:4, /* 22-25: load/store size in bytes */ 110 op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */ 111 dc_miss_lat:16, /* 32-47: data cache miss latency */ 112 tlb_refill_lat:16; /* 48-63: L1 TLB refill latency */ 113 }; 114 }; 115 116 /* MSR 0xc001103c: IBS Fetch Control Extended */ 117 union ic_ibs_extd_ctl { 118 __u64 val; 119 struct { 120 __u64 itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */ 121 reserved:48; /* 16-63: reserved */ 122 }; 123 }; 124 125 /* 126 * IBS driver related 127 */ 128 129 struct perf_ibs_data { 130 u32 size; 131 union { 132 u32 data[0]; /* data buffer starts here */ 133 u32 caps; 134 }; 135 u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX]; 136 }; 137