1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2dd7bd109SArnaldo Carvalho de Melo /* 3dd7bd109SArnaldo Carvalho de Melo * This file is subject to the terms and conditions of the GNU General Public 4dd7bd109SArnaldo Carvalho de Melo * License. See the file "COPYING" in the main directory of this archive 5dd7bd109SArnaldo Carvalho de Melo * for more details. 6dd7bd109SArnaldo Carvalho de Melo * 7dd7bd109SArnaldo Carvalho de Melo * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 8dd7bd109SArnaldo Carvalho de Melo * Copyright (C) 2013 Cavium, Inc. 9dd7bd109SArnaldo Carvalho de Melo * Authors: Sanjay Lal <sanjayl@kymasys.com> 10dd7bd109SArnaldo Carvalho de Melo */ 11dd7bd109SArnaldo Carvalho de Melo 12dd7bd109SArnaldo Carvalho de Melo #ifndef __LINUX_KVM_MIPS_H 13dd7bd109SArnaldo Carvalho de Melo #define __LINUX_KVM_MIPS_H 14dd7bd109SArnaldo Carvalho de Melo 15dd7bd109SArnaldo Carvalho de Melo #include <linux/types.h> 16dd7bd109SArnaldo Carvalho de Melo 17dd7bd109SArnaldo Carvalho de Melo /* 18dd7bd109SArnaldo Carvalho de Melo * KVM MIPS specific structures and definitions. 19dd7bd109SArnaldo Carvalho de Melo * 20dd7bd109SArnaldo Carvalho de Melo * Some parts derived from the x86 version of this file. 21dd7bd109SArnaldo Carvalho de Melo */ 22dd7bd109SArnaldo Carvalho de Melo 23dd7bd109SArnaldo Carvalho de Melo /* 24dd7bd109SArnaldo Carvalho de Melo * for KVM_GET_REGS and KVM_SET_REGS 25dd7bd109SArnaldo Carvalho de Melo * 26dd7bd109SArnaldo Carvalho de Melo * If Config[AT] is zero (32-bit CPU), the register contents are 27dd7bd109SArnaldo Carvalho de Melo * stored in the lower 32-bits of the struct kvm_regs fields and sign 28dd7bd109SArnaldo Carvalho de Melo * extended to 64-bits. 29dd7bd109SArnaldo Carvalho de Melo */ 30dd7bd109SArnaldo Carvalho de Melo struct kvm_regs { 31dd7bd109SArnaldo Carvalho de Melo /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 32dd7bd109SArnaldo Carvalho de Melo __u64 gpr[32]; 33dd7bd109SArnaldo Carvalho de Melo __u64 hi; 34dd7bd109SArnaldo Carvalho de Melo __u64 lo; 35dd7bd109SArnaldo Carvalho de Melo __u64 pc; 36dd7bd109SArnaldo Carvalho de Melo }; 37dd7bd109SArnaldo Carvalho de Melo 38dd7bd109SArnaldo Carvalho de Melo /* 39dd7bd109SArnaldo Carvalho de Melo * for KVM_GET_FPU and KVM_SET_FPU 40dd7bd109SArnaldo Carvalho de Melo */ 41dd7bd109SArnaldo Carvalho de Melo struct kvm_fpu { 42dd7bd109SArnaldo Carvalho de Melo }; 43dd7bd109SArnaldo Carvalho de Melo 44dd7bd109SArnaldo Carvalho de Melo 45dd7bd109SArnaldo Carvalho de Melo /* 46dd7bd109SArnaldo Carvalho de Melo * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various 47dd7bd109SArnaldo Carvalho de Melo * registers. The id field is broken down as follows: 48dd7bd109SArnaldo Carvalho de Melo * 49dd7bd109SArnaldo Carvalho de Melo * bits[63..52] - As per linux/kvm.h 50dd7bd109SArnaldo Carvalho de Melo * bits[51..32] - Must be zero. 51dd7bd109SArnaldo Carvalho de Melo * bits[31..16] - Register set. 52dd7bd109SArnaldo Carvalho de Melo * 53dd7bd109SArnaldo Carvalho de Melo * Register set = 0: GP registers from kvm_regs (see definitions below). 54dd7bd109SArnaldo Carvalho de Melo * 55dd7bd109SArnaldo Carvalho de Melo * Register set = 1: CP0 registers. 56dd7bd109SArnaldo Carvalho de Melo * bits[15..8] - Must be zero. 57dd7bd109SArnaldo Carvalho de Melo * bits[7..3] - Register 'rd' index. 58dd7bd109SArnaldo Carvalho de Melo * bits[2..0] - Register 'sel' index. 59dd7bd109SArnaldo Carvalho de Melo * 60dd7bd109SArnaldo Carvalho de Melo * Register set = 2: KVM specific registers (see definitions below). 61dd7bd109SArnaldo Carvalho de Melo * 62dd7bd109SArnaldo Carvalho de Melo * Register set = 3: FPU / MSA registers (see definitions below). 63dd7bd109SArnaldo Carvalho de Melo * 64dd7bd109SArnaldo Carvalho de Melo * Other sets registers may be added in the future. Each set would 65dd7bd109SArnaldo Carvalho de Melo * have its own identifier in bits[31..16]. 66dd7bd109SArnaldo Carvalho de Melo */ 67dd7bd109SArnaldo Carvalho de Melo 68dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL) 69dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL) 70dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL) 71dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL) 72dd7bd109SArnaldo Carvalho de Melo 73dd7bd109SArnaldo Carvalho de Melo 74dd7bd109SArnaldo Carvalho de Melo /* 75dd7bd109SArnaldo Carvalho de Melo * KVM_REG_MIPS_GP - General purpose registers from kvm_regs. 76dd7bd109SArnaldo Carvalho de Melo */ 77dd7bd109SArnaldo Carvalho de Melo 78dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0) 79dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1) 80dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2) 81dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3) 82dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4) 83dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5) 84dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6) 85dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7) 86dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8) 87dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9) 88dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10) 89dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11) 90dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12) 91dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13) 92dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14) 93dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15) 94dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16) 95dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17) 96dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18) 97dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19) 98dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20) 99dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21) 100dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22) 101dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23) 102dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24) 103dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25) 104dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26) 105dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27) 106dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28) 107dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29) 108dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30) 109dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31) 110dd7bd109SArnaldo Carvalho de Melo 111dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32) 112dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33) 113dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34) 114dd7bd109SArnaldo Carvalho de Melo 115dd7bd109SArnaldo Carvalho de Melo 116dd7bd109SArnaldo Carvalho de Melo /* 117dd7bd109SArnaldo Carvalho de Melo * KVM_REG_MIPS_KVM - KVM specific control registers. 118dd7bd109SArnaldo Carvalho de Melo */ 119dd7bd109SArnaldo Carvalho de Melo 120dd7bd109SArnaldo Carvalho de Melo /* 121dd7bd109SArnaldo Carvalho de Melo * CP0_Count control 122dd7bd109SArnaldo Carvalho de Melo * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now 123dd7bd109SArnaldo Carvalho de Melo * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer 124dd7bd109SArnaldo Carvalho de Melo * interrupts since COUNT_RESUME 125dd7bd109SArnaldo Carvalho de Melo * This can be used to freeze the timer to get a consistent snapshot of 126dd7bd109SArnaldo Carvalho de Melo * the CP0_Count and timer interrupt pending state, while also resuming 127dd7bd109SArnaldo Carvalho de Melo * safely without losing time or guest timer interrupts. 128dd7bd109SArnaldo Carvalho de Melo * Other: Reserved, do not change. 129dd7bd109SArnaldo Carvalho de Melo */ 130dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0) 131dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 132dd7bd109SArnaldo Carvalho de Melo 133dd7bd109SArnaldo Carvalho de Melo /* 134dd7bd109SArnaldo Carvalho de Melo * CP0_Count resume monotonic nanoseconds 135dd7bd109SArnaldo Carvalho de Melo * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master 136dd7bd109SArnaldo Carvalho de Melo * disable). Any reads and writes of Count related registers while 137dd7bd109SArnaldo Carvalho de Melo * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is 138dd7bd109SArnaldo Carvalho de Melo * cleared again (master enable) any timer interrupts since this time will be 139dd7bd109SArnaldo Carvalho de Melo * emulated. 140dd7bd109SArnaldo Carvalho de Melo * Modifications to times in the future are rejected. 141dd7bd109SArnaldo Carvalho de Melo */ 142dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1) 143dd7bd109SArnaldo Carvalho de Melo /* 144dd7bd109SArnaldo Carvalho de Melo * CP0_Count rate in Hz 145dd7bd109SArnaldo Carvalho de Melo * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without 146dd7bd109SArnaldo Carvalho de Melo * discontinuities in CP0_Count. 147dd7bd109SArnaldo Carvalho de Melo */ 148dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2) 149dd7bd109SArnaldo Carvalho de Melo 150dd7bd109SArnaldo Carvalho de Melo 151dd7bd109SArnaldo Carvalho de Melo /* 152dd7bd109SArnaldo Carvalho de Melo * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers. 153dd7bd109SArnaldo Carvalho de Melo * 154dd7bd109SArnaldo Carvalho de Melo * bits[15..8] - Register subset (see definitions below). 155dd7bd109SArnaldo Carvalho de Melo * bits[7..5] - Must be zero. 156dd7bd109SArnaldo Carvalho de Melo * bits[4..0] - Register number within register subset. 157dd7bd109SArnaldo Carvalho de Melo */ 158dd7bd109SArnaldo Carvalho de Melo 159dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL) 160dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL) 161dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL) 162dd7bd109SArnaldo Carvalho de Melo 163dd7bd109SArnaldo Carvalho de Melo /* 164dd7bd109SArnaldo Carvalho de Melo * KVM_REG_MIPS_FPR - Floating point / Vector registers. 165dd7bd109SArnaldo Carvalho de Melo */ 166dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n)) 167dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n)) 168dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n)) 169dd7bd109SArnaldo Carvalho de Melo 170dd7bd109SArnaldo Carvalho de Melo /* 171dd7bd109SArnaldo Carvalho de Melo * KVM_REG_MIPS_FCR - Floating point control registers. 172dd7bd109SArnaldo Carvalho de Melo */ 173dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0) 174dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31) 175dd7bd109SArnaldo Carvalho de Melo 176dd7bd109SArnaldo Carvalho de Melo /* 177dd7bd109SArnaldo Carvalho de Melo * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers. 178dd7bd109SArnaldo Carvalho de Melo */ 179dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0) 180dd7bd109SArnaldo Carvalho de Melo #define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1) 181dd7bd109SArnaldo Carvalho de Melo 182dd7bd109SArnaldo Carvalho de Melo 183dd7bd109SArnaldo Carvalho de Melo /* 184dd7bd109SArnaldo Carvalho de Melo * KVM MIPS specific structures and definitions 185dd7bd109SArnaldo Carvalho de Melo * 186dd7bd109SArnaldo Carvalho de Melo */ 187dd7bd109SArnaldo Carvalho de Melo struct kvm_debug_exit_arch { 188dd7bd109SArnaldo Carvalho de Melo __u64 epc; 189dd7bd109SArnaldo Carvalho de Melo }; 190dd7bd109SArnaldo Carvalho de Melo 191dd7bd109SArnaldo Carvalho de Melo /* for KVM_SET_GUEST_DEBUG */ 192dd7bd109SArnaldo Carvalho de Melo struct kvm_guest_debug_arch { 193dd7bd109SArnaldo Carvalho de Melo }; 194dd7bd109SArnaldo Carvalho de Melo 195dd7bd109SArnaldo Carvalho de Melo /* definition of registers in kvm_run */ 196dd7bd109SArnaldo Carvalho de Melo struct kvm_sync_regs { 197dd7bd109SArnaldo Carvalho de Melo }; 198dd7bd109SArnaldo Carvalho de Melo 199dd7bd109SArnaldo Carvalho de Melo /* dummy definition */ 200dd7bd109SArnaldo Carvalho de Melo struct kvm_sregs { 201dd7bd109SArnaldo Carvalho de Melo }; 202dd7bd109SArnaldo Carvalho de Melo 203dd7bd109SArnaldo Carvalho de Melo struct kvm_mips_interrupt { 204dd7bd109SArnaldo Carvalho de Melo /* in */ 205dd7bd109SArnaldo Carvalho de Melo __u32 cpu; 206dd7bd109SArnaldo Carvalho de Melo __u32 irq; 207dd7bd109SArnaldo Carvalho de Melo }; 208dd7bd109SArnaldo Carvalho de Melo 209dd7bd109SArnaldo Carvalho de Melo #endif /* __LINUX_KVM_MIPS_H */ 210