1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __ARM_KVM_H__ 24 #define __ARM_KVM_H__ 25 26 #define KVM_SPSR_EL1 0 27 #define KVM_SPSR_SVC KVM_SPSR_EL1 28 #define KVM_SPSR_ABT 1 29 #define KVM_SPSR_UND 2 30 #define KVM_SPSR_IRQ 3 31 #define KVM_SPSR_FIQ 4 32 #define KVM_NR_SPSR 5 33 34 #ifndef __ASSEMBLY__ 35 #include <linux/psci.h> 36 #include <linux/types.h> 37 #include <asm/ptrace.h> 38 #include <asm/sve_context.h> 39 40 #define __KVM_HAVE_GUEST_DEBUG 41 #define __KVM_HAVE_IRQ_LINE 42 #define __KVM_HAVE_READONLY_MEM 43 #define __KVM_HAVE_VCPU_EVENTS 44 45 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 46 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 47 48 #define KVM_REG_SIZE(id) \ 49 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 50 51 struct kvm_regs { 52 struct user_pt_regs regs; /* sp = sp_el0 */ 53 54 __u64 sp_el1; 55 __u64 elr_el1; 56 57 __u64 spsr[KVM_NR_SPSR]; 58 59 struct user_fpsimd_state fp_regs; 60 }; 61 62 /* 63 * Supported CPU Targets - Adding a new target type is not recommended, 64 * unless there are some special registers not supported by the 65 * genericv8 syreg table. 66 */ 67 #define KVM_ARM_TARGET_AEM_V8 0 68 #define KVM_ARM_TARGET_FOUNDATION_V8 1 69 #define KVM_ARM_TARGET_CORTEX_A57 2 70 #define KVM_ARM_TARGET_XGENE_POTENZA 3 71 #define KVM_ARM_TARGET_CORTEX_A53 4 72 /* Generic ARM v8 target */ 73 #define KVM_ARM_TARGET_GENERIC_V8 5 74 75 #define KVM_ARM_NUM_TARGETS 6 76 77 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 78 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 79 #define KVM_ARM_DEVICE_TYPE_MASK GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ 80 KVM_ARM_DEVICE_TYPE_SHIFT) 81 #define KVM_ARM_DEVICE_ID_SHIFT 16 82 #define KVM_ARM_DEVICE_ID_MASK GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ 83 KVM_ARM_DEVICE_ID_SHIFT) 84 85 /* Supported device IDs */ 86 #define KVM_ARM_DEVICE_VGIC_V2 0 87 88 /* Supported VGIC address types */ 89 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 90 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 91 92 #define KVM_VGIC_V2_DIST_SIZE 0x1000 93 #define KVM_VGIC_V2_CPU_SIZE 0x2000 94 95 /* Supported VGICv3 address types */ 96 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 97 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 98 #define KVM_VGIC_ITS_ADDR_TYPE 4 99 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 100 101 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 102 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 103 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 104 105 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 106 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 107 #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 108 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 109 #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 110 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 111 #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 112 113 struct kvm_vcpu_init { 114 __u32 target; 115 __u32 features[7]; 116 }; 117 118 struct kvm_sregs { 119 }; 120 121 struct kvm_fpu { 122 }; 123 124 /* 125 * See v8 ARM ARM D7.3: Debug Registers 126 * 127 * The architectural limit is 16 debug registers of each type although 128 * in practice there are usually less (see ID_AA64DFR0_EL1). 129 * 130 * Although the control registers are architecturally defined as 32 131 * bits wide we use a 64 bit structure here to keep parity with 132 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 133 * 64 bit values. It also allows for the possibility of the 134 * architecture expanding the control registers without having to 135 * change the userspace ABI. 136 */ 137 #define KVM_ARM_MAX_DBG_REGS 16 138 struct kvm_guest_debug_arch { 139 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 140 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 141 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 142 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 143 }; 144 145 #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 146 struct kvm_debug_exit_arch { 147 __u32 hsr; 148 __u32 hsr_high; /* ESR_EL2[61:32] */ 149 __u64 far; /* used for watchpoints */ 150 }; 151 152 /* 153 * Architecture specific defines for kvm_guest_debug->control 154 */ 155 156 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 157 #define KVM_GUESTDBG_USE_HW (1 << 17) 158 159 struct kvm_sync_regs { 160 /* Used with KVM_CAP_ARM_USER_IRQ */ 161 __u64 device_irq_level; 162 }; 163 164 /* 165 * PMU filter structure. Describe a range of events with a particular 166 * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER. 167 */ 168 struct kvm_pmu_event_filter { 169 __u16 base_event; 170 __u16 nevents; 171 172 #define KVM_PMU_EVENT_ALLOW 0 173 #define KVM_PMU_EVENT_DENY 1 174 175 __u8 action; 176 __u8 pad[3]; 177 }; 178 179 /* for KVM_GET/SET_VCPU_EVENTS */ 180 struct kvm_vcpu_events { 181 struct { 182 __u8 serror_pending; 183 __u8 serror_has_esr; 184 __u8 ext_dabt_pending; 185 /* Align it to 8 bytes */ 186 __u8 pad[5]; 187 __u64 serror_esr; 188 } exception; 189 __u32 reserved[12]; 190 }; 191 192 struct kvm_arm_copy_mte_tags { 193 __u64 guest_ipa; 194 __u64 length; 195 void __user *addr; 196 __u64 flags; 197 __u64 reserved[2]; 198 }; 199 200 #define KVM_ARM_TAGS_TO_GUEST 0 201 #define KVM_ARM_TAGS_FROM_GUEST 1 202 203 /* If you need to interpret the index values, here is the key: */ 204 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 205 #define KVM_REG_ARM_COPROC_SHIFT 16 206 207 /* Normal registers are mapped as coprocessor 16. */ 208 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 209 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 210 211 /* Some registers need more space to represent values. */ 212 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 213 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 214 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 215 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 216 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 217 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 218 219 /* AArch64 system registers */ 220 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 221 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 222 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 223 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 224 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 225 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 226 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 227 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 228 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 229 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 230 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 231 232 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 233 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 234 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 235 236 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 237 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 238 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 239 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 240 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 241 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 242 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 243 244 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 245 246 /* Physical Timer EL0 Registers */ 247 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 248 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 249 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 250 251 /* 252 * EL0 Virtual Timer Registers 253 * 254 * WARNING: 255 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 256 * with the appropriate register encodings. Their values have been 257 * accidentally swapped. As this is set API, the definitions here 258 * must be used, rather than ones derived from the encodings. 259 */ 260 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 261 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 262 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 263 264 /* KVM-as-firmware specific pseudo-registers */ 265 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 266 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 267 KVM_REG_ARM_FW | ((r) & 0xffff)) 268 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 269 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 270 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 271 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 272 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 273 274 /* 275 * Only two states can be presented by the host kernel: 276 * - NOT_REQUIRED: the guest doesn't need to do anything 277 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available) 278 * 279 * All the other values are deprecated. The host still accepts all 280 * values (they are ABI), but will narrow them to the above two. 281 */ 282 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 283 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 284 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 285 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 286 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 287 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 288 289 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 290 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 291 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 292 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 293 294 /* SVE registers */ 295 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 296 297 /* Z- and P-regs occupy blocks at the following offsets within this range: */ 298 #define KVM_REG_ARM64_SVE_ZREG_BASE 0 299 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 300 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 301 302 #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 303 #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 304 305 #define KVM_ARM64_SVE_MAX_SLICES 32 306 307 #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 308 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 309 KVM_REG_SIZE_U2048 | \ 310 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 311 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 312 313 #define KVM_REG_ARM64_SVE_PREG(n, i) \ 314 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 315 KVM_REG_SIZE_U256 | \ 316 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 317 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 318 319 #define KVM_REG_ARM64_SVE_FFR(i) \ 320 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 321 KVM_REG_SIZE_U256 | \ 322 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 323 324 /* 325 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 326 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 327 * invariant layout which differs from the layout used for the FPSIMD 328 * V-registers on big-endian systems: see sigcontext.h for more explanation. 329 */ 330 331 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 332 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 333 334 /* Vector lengths pseudo-register: */ 335 #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 336 KVM_REG_SIZE_U512 | 0xffff) 337 #define KVM_ARM64_SVE_VLS_WORDS \ 338 ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 339 340 /* Bitmap feature firmware registers */ 341 #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 342 #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 343 KVM_REG_ARM_FW_FEAT_BMAP | \ 344 ((r) & 0xffff)) 345 346 #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 347 348 enum { 349 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 350 #ifdef __KERNEL__ 351 KVM_REG_ARM_STD_BMAP_BIT_COUNT, 352 #endif 353 }; 354 355 #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 356 357 enum { 358 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 359 #ifdef __KERNEL__ 360 KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT, 361 #endif 362 }; 363 364 #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 365 366 enum { 367 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 368 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 369 #ifdef __KERNEL__ 370 KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, 371 #endif 372 }; 373 374 /* Device Control API: ARM VGIC */ 375 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 376 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 377 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 378 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 379 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 380 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 381 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 382 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 383 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 384 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 385 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 386 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 387 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 388 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 389 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 390 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 391 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 392 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 393 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 394 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 395 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 396 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 397 398 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 399 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 400 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 401 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 402 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 403 404 /* Device Control API on vcpu fd */ 405 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 406 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 407 #define KVM_ARM_VCPU_PMU_V3_INIT 1 408 #define KVM_ARM_VCPU_PMU_V3_FILTER 2 409 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 410 #define KVM_ARM_VCPU_TIMER_CTRL 1 411 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 412 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 413 #define KVM_ARM_VCPU_PVTIME_CTRL 2 414 #define KVM_ARM_VCPU_PVTIME_IPA 0 415 416 /* KVM_IRQ_LINE irq field index values */ 417 #define KVM_ARM_IRQ_VCPU2_SHIFT 28 418 #define KVM_ARM_IRQ_VCPU2_MASK 0xf 419 #define KVM_ARM_IRQ_TYPE_SHIFT 24 420 #define KVM_ARM_IRQ_TYPE_MASK 0xf 421 #define KVM_ARM_IRQ_VCPU_SHIFT 16 422 #define KVM_ARM_IRQ_VCPU_MASK 0xff 423 #define KVM_ARM_IRQ_NUM_SHIFT 0 424 #define KVM_ARM_IRQ_NUM_MASK 0xffff 425 426 /* irq_type field */ 427 #define KVM_ARM_IRQ_TYPE_CPU 0 428 #define KVM_ARM_IRQ_TYPE_SPI 1 429 #define KVM_ARM_IRQ_TYPE_PPI 2 430 431 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 432 #define KVM_ARM_IRQ_CPU_IRQ 0 433 #define KVM_ARM_IRQ_CPU_FIQ 1 434 435 /* 436 * This used to hold the highest supported SPI, but it is now obsolete 437 * and only here to provide source code level compatibility with older 438 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 439 */ 440 #ifndef __KERNEL__ 441 #define KVM_ARM_IRQ_GIC_MAX 127 442 #endif 443 444 /* One single KVM irqchip, ie. the VGIC */ 445 #define KVM_NR_IRQCHIPS 1 446 447 /* PSCI interface */ 448 #define KVM_PSCI_FN_BASE 0x95c1ba5e 449 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 450 451 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 452 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 453 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 454 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 455 456 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 457 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 458 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 459 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 460 461 /* arm64-specific kvm_run::system_event flags */ 462 /* 463 * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call. 464 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET. 465 */ 466 #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 467 468 /* run->fail_entry.hardware_entry_failure_reason codes. */ 469 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 470 471 #endif 472 473 #endif /* __ARM_KVM_H__ */ 474