1 /* 2 * intel_hdmi_audio.c - Intel HDMI audio driver 3 * 4 * Copyright (C) 2016 Intel Corp 5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 6 * Ramesh Babu K V <ramesh.babu@intel.com> 7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 8 * Jerome Anand <jerome.anand@intel.com> 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 21 * ALSA driver for Intel HDMI audio 22 */ 23 24 #include <linux/types.h> 25 #include <linux/platform_device.h> 26 #include <linux/io.h> 27 #include <linux/slab.h> 28 #include <linux/module.h> 29 #include <linux/interrupt.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/delay.h> 33 #include <asm/set_memory.h> 34 #include <sound/core.h> 35 #include <sound/asoundef.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/initval.h> 39 #include <sound/control.h> 40 #include <sound/jack.h> 41 #include <drm/drm_edid.h> 42 #include <drm/intel_lpe_audio.h> 43 #include "intel_hdmi_audio.h" 44 45 #define for_each_pipe(card_ctx, pipe) \ 46 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) 47 #define for_each_port(card_ctx, port) \ 48 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) 49 50 /*standard module options for ALSA. This module supports only one card*/ 51 static int hdmi_card_index = SNDRV_DEFAULT_IDX1; 52 static char *hdmi_card_id = SNDRV_DEFAULT_STR1; 53 54 module_param_named(index, hdmi_card_index, int, 0444); 55 MODULE_PARM_DESC(index, 56 "Index value for INTEL Intel HDMI Audio controller."); 57 module_param_named(id, hdmi_card_id, charp, 0444); 58 MODULE_PARM_DESC(id, 59 "ID string for INTEL Intel HDMI Audio controller."); 60 61 /* 62 * ELD SA bits in the CEA Speaker Allocation data block 63 */ 64 static const int eld_speaker_allocation_bits[] = { 65 [0] = FL | FR, 66 [1] = LFE, 67 [2] = FC, 68 [3] = RL | RR, 69 [4] = RC, 70 [5] = FLC | FRC, 71 [6] = RLC | RRC, 72 /* the following are not defined in ELD yet */ 73 [7] = 0, 74 }; 75 76 /* 77 * This is an ordered list! 78 * 79 * The preceding ones have better chances to be selected by 80 * hdmi_channel_allocation(). 81 */ 82 static struct cea_channel_speaker_allocation channel_allocations[] = { 83 /* channel: 7 6 5 4 3 2 1 0 */ 84 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 85 /* 2.1 */ 86 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 87 /* Dolby Surround */ 88 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 89 /* surround40 */ 90 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 91 /* surround41 */ 92 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 93 /* surround50 */ 94 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 95 /* surround51 */ 96 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 97 /* 6.1 */ 98 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 99 /* surround71 */ 100 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 101 102 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 103 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 104 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 105 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 106 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 107 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 108 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 109 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 110 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 111 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 112 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 113 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 114 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 115 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 116 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 117 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 118 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 119 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 120 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 121 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 122 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 123 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 124 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 125 }; 126 127 static const struct channel_map_table map_tables[] = { 128 { SNDRV_CHMAP_FL, 0x00, FL }, 129 { SNDRV_CHMAP_FR, 0x01, FR }, 130 { SNDRV_CHMAP_RL, 0x04, RL }, 131 { SNDRV_CHMAP_RR, 0x05, RR }, 132 { SNDRV_CHMAP_LFE, 0x02, LFE }, 133 { SNDRV_CHMAP_FC, 0x03, FC }, 134 { SNDRV_CHMAP_RLC, 0x06, RLC }, 135 { SNDRV_CHMAP_RRC, 0x07, RRC }, 136 {} /* terminator */ 137 }; 138 139 /* hardware capability structure */ 140 static const struct snd_pcm_hardware had_pcm_hardware = { 141 .info = (SNDRV_PCM_INFO_INTERLEAVED | 142 SNDRV_PCM_INFO_MMAP | 143 SNDRV_PCM_INFO_MMAP_VALID | 144 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 145 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 146 SNDRV_PCM_FMTBIT_S24_LE | 147 SNDRV_PCM_FMTBIT_S32_LE), 148 .rates = SNDRV_PCM_RATE_32000 | 149 SNDRV_PCM_RATE_44100 | 150 SNDRV_PCM_RATE_48000 | 151 SNDRV_PCM_RATE_88200 | 152 SNDRV_PCM_RATE_96000 | 153 SNDRV_PCM_RATE_176400 | 154 SNDRV_PCM_RATE_192000, 155 .rate_min = HAD_MIN_RATE, 156 .rate_max = HAD_MAX_RATE, 157 .channels_min = HAD_MIN_CHANNEL, 158 .channels_max = HAD_MAX_CHANNEL, 159 .buffer_bytes_max = HAD_MAX_BUFFER, 160 .period_bytes_min = HAD_MIN_PERIOD_BYTES, 161 .period_bytes_max = HAD_MAX_PERIOD_BYTES, 162 .periods_min = HAD_MIN_PERIODS, 163 .periods_max = HAD_MAX_PERIODS, 164 .fifo_size = HAD_FIFO_SIZE, 165 }; 166 167 /* Get the active PCM substream; 168 * Call had_substream_put() for unreferecing. 169 * Don't call this inside had_spinlock, as it takes by itself 170 */ 171 static struct snd_pcm_substream * 172 had_substream_get(struct snd_intelhad *intelhaddata) 173 { 174 struct snd_pcm_substream *substream; 175 unsigned long flags; 176 177 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 178 substream = intelhaddata->stream_info.substream; 179 if (substream) 180 intelhaddata->stream_info.substream_refcount++; 181 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 182 return substream; 183 } 184 185 /* Unref the active PCM substream; 186 * Don't call this inside had_spinlock, as it takes by itself 187 */ 188 static void had_substream_put(struct snd_intelhad *intelhaddata) 189 { 190 unsigned long flags; 191 192 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 193 intelhaddata->stream_info.substream_refcount--; 194 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 195 } 196 197 static u32 had_config_offset(int pipe) 198 { 199 switch (pipe) { 200 default: 201 case 0: 202 return AUDIO_HDMI_CONFIG_A; 203 case 1: 204 return AUDIO_HDMI_CONFIG_B; 205 case 2: 206 return AUDIO_HDMI_CONFIG_C; 207 } 208 } 209 210 /* Register access functions */ 211 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, 212 int pipe, u32 reg) 213 { 214 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); 215 } 216 217 static void had_write_register_raw(struct snd_intelhad_card *card_ctx, 218 int pipe, u32 reg, u32 val) 219 { 220 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); 221 } 222 223 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) 224 { 225 if (!ctx->connected) 226 *val = 0; 227 else 228 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); 229 } 230 231 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) 232 { 233 if (ctx->connected) 234 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); 235 } 236 237 /* 238 * enable / disable audio configuration 239 * 240 * The normal read/modify should not directly be used on VLV2 for 241 * updating AUD_CONFIG register. 242 * This is because: 243 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 244 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always 245 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the 246 * register. This field should be 1xy binary for configuration with 6 or 247 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) 248 * causes the "channels" field to be updated as 0xy binary resulting in 249 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with 250 * appropriate value when doing read-modify of AUD_CONFIG register. 251 */ 252 static void had_enable_audio(struct snd_intelhad *intelhaddata, 253 bool enable) 254 { 255 /* update the cached value */ 256 intelhaddata->aud_config.regx.aud_en = enable; 257 had_write_register(intelhaddata, AUD_CONFIG, 258 intelhaddata->aud_config.regval); 259 } 260 261 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ 262 static void had_ack_irqs(struct snd_intelhad *ctx) 263 { 264 u32 status_reg; 265 266 if (!ctx->connected) 267 return; 268 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 269 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 270 had_write_register(ctx, AUD_HDMI_STATUS, status_reg); 271 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 272 } 273 274 /* Reset buffer pointers */ 275 static void had_reset_audio(struct snd_intelhad *intelhaddata) 276 { 277 had_write_register(intelhaddata, AUD_HDMI_STATUS, 278 AUD_HDMI_STATUSG_MASK_FUNCRST); 279 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); 280 } 281 282 /* 283 * initialize audio channel status registers 284 * This function is called in the prepare callback 285 */ 286 static int had_prog_status_reg(struct snd_pcm_substream *substream, 287 struct snd_intelhad *intelhaddata) 288 { 289 union aud_cfg cfg_val = {.regval = 0}; 290 union aud_ch_status_0 ch_stat0 = {.regval = 0}; 291 union aud_ch_status_1 ch_stat1 = {.regval = 0}; 292 293 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & 294 IEC958_AES0_NONAUDIO) >> 1; 295 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & 296 IEC958_AES3_CON_CLOCK) >> 4; 297 cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id; 298 299 switch (substream->runtime->rate) { 300 case AUD_SAMPLE_RATE_32: 301 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; 302 break; 303 304 case AUD_SAMPLE_RATE_44_1: 305 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; 306 break; 307 case AUD_SAMPLE_RATE_48: 308 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; 309 break; 310 case AUD_SAMPLE_RATE_88_2: 311 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; 312 break; 313 case AUD_SAMPLE_RATE_96: 314 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; 315 break; 316 case AUD_SAMPLE_RATE_176_4: 317 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; 318 break; 319 case AUD_SAMPLE_RATE_192: 320 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; 321 break; 322 323 default: 324 /* control should never come here */ 325 return -EINVAL; 326 } 327 328 had_write_register(intelhaddata, 329 AUD_CH_STATUS_0, ch_stat0.regval); 330 331 switch (substream->runtime->format) { 332 case SNDRV_PCM_FORMAT_S16_LE: 333 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; 334 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; 335 break; 336 case SNDRV_PCM_FORMAT_S24_LE: 337 case SNDRV_PCM_FORMAT_S32_LE: 338 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; 339 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; 340 break; 341 default: 342 return -EINVAL; 343 } 344 345 had_write_register(intelhaddata, 346 AUD_CH_STATUS_1, ch_stat1.regval); 347 return 0; 348 } 349 350 /* 351 * function to initialize audio 352 * registers and buffer confgiuration registers 353 * This function is called in the prepare callback 354 */ 355 static int had_init_audio_ctrl(struct snd_pcm_substream *substream, 356 struct snd_intelhad *intelhaddata) 357 { 358 union aud_cfg cfg_val = {.regval = 0}; 359 union aud_buf_config buf_cfg = {.regval = 0}; 360 u8 channels; 361 362 had_prog_status_reg(substream, intelhaddata); 363 364 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; 365 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; 366 buf_cfg.regx.aud_delay = 0; 367 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); 368 369 channels = substream->runtime->channels; 370 cfg_val.regx.num_ch = channels - 2; 371 if (channels <= 2) 372 cfg_val.regx.layout = LAYOUT0; 373 else 374 cfg_val.regx.layout = LAYOUT1; 375 376 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 377 cfg_val.regx.packet_mode = 1; 378 379 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) 380 cfg_val.regx.left_align = 1; 381 382 cfg_val.regx.val_bit = 1; 383 384 /* fix up the DP bits */ 385 if (intelhaddata->dp_output) { 386 cfg_val.regx.dp_modei = 1; 387 cfg_val.regx.set = 1; 388 } 389 390 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 391 intelhaddata->aud_config = cfg_val; 392 return 0; 393 } 394 395 /* 396 * Compute derived values in channel_allocations[]. 397 */ 398 static void init_channel_allocations(void) 399 { 400 int i, j; 401 struct cea_channel_speaker_allocation *p; 402 403 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 404 p = channel_allocations + i; 405 p->channels = 0; 406 p->spk_mask = 0; 407 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 408 if (p->speakers[j]) { 409 p->channels++; 410 p->spk_mask |= p->speakers[j]; 411 } 412 } 413 } 414 415 /* 416 * The transformation takes two steps: 417 * 418 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 419 * spk_mask => (channel_allocations[]) => ai->CA 420 * 421 * TODO: it could select the wrong CA from multiple candidates. 422 */ 423 static int had_channel_allocation(struct snd_intelhad *intelhaddata, 424 int channels) 425 { 426 int i; 427 int ca = 0; 428 int spk_mask = 0; 429 430 /* 431 * CA defaults to 0 for basic stereo audio 432 */ 433 if (channels <= 2) 434 return 0; 435 436 /* 437 * expand ELD's speaker allocation mask 438 * 439 * ELD tells the speaker mask in a compact(paired) form, 440 * expand ELD's notions to match the ones used by Audio InfoFrame. 441 */ 442 443 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 444 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 445 spk_mask |= eld_speaker_allocation_bits[i]; 446 } 447 448 /* search for the first working match in the CA table */ 449 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 450 if (channels == channel_allocations[i].channels && 451 (spk_mask & channel_allocations[i].spk_mask) == 452 channel_allocations[i].spk_mask) { 453 ca = channel_allocations[i].ca_index; 454 break; 455 } 456 } 457 458 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); 459 460 return ca; 461 } 462 463 /* from speaker bit mask to ALSA API channel position */ 464 static int spk_to_chmap(int spk) 465 { 466 const struct channel_map_table *t = map_tables; 467 468 for (; t->map; t++) { 469 if (t->spk_mask == spk) 470 return t->map; 471 } 472 return 0; 473 } 474 475 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) 476 { 477 int i, c; 478 int spk_mask = 0; 479 struct snd_pcm_chmap_elem *chmap; 480 u8 eld_high, eld_high_mask = 0xF0; 481 u8 high_msb; 482 483 kfree(intelhaddata->chmap->chmap); 484 intelhaddata->chmap->chmap = NULL; 485 486 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); 487 if (!chmap) 488 return; 489 490 dev_dbg(intelhaddata->dev, "eld speaker = %x\n", 491 intelhaddata->eld[DRM_ELD_SPEAKER]); 492 493 /* WA: Fix the max channel supported to 8 */ 494 495 /* 496 * Sink may support more than 8 channels, if eld_high has more than 497 * one bit set. SOC supports max 8 channels. 498 * Refer eld_speaker_allocation_bits, for sink speaker allocation 499 */ 500 501 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ 502 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; 503 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { 504 /* eld_high & (eld_high-1): if more than 1 bit set */ 505 /* 0x1F: 7 channels */ 506 for (i = 1; i < 4; i++) { 507 high_msb = eld_high & (0x80 >> i); 508 if (high_msb) { 509 intelhaddata->eld[DRM_ELD_SPEAKER] &= 510 high_msb | 0xF; 511 break; 512 } 513 } 514 } 515 516 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 517 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 518 spk_mask |= eld_speaker_allocation_bits[i]; 519 } 520 521 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 522 if (spk_mask == channel_allocations[i].spk_mask) { 523 for (c = 0; c < channel_allocations[i].channels; c++) { 524 chmap->map[c] = spk_to_chmap( 525 channel_allocations[i].speakers[ 526 (MAX_SPEAKERS - 1) - c]); 527 } 528 chmap->channels = channel_allocations[i].channels; 529 intelhaddata->chmap->chmap = chmap; 530 break; 531 } 532 } 533 if (i >= ARRAY_SIZE(channel_allocations)) 534 kfree(chmap); 535 } 536 537 /* 538 * ALSA API channel-map control callbacks 539 */ 540 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, 541 struct snd_ctl_elem_info *uinfo) 542 { 543 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 544 uinfo->count = HAD_MAX_CHANNEL; 545 uinfo->value.integer.min = 0; 546 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 547 return 0; 548 } 549 550 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, 551 struct snd_ctl_elem_value *ucontrol) 552 { 553 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 554 struct snd_intelhad *intelhaddata = info->private_data; 555 int i; 556 const struct snd_pcm_chmap_elem *chmap; 557 558 memset(ucontrol->value.integer.value, 0, 559 sizeof(long) * HAD_MAX_CHANNEL); 560 mutex_lock(&intelhaddata->mutex); 561 if (!intelhaddata->chmap->chmap) { 562 mutex_unlock(&intelhaddata->mutex); 563 return 0; 564 } 565 566 chmap = intelhaddata->chmap->chmap; 567 for (i = 0; i < chmap->channels; i++) 568 ucontrol->value.integer.value[i] = chmap->map[i]; 569 mutex_unlock(&intelhaddata->mutex); 570 571 return 0; 572 } 573 574 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, 575 struct snd_pcm *pcm) 576 { 577 int err; 578 579 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 580 NULL, 0, (unsigned long)intelhaddata, 581 &intelhaddata->chmap); 582 if (err < 0) 583 return err; 584 585 intelhaddata->chmap->private_data = intelhaddata; 586 intelhaddata->chmap->kctl->info = had_chmap_ctl_info; 587 intelhaddata->chmap->kctl->get = had_chmap_ctl_get; 588 intelhaddata->chmap->chmap = NULL; 589 return 0; 590 } 591 592 /* 593 * Initialize Data Island Packets registers 594 * This function is called in the prepare callback 595 */ 596 static void had_prog_dip(struct snd_pcm_substream *substream, 597 struct snd_intelhad *intelhaddata) 598 { 599 int i; 600 union aud_ctrl_st ctrl_state = {.regval = 0}; 601 union aud_info_frame2 frame2 = {.regval = 0}; 602 union aud_info_frame3 frame3 = {.regval = 0}; 603 u8 checksum = 0; 604 u32 info_frame; 605 int channels; 606 int ca; 607 608 channels = substream->runtime->channels; 609 610 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 611 612 ca = had_channel_allocation(intelhaddata, channels); 613 if (intelhaddata->dp_output) { 614 info_frame = DP_INFO_FRAME_WORD1; 615 frame2.regval = (substream->runtime->channels - 1) | (ca << 24); 616 } else { 617 info_frame = HDMI_INFO_FRAME_WORD1; 618 frame2.regx.chnl_cnt = substream->runtime->channels - 1; 619 frame3.regx.chnl_alloc = ca; 620 621 /* Calculte the byte wide checksum for all valid DIP words */ 622 for (i = 0; i < BYTES_PER_WORD; i++) 623 checksum += (info_frame >> (i * 8)) & 0xff; 624 for (i = 0; i < BYTES_PER_WORD; i++) 625 checksum += (frame2.regval >> (i * 8)) & 0xff; 626 for (i = 0; i < BYTES_PER_WORD; i++) 627 checksum += (frame3.regval >> (i * 8)) & 0xff; 628 629 frame2.regx.chksum = -(checksum); 630 } 631 632 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); 633 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); 634 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); 635 636 /* program remaining DIP words with zero */ 637 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) 638 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); 639 640 ctrl_state.regx.dip_freq = 1; 641 ctrl_state.regx.dip_en_sta = 1; 642 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 643 } 644 645 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) 646 { 647 u32 maud_val; 648 649 /* Select maud according to DP 1.2 spec */ 650 if (link_rate == DP_2_7_GHZ) { 651 switch (aud_samp_freq) { 652 case AUD_SAMPLE_RATE_32: 653 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; 654 break; 655 656 case AUD_SAMPLE_RATE_44_1: 657 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; 658 break; 659 660 case AUD_SAMPLE_RATE_48: 661 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; 662 break; 663 664 case AUD_SAMPLE_RATE_88_2: 665 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; 666 break; 667 668 case AUD_SAMPLE_RATE_96: 669 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; 670 break; 671 672 case AUD_SAMPLE_RATE_176_4: 673 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; 674 break; 675 676 case HAD_MAX_RATE: 677 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; 678 break; 679 680 default: 681 maud_val = -EINVAL; 682 break; 683 } 684 } else if (link_rate == DP_1_62_GHZ) { 685 switch (aud_samp_freq) { 686 case AUD_SAMPLE_RATE_32: 687 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; 688 break; 689 690 case AUD_SAMPLE_RATE_44_1: 691 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; 692 break; 693 694 case AUD_SAMPLE_RATE_48: 695 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; 696 break; 697 698 case AUD_SAMPLE_RATE_88_2: 699 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; 700 break; 701 702 case AUD_SAMPLE_RATE_96: 703 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; 704 break; 705 706 case AUD_SAMPLE_RATE_176_4: 707 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; 708 break; 709 710 case HAD_MAX_RATE: 711 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; 712 break; 713 714 default: 715 maud_val = -EINVAL; 716 break; 717 } 718 } else 719 maud_val = -EINVAL; 720 721 return maud_val; 722 } 723 724 /* 725 * Program HDMI audio CTS value 726 * 727 * @aud_samp_freq: sampling frequency of audio data 728 * @tmds: sampling frequency of the display data 729 * @link_rate: DP link rate 730 * @n_param: N value, depends on aud_samp_freq 731 * @intelhaddata: substream private data 732 * 733 * Program CTS register based on the audio and display sampling frequency 734 */ 735 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, 736 u32 n_param, struct snd_intelhad *intelhaddata) 737 { 738 u32 cts_val; 739 u64 dividend, divisor; 740 741 if (intelhaddata->dp_output) { 742 /* Substitute cts_val with Maud according to DP 1.2 spec*/ 743 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); 744 } else { 745 /* Calculate CTS according to HDMI 1.3a spec*/ 746 dividend = (u64)tmds * n_param*1000; 747 divisor = 128 * aud_samp_freq; 748 cts_val = div64_u64(dividend, divisor); 749 } 750 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", 751 tmds, n_param, cts_val); 752 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); 753 } 754 755 static int had_calculate_n_value(u32 aud_samp_freq) 756 { 757 int n_val; 758 759 /* Select N according to HDMI 1.3a spec*/ 760 switch (aud_samp_freq) { 761 case AUD_SAMPLE_RATE_32: 762 n_val = 4096; 763 break; 764 765 case AUD_SAMPLE_RATE_44_1: 766 n_val = 6272; 767 break; 768 769 case AUD_SAMPLE_RATE_48: 770 n_val = 6144; 771 break; 772 773 case AUD_SAMPLE_RATE_88_2: 774 n_val = 12544; 775 break; 776 777 case AUD_SAMPLE_RATE_96: 778 n_val = 12288; 779 break; 780 781 case AUD_SAMPLE_RATE_176_4: 782 n_val = 25088; 783 break; 784 785 case HAD_MAX_RATE: 786 n_val = 24576; 787 break; 788 789 default: 790 n_val = -EINVAL; 791 break; 792 } 793 return n_val; 794 } 795 796 /* 797 * Program HDMI audio N value 798 * 799 * @aud_samp_freq: sampling frequency of audio data 800 * @n_param: N value, depends on aud_samp_freq 801 * @intelhaddata: substream private data 802 * 803 * This function is called in the prepare callback. 804 * It programs based on the audio and display sampling frequency 805 */ 806 static int had_prog_n(u32 aud_samp_freq, u32 *n_param, 807 struct snd_intelhad *intelhaddata) 808 { 809 int n_val; 810 811 if (intelhaddata->dp_output) { 812 /* 813 * According to DP specs, Maud and Naud values hold 814 * a relationship, which is stated as: 815 * Maud/Naud = 512 * fs / f_LS_Clk 816 * where, fs is the sampling frequency of the audio stream 817 * and Naud is 32768 for Async clock. 818 */ 819 820 n_val = DP_NAUD_VAL; 821 } else 822 n_val = had_calculate_n_value(aud_samp_freq); 823 824 if (n_val < 0) 825 return n_val; 826 827 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); 828 *n_param = n_val; 829 return 0; 830 } 831 832 /* 833 * PCM ring buffer handling 834 * 835 * The hardware provides a ring buffer with the fixed 4 buffer descriptors 836 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping 837 * moves at each period elapsed. The below illustrates how it works: 838 * 839 * At time=0 840 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 841 * BD | 0 | 1 | 2 | 3 | 842 * 843 * At time=1 (period elapsed) 844 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 845 * BD | 1 | 2 | 3 | 0 | 846 * 847 * At time=2 (second period elapsed) 848 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 849 * BD | 2 | 3 | 0 | 1 | 850 * 851 * The bd_head field points to the index of the BD to be read. It's also the 852 * position to be filled at next. The pcm_head and the pcm_filled fields 853 * point to the indices of the current position and of the next position to 854 * be filled, respectively. For PCM buffer there are both _head and _filled 855 * because they may be difference when nperiods > 4. For example, in the 856 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: 857 * 858 * pcm_head (=1) --v v-- pcm_filled (=5) 859 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 860 * BD | 1 | 2 | 3 | 0 | 861 * bd_head (=1) --^ ^-- next to fill (= bd_head) 862 * 863 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that 864 * the hardware skips those BDs in the loop. 865 * 866 * An exceptional setup is the case with nperiods=1. Since we have to update 867 * BDs after finishing one BD processing, we'd need at least two BDs, where 868 * both BDs point to the same content, the same address, the same size of the 869 * whole PCM buffer. 870 */ 871 872 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) 873 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) 874 875 /* Set up a buffer descriptor at the "filled" position */ 876 static void had_prog_bd(struct snd_pcm_substream *substream, 877 struct snd_intelhad *intelhaddata) 878 { 879 int idx = intelhaddata->bd_head; 880 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; 881 u32 addr = substream->runtime->dma_addr + ofs; 882 883 addr |= AUD_BUF_VALID; 884 if (!substream->runtime->no_period_wakeup) 885 addr |= AUD_BUF_INTR_EN; 886 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); 887 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 888 intelhaddata->period_bytes); 889 890 /* advance the indices to the next */ 891 intelhaddata->bd_head++; 892 intelhaddata->bd_head %= intelhaddata->num_bds; 893 intelhaddata->pcmbuf_filled++; 894 intelhaddata->pcmbuf_filled %= substream->runtime->periods; 895 } 896 897 /* invalidate a buffer descriptor with the given index */ 898 static void had_invalidate_bd(struct snd_intelhad *intelhaddata, 899 int idx) 900 { 901 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); 902 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); 903 } 904 905 /* Initial programming of ring buffer */ 906 static void had_init_ringbuf(struct snd_pcm_substream *substream, 907 struct snd_intelhad *intelhaddata) 908 { 909 struct snd_pcm_runtime *runtime = substream->runtime; 910 int i, num_periods; 911 912 num_periods = runtime->periods; 913 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); 914 /* set the minimum 2 BDs for num_periods=1 */ 915 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); 916 intelhaddata->period_bytes = 917 frames_to_bytes(runtime, runtime->period_size); 918 WARN_ON(intelhaddata->period_bytes & 0x3f); 919 920 intelhaddata->bd_head = 0; 921 intelhaddata->pcmbuf_head = 0; 922 intelhaddata->pcmbuf_filled = 0; 923 924 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { 925 if (i < intelhaddata->num_bds) 926 had_prog_bd(substream, intelhaddata); 927 else /* invalidate the rest */ 928 had_invalidate_bd(intelhaddata, i); 929 } 930 931 intelhaddata->bd_head = 0; /* reset at head again before starting */ 932 } 933 934 /* process a bd, advance to the next */ 935 static void had_advance_ringbuf(struct snd_pcm_substream *substream, 936 struct snd_intelhad *intelhaddata) 937 { 938 int num_periods = substream->runtime->periods; 939 940 /* reprogram the next buffer */ 941 had_prog_bd(substream, intelhaddata); 942 943 /* proceed to next */ 944 intelhaddata->pcmbuf_head++; 945 intelhaddata->pcmbuf_head %= num_periods; 946 } 947 948 /* process the current BD(s); 949 * returns the current PCM buffer byte position, or -EPIPE for underrun. 950 */ 951 static int had_process_ringbuf(struct snd_pcm_substream *substream, 952 struct snd_intelhad *intelhaddata) 953 { 954 int len, processed; 955 unsigned long flags; 956 957 processed = 0; 958 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 959 for (;;) { 960 /* get the remaining bytes on the buffer */ 961 had_read_register(intelhaddata, 962 AUD_BUF_LEN(intelhaddata->bd_head), 963 &len); 964 if (len < 0 || len > intelhaddata->period_bytes) { 965 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", 966 len); 967 len = -EPIPE; 968 goto out; 969 } 970 971 if (len > 0) /* OK, this is the current buffer */ 972 break; 973 974 /* len=0 => already empty, check the next buffer */ 975 if (++processed >= intelhaddata->num_bds) { 976 len = -EPIPE; /* all empty? - report underrun */ 977 goto out; 978 } 979 had_advance_ringbuf(substream, intelhaddata); 980 } 981 982 len = intelhaddata->period_bytes - len; 983 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; 984 out: 985 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 986 return len; 987 } 988 989 /* called from irq handler */ 990 static void had_process_buffer_done(struct snd_intelhad *intelhaddata) 991 { 992 struct snd_pcm_substream *substream; 993 994 substream = had_substream_get(intelhaddata); 995 if (!substream) 996 return; /* no stream? - bail out */ 997 998 if (!intelhaddata->connected) { 999 snd_pcm_stop_xrun(substream); 1000 goto out; /* disconnected? - bail out */ 1001 } 1002 1003 /* process or stop the stream */ 1004 if (had_process_ringbuf(substream, intelhaddata) < 0) 1005 snd_pcm_stop_xrun(substream); 1006 else 1007 snd_pcm_period_elapsed(substream); 1008 1009 out: 1010 had_substream_put(intelhaddata); 1011 } 1012 1013 /* 1014 * The interrupt status 'sticky' bits might not be cleared by 1015 * setting '1' to that bit once... 1016 */ 1017 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) 1018 { 1019 int i; 1020 u32 val; 1021 1022 for (i = 0; i < 100; i++) { 1023 /* clear bit30, 31 AUD_HDMI_STATUS */ 1024 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); 1025 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) 1026 return; 1027 udelay(100); 1028 cond_resched(); 1029 had_write_register(intelhaddata, AUD_HDMI_STATUS, val); 1030 } 1031 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); 1032 } 1033 1034 /* Perform some reset procedure but only when need_reset is set; 1035 * this is called from prepare or hw_free callbacks once after trigger STOP 1036 * or underrun has been processed in order to settle down the h/w state. 1037 */ 1038 static void had_do_reset(struct snd_intelhad *intelhaddata) 1039 { 1040 if (!intelhaddata->need_reset || !intelhaddata->connected) 1041 return; 1042 1043 /* Reset buffer pointers */ 1044 had_reset_audio(intelhaddata); 1045 wait_clear_underrun_bit(intelhaddata); 1046 intelhaddata->need_reset = false; 1047 } 1048 1049 /* called from irq handler */ 1050 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) 1051 { 1052 struct snd_pcm_substream *substream; 1053 1054 /* Report UNDERRUN error to above layers */ 1055 substream = had_substream_get(intelhaddata); 1056 if (substream) { 1057 snd_pcm_stop_xrun(substream); 1058 had_substream_put(intelhaddata); 1059 } 1060 intelhaddata->need_reset = true; 1061 } 1062 1063 /* 1064 * ALSA PCM open callback 1065 */ 1066 static int had_pcm_open(struct snd_pcm_substream *substream) 1067 { 1068 struct snd_intelhad *intelhaddata; 1069 struct snd_pcm_runtime *runtime; 1070 int retval; 1071 1072 intelhaddata = snd_pcm_substream_chip(substream); 1073 runtime = substream->runtime; 1074 1075 pm_runtime_get_sync(intelhaddata->dev); 1076 1077 /* set the runtime hw parameter with local snd_pcm_hardware struct */ 1078 runtime->hw = had_pcm_hardware; 1079 1080 retval = snd_pcm_hw_constraint_integer(runtime, 1081 SNDRV_PCM_HW_PARAM_PERIODS); 1082 if (retval < 0) 1083 goto error; 1084 1085 /* Make sure, that the period size is always aligned 1086 * 64byte boundary 1087 */ 1088 retval = snd_pcm_hw_constraint_step(substream->runtime, 0, 1089 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); 1090 if (retval < 0) 1091 goto error; 1092 1093 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1094 if (retval < 0) 1095 goto error; 1096 1097 /* expose PCM substream */ 1098 spin_lock_irq(&intelhaddata->had_spinlock); 1099 intelhaddata->stream_info.substream = substream; 1100 intelhaddata->stream_info.substream_refcount++; 1101 spin_unlock_irq(&intelhaddata->had_spinlock); 1102 1103 return retval; 1104 error: 1105 pm_runtime_mark_last_busy(intelhaddata->dev); 1106 pm_runtime_put_autosuspend(intelhaddata->dev); 1107 return retval; 1108 } 1109 1110 /* 1111 * ALSA PCM close callback 1112 */ 1113 static int had_pcm_close(struct snd_pcm_substream *substream) 1114 { 1115 struct snd_intelhad *intelhaddata; 1116 1117 intelhaddata = snd_pcm_substream_chip(substream); 1118 1119 /* unreference and sync with the pending PCM accesses */ 1120 spin_lock_irq(&intelhaddata->had_spinlock); 1121 intelhaddata->stream_info.substream = NULL; 1122 intelhaddata->stream_info.substream_refcount--; 1123 while (intelhaddata->stream_info.substream_refcount > 0) { 1124 spin_unlock_irq(&intelhaddata->had_spinlock); 1125 cpu_relax(); 1126 spin_lock_irq(&intelhaddata->had_spinlock); 1127 } 1128 spin_unlock_irq(&intelhaddata->had_spinlock); 1129 1130 pm_runtime_mark_last_busy(intelhaddata->dev); 1131 pm_runtime_put_autosuspend(intelhaddata->dev); 1132 return 0; 1133 } 1134 1135 /* 1136 * ALSA PCM hw_params callback 1137 */ 1138 static int had_pcm_hw_params(struct snd_pcm_substream *substream, 1139 struct snd_pcm_hw_params *hw_params) 1140 { 1141 struct snd_intelhad *intelhaddata; 1142 unsigned long addr; 1143 int pages, buf_size, retval; 1144 1145 intelhaddata = snd_pcm_substream_chip(substream); 1146 buf_size = params_buffer_bytes(hw_params); 1147 retval = snd_pcm_lib_malloc_pages(substream, buf_size); 1148 if (retval < 0) 1149 return retval; 1150 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", 1151 __func__, buf_size); 1152 /* mark the pages as uncached region */ 1153 addr = (unsigned long) substream->runtime->dma_area; 1154 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE; 1155 retval = set_memory_uc(addr, pages); 1156 if (retval) { 1157 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n", 1158 retval); 1159 return retval; 1160 } 1161 memset(substream->runtime->dma_area, 0, buf_size); 1162 1163 return retval; 1164 } 1165 1166 /* 1167 * ALSA PCM hw_free callback 1168 */ 1169 static int had_pcm_hw_free(struct snd_pcm_substream *substream) 1170 { 1171 struct snd_intelhad *intelhaddata; 1172 unsigned long addr; 1173 u32 pages; 1174 1175 intelhaddata = snd_pcm_substream_chip(substream); 1176 had_do_reset(intelhaddata); 1177 1178 /* mark back the pages as cached/writeback region before the free */ 1179 if (substream->runtime->dma_area != NULL) { 1180 addr = (unsigned long) substream->runtime->dma_area; 1181 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / 1182 PAGE_SIZE; 1183 set_memory_wb(addr, pages); 1184 return snd_pcm_lib_free_pages(substream); 1185 } 1186 return 0; 1187 } 1188 1189 /* 1190 * ALSA PCM trigger callback 1191 */ 1192 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1193 { 1194 int retval = 0; 1195 struct snd_intelhad *intelhaddata; 1196 1197 intelhaddata = snd_pcm_substream_chip(substream); 1198 1199 spin_lock(&intelhaddata->had_spinlock); 1200 switch (cmd) { 1201 case SNDRV_PCM_TRIGGER_START: 1202 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1203 case SNDRV_PCM_TRIGGER_RESUME: 1204 /* Enable Audio */ 1205 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ 1206 had_enable_audio(intelhaddata, true); 1207 break; 1208 1209 case SNDRV_PCM_TRIGGER_STOP: 1210 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1211 /* Disable Audio */ 1212 had_enable_audio(intelhaddata, false); 1213 intelhaddata->need_reset = true; 1214 break; 1215 1216 default: 1217 retval = -EINVAL; 1218 } 1219 spin_unlock(&intelhaddata->had_spinlock); 1220 return retval; 1221 } 1222 1223 /* 1224 * ALSA PCM prepare callback 1225 */ 1226 static int had_pcm_prepare(struct snd_pcm_substream *substream) 1227 { 1228 int retval; 1229 u32 disp_samp_freq, n_param; 1230 u32 link_rate = 0; 1231 struct snd_intelhad *intelhaddata; 1232 struct snd_pcm_runtime *runtime; 1233 1234 intelhaddata = snd_pcm_substream_chip(substream); 1235 runtime = substream->runtime; 1236 1237 dev_dbg(intelhaddata->dev, "period_size=%d\n", 1238 (int)frames_to_bytes(runtime, runtime->period_size)); 1239 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); 1240 dev_dbg(intelhaddata->dev, "buffer_size=%d\n", 1241 (int)snd_pcm_lib_buffer_bytes(substream)); 1242 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); 1243 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); 1244 1245 had_do_reset(intelhaddata); 1246 1247 /* Get N value in KHz */ 1248 disp_samp_freq = intelhaddata->tmds_clock_speed; 1249 1250 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1251 if (retval) { 1252 dev_err(intelhaddata->dev, 1253 "programming N value failed %#x\n", retval); 1254 goto prep_end; 1255 } 1256 1257 if (intelhaddata->dp_output) 1258 link_rate = intelhaddata->link_rate; 1259 1260 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1261 n_param, intelhaddata); 1262 1263 had_prog_dip(substream, intelhaddata); 1264 1265 retval = had_init_audio_ctrl(substream, intelhaddata); 1266 1267 /* Prog buffer address */ 1268 had_init_ringbuf(substream, intelhaddata); 1269 1270 /* 1271 * Program channel mapping in following order: 1272 * FL, FR, C, LFE, RL, RR 1273 */ 1274 1275 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); 1276 1277 prep_end: 1278 return retval; 1279 } 1280 1281 /* 1282 * ALSA PCM pointer callback 1283 */ 1284 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) 1285 { 1286 struct snd_intelhad *intelhaddata; 1287 int len; 1288 1289 intelhaddata = snd_pcm_substream_chip(substream); 1290 1291 if (!intelhaddata->connected) 1292 return SNDRV_PCM_POS_XRUN; 1293 1294 len = had_process_ringbuf(substream, intelhaddata); 1295 if (len < 0) 1296 return SNDRV_PCM_POS_XRUN; 1297 len = bytes_to_frames(substream->runtime, len); 1298 /* wrapping may happen when periods=1 */ 1299 len %= substream->runtime->buffer_size; 1300 return len; 1301 } 1302 1303 /* 1304 * ALSA PCM mmap callback 1305 */ 1306 static int had_pcm_mmap(struct snd_pcm_substream *substream, 1307 struct vm_area_struct *vma) 1308 { 1309 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1310 return remap_pfn_range(vma, vma->vm_start, 1311 substream->dma_buffer.addr >> PAGE_SHIFT, 1312 vma->vm_end - vma->vm_start, vma->vm_page_prot); 1313 } 1314 1315 /* 1316 * ALSA PCM ops 1317 */ 1318 static const struct snd_pcm_ops had_pcm_ops = { 1319 .open = had_pcm_open, 1320 .close = had_pcm_close, 1321 .ioctl = snd_pcm_lib_ioctl, 1322 .hw_params = had_pcm_hw_params, 1323 .hw_free = had_pcm_hw_free, 1324 .prepare = had_pcm_prepare, 1325 .trigger = had_pcm_trigger, 1326 .pointer = had_pcm_pointer, 1327 .mmap = had_pcm_mmap, 1328 }; 1329 1330 /* process mode change of the running stream; called in mutex */ 1331 static int had_process_mode_change(struct snd_intelhad *intelhaddata) 1332 { 1333 struct snd_pcm_substream *substream; 1334 int retval = 0; 1335 u32 disp_samp_freq, n_param; 1336 u32 link_rate = 0; 1337 1338 substream = had_substream_get(intelhaddata); 1339 if (!substream) 1340 return 0; 1341 1342 /* Disable Audio */ 1343 had_enable_audio(intelhaddata, false); 1344 1345 /* Update CTS value */ 1346 disp_samp_freq = intelhaddata->tmds_clock_speed; 1347 1348 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1349 if (retval) { 1350 dev_err(intelhaddata->dev, 1351 "programming N value failed %#x\n", retval); 1352 goto out; 1353 } 1354 1355 if (intelhaddata->dp_output) 1356 link_rate = intelhaddata->link_rate; 1357 1358 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1359 n_param, intelhaddata); 1360 1361 /* Enable Audio */ 1362 had_enable_audio(intelhaddata, true); 1363 1364 out: 1365 had_substream_put(intelhaddata); 1366 return retval; 1367 } 1368 1369 /* process hot plug, called from wq with mutex locked */ 1370 static void had_process_hot_plug(struct snd_intelhad *intelhaddata) 1371 { 1372 struct snd_pcm_substream *substream; 1373 1374 spin_lock_irq(&intelhaddata->had_spinlock); 1375 if (intelhaddata->connected) { 1376 dev_dbg(intelhaddata->dev, "Device already connected\n"); 1377 spin_unlock_irq(&intelhaddata->had_spinlock); 1378 return; 1379 } 1380 1381 /* Disable Audio */ 1382 had_enable_audio(intelhaddata, false); 1383 1384 intelhaddata->connected = true; 1385 dev_dbg(intelhaddata->dev, 1386 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", 1387 __func__, __LINE__); 1388 spin_unlock_irq(&intelhaddata->had_spinlock); 1389 1390 had_build_channel_allocation_map(intelhaddata); 1391 1392 /* Report to above ALSA layer */ 1393 substream = had_substream_get(intelhaddata); 1394 if (substream) { 1395 snd_pcm_stop_xrun(substream); 1396 had_substream_put(intelhaddata); 1397 } 1398 1399 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); 1400 } 1401 1402 /* process hot unplug, called from wq with mutex locked */ 1403 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) 1404 { 1405 struct snd_pcm_substream *substream; 1406 1407 spin_lock_irq(&intelhaddata->had_spinlock); 1408 if (!intelhaddata->connected) { 1409 dev_dbg(intelhaddata->dev, "Device already disconnected\n"); 1410 spin_unlock_irq(&intelhaddata->had_spinlock); 1411 return; 1412 1413 } 1414 1415 /* Disable Audio */ 1416 had_enable_audio(intelhaddata, false); 1417 1418 intelhaddata->connected = false; 1419 dev_dbg(intelhaddata->dev, 1420 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", 1421 __func__, __LINE__); 1422 spin_unlock_irq(&intelhaddata->had_spinlock); 1423 1424 kfree(intelhaddata->chmap->chmap); 1425 intelhaddata->chmap->chmap = NULL; 1426 1427 /* Report to above ALSA layer */ 1428 substream = had_substream_get(intelhaddata); 1429 if (substream) { 1430 snd_pcm_stop_xrun(substream); 1431 had_substream_put(intelhaddata); 1432 } 1433 1434 snd_jack_report(intelhaddata->jack, 0); 1435 } 1436 1437 /* 1438 * ALSA iec958 and ELD controls 1439 */ 1440 1441 static int had_iec958_info(struct snd_kcontrol *kcontrol, 1442 struct snd_ctl_elem_info *uinfo) 1443 { 1444 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1445 uinfo->count = 1; 1446 return 0; 1447 } 1448 1449 static int had_iec958_get(struct snd_kcontrol *kcontrol, 1450 struct snd_ctl_elem_value *ucontrol) 1451 { 1452 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1453 1454 mutex_lock(&intelhaddata->mutex); 1455 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; 1456 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; 1457 ucontrol->value.iec958.status[2] = 1458 (intelhaddata->aes_bits >> 16) & 0xff; 1459 ucontrol->value.iec958.status[3] = 1460 (intelhaddata->aes_bits >> 24) & 0xff; 1461 mutex_unlock(&intelhaddata->mutex); 1462 return 0; 1463 } 1464 1465 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, 1466 struct snd_ctl_elem_value *ucontrol) 1467 { 1468 ucontrol->value.iec958.status[0] = 0xff; 1469 ucontrol->value.iec958.status[1] = 0xff; 1470 ucontrol->value.iec958.status[2] = 0xff; 1471 ucontrol->value.iec958.status[3] = 0xff; 1472 return 0; 1473 } 1474 1475 static int had_iec958_put(struct snd_kcontrol *kcontrol, 1476 struct snd_ctl_elem_value *ucontrol) 1477 { 1478 unsigned int val; 1479 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1480 int changed = 0; 1481 1482 val = (ucontrol->value.iec958.status[0] << 0) | 1483 (ucontrol->value.iec958.status[1] << 8) | 1484 (ucontrol->value.iec958.status[2] << 16) | 1485 (ucontrol->value.iec958.status[3] << 24); 1486 mutex_lock(&intelhaddata->mutex); 1487 if (intelhaddata->aes_bits != val) { 1488 intelhaddata->aes_bits = val; 1489 changed = 1; 1490 } 1491 mutex_unlock(&intelhaddata->mutex); 1492 return changed; 1493 } 1494 1495 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, 1496 struct snd_ctl_elem_info *uinfo) 1497 { 1498 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1499 uinfo->count = HDMI_MAX_ELD_BYTES; 1500 return 0; 1501 } 1502 1503 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, 1504 struct snd_ctl_elem_value *ucontrol) 1505 { 1506 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1507 1508 mutex_lock(&intelhaddata->mutex); 1509 memcpy(ucontrol->value.bytes.data, intelhaddata->eld, 1510 HDMI_MAX_ELD_BYTES); 1511 mutex_unlock(&intelhaddata->mutex); 1512 return 0; 1513 } 1514 1515 static const struct snd_kcontrol_new had_controls[] = { 1516 { 1517 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1518 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1519 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 1520 .info = had_iec958_info, /* shared */ 1521 .get = had_iec958_mask_get, 1522 }, 1523 { 1524 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1525 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1526 .info = had_iec958_info, 1527 .get = had_iec958_get, 1528 .put = had_iec958_put, 1529 }, 1530 { 1531 .access = (SNDRV_CTL_ELEM_ACCESS_READ | 1532 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1533 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1534 .name = "ELD", 1535 .info = had_ctl_eld_info, 1536 .get = had_ctl_eld_get, 1537 }, 1538 }; 1539 1540 /* 1541 * audio interrupt handler 1542 */ 1543 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) 1544 { 1545 struct snd_intelhad_card *card_ctx = dev_id; 1546 u32 audio_stat[3] = {}; 1547 int pipe, port; 1548 1549 for_each_pipe(card_ctx, pipe) { 1550 /* use raw register access to ack IRQs even while disconnected */ 1551 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, 1552 AUD_HDMI_STATUS) & 1553 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); 1554 1555 if (audio_stat[pipe]) 1556 had_write_register_raw(card_ctx, pipe, 1557 AUD_HDMI_STATUS, audio_stat[pipe]); 1558 } 1559 1560 for_each_port(card_ctx, port) { 1561 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1562 int pipe = ctx->pipe; 1563 1564 if (pipe < 0) 1565 continue; 1566 1567 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) 1568 had_process_buffer_done(ctx); 1569 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) 1570 had_process_buffer_underrun(ctx); 1571 } 1572 1573 return IRQ_HANDLED; 1574 } 1575 1576 /* 1577 * monitor plug/unplug notification from i915; just kick off the work 1578 */ 1579 static void notify_audio_lpe(struct platform_device *pdev, int port) 1580 { 1581 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1582 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1583 1584 schedule_work(&ctx->hdmi_audio_wq); 1585 } 1586 1587 /* the work to handle monitor hot plug/unplug */ 1588 static void had_audio_wq(struct work_struct *work) 1589 { 1590 struct snd_intelhad *ctx = 1591 container_of(work, struct snd_intelhad, hdmi_audio_wq); 1592 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; 1593 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; 1594 1595 pm_runtime_get_sync(ctx->dev); 1596 mutex_lock(&ctx->mutex); 1597 if (ppdata->pipe < 0) { 1598 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", 1599 __func__, ctx->port); 1600 1601 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ 1602 1603 ctx->dp_output = false; 1604 ctx->tmds_clock_speed = 0; 1605 ctx->link_rate = 0; 1606 1607 /* Shut down the stream */ 1608 had_process_hot_unplug(ctx); 1609 1610 ctx->pipe = -1; 1611 } else { 1612 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", 1613 __func__, ctx->port, ppdata->ls_clock); 1614 1615 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); 1616 1617 ctx->dp_output = ppdata->dp_output; 1618 if (ctx->dp_output) { 1619 ctx->tmds_clock_speed = 0; 1620 ctx->link_rate = ppdata->ls_clock; 1621 } else { 1622 ctx->tmds_clock_speed = ppdata->ls_clock; 1623 ctx->link_rate = 0; 1624 } 1625 1626 /* 1627 * Shut down the stream before we change 1628 * the pipe assignment for this pcm device 1629 */ 1630 had_process_hot_plug(ctx); 1631 1632 ctx->pipe = ppdata->pipe; 1633 1634 /* Restart the stream if necessary */ 1635 had_process_mode_change(ctx); 1636 } 1637 1638 mutex_unlock(&ctx->mutex); 1639 pm_runtime_mark_last_busy(ctx->dev); 1640 pm_runtime_put_autosuspend(ctx->dev); 1641 } 1642 1643 /* 1644 * Jack interface 1645 */ 1646 static int had_create_jack(struct snd_intelhad *ctx, 1647 struct snd_pcm *pcm) 1648 { 1649 char hdmi_str[32]; 1650 int err; 1651 1652 snprintf(hdmi_str, sizeof(hdmi_str), 1653 "HDMI/DP,pcm=%d", pcm->device); 1654 1655 err = snd_jack_new(ctx->card_ctx->card, hdmi_str, 1656 SND_JACK_AVOUT, &ctx->jack, 1657 true, false); 1658 if (err < 0) 1659 return err; 1660 ctx->jack->private_data = ctx; 1661 return 0; 1662 } 1663 1664 /* 1665 * PM callbacks 1666 */ 1667 1668 static int hdmi_lpe_audio_runtime_suspend(struct device *dev) 1669 { 1670 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1671 int port; 1672 1673 for_each_port(card_ctx, port) { 1674 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1675 struct snd_pcm_substream *substream; 1676 1677 substream = had_substream_get(ctx); 1678 if (substream) { 1679 snd_pcm_suspend(substream); 1680 had_substream_put(ctx); 1681 } 1682 } 1683 1684 return 0; 1685 } 1686 1687 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev) 1688 { 1689 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1690 int err; 1691 1692 err = hdmi_lpe_audio_runtime_suspend(dev); 1693 if (!err) 1694 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); 1695 return err; 1696 } 1697 1698 static int hdmi_lpe_audio_runtime_resume(struct device *dev) 1699 { 1700 pm_runtime_mark_last_busy(dev); 1701 return 0; 1702 } 1703 1704 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev) 1705 { 1706 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1707 1708 hdmi_lpe_audio_runtime_resume(dev); 1709 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); 1710 return 0; 1711 } 1712 1713 /* release resources */ 1714 static void hdmi_lpe_audio_free(struct snd_card *card) 1715 { 1716 struct snd_intelhad_card *card_ctx = card->private_data; 1717 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; 1718 int port; 1719 1720 spin_lock_irq(&pdata->lpe_audio_slock); 1721 pdata->notify_audio_lpe = NULL; 1722 spin_unlock_irq(&pdata->lpe_audio_slock); 1723 1724 for_each_port(card_ctx, port) { 1725 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1726 1727 cancel_work_sync(&ctx->hdmi_audio_wq); 1728 } 1729 1730 if (card_ctx->mmio_start) 1731 iounmap(card_ctx->mmio_start); 1732 if (card_ctx->irq >= 0) 1733 free_irq(card_ctx->irq, card_ctx); 1734 } 1735 1736 /* 1737 * hdmi_lpe_audio_probe - start bridge with i915 1738 * 1739 * This function is called when the i915 driver creates the 1740 * hdmi-lpe-audio platform device. 1741 */ 1742 static int hdmi_lpe_audio_probe(struct platform_device *pdev) 1743 { 1744 struct snd_card *card; 1745 struct snd_intelhad_card *card_ctx; 1746 struct snd_pcm *pcm; 1747 struct intel_hdmi_lpe_audio_pdata *pdata; 1748 int irq; 1749 struct resource *res_mmio; 1750 int port, ret; 1751 1752 pdata = pdev->dev.platform_data; 1753 if (!pdata) { 1754 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); 1755 return -EINVAL; 1756 } 1757 1758 /* get resources */ 1759 irq = platform_get_irq(pdev, 0); 1760 if (irq < 0) { 1761 dev_err(&pdev->dev, "Could not get irq resource: %d\n", irq); 1762 return irq; 1763 } 1764 1765 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1766 if (!res_mmio) { 1767 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); 1768 return -ENXIO; 1769 } 1770 1771 /* create a card instance with ALSA framework */ 1772 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, 1773 THIS_MODULE, sizeof(*card_ctx), &card); 1774 if (ret) 1775 return ret; 1776 1777 card_ctx = card->private_data; 1778 card_ctx->dev = &pdev->dev; 1779 card_ctx->card = card; 1780 strcpy(card->driver, INTEL_HAD); 1781 strcpy(card->shortname, "Intel HDMI/DP LPE Audio"); 1782 strcpy(card->longname, "Intel HDMI/DP LPE Audio"); 1783 1784 card_ctx->irq = -1; 1785 1786 card->private_free = hdmi_lpe_audio_free; 1787 1788 platform_set_drvdata(pdev, card_ctx); 1789 1790 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", 1791 __func__, (unsigned int)res_mmio->start, 1792 (unsigned int)res_mmio->end); 1793 1794 card_ctx->mmio_start = ioremap_nocache(res_mmio->start, 1795 (size_t)(resource_size(res_mmio))); 1796 if (!card_ctx->mmio_start) { 1797 dev_err(&pdev->dev, "Could not get ioremap\n"); 1798 ret = -EACCES; 1799 goto err; 1800 } 1801 1802 /* setup interrupt handler */ 1803 ret = request_irq(irq, display_pipe_interrupt_handler, 0, 1804 pdev->name, card_ctx); 1805 if (ret < 0) { 1806 dev_err(&pdev->dev, "request_irq failed\n"); 1807 goto err; 1808 } 1809 1810 card_ctx->irq = irq; 1811 1812 /* only 32bit addressable */ 1813 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1814 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1815 1816 init_channel_allocations(); 1817 1818 card_ctx->num_pipes = pdata->num_pipes; 1819 card_ctx->num_ports = pdata->num_ports; 1820 1821 for_each_port(card_ctx, port) { 1822 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1823 int i; 1824 1825 ctx->card_ctx = card_ctx; 1826 ctx->dev = card_ctx->dev; 1827 ctx->port = port; 1828 ctx->pipe = -1; 1829 1830 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); 1831 1832 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, 1833 MAX_CAP_STREAMS, &pcm); 1834 if (ret) 1835 goto err; 1836 1837 /* setup private data which can be retrieved when required */ 1838 pcm->private_data = ctx; 1839 pcm->info_flags = 0; 1840 strncpy(pcm->name, card->shortname, strlen(card->shortname)); 1841 /* setup the ops for playabck */ 1842 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); 1843 1844 /* allocate dma pages; 1845 * try to allocate 600k buffer as default which is large enough 1846 */ 1847 snd_pcm_lib_preallocate_pages_for_all(pcm, 1848 SNDRV_DMA_TYPE_DEV, NULL, 1849 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER); 1850 1851 /* create controls */ 1852 for (i = 0; i < ARRAY_SIZE(had_controls); i++) { 1853 struct snd_kcontrol *kctl; 1854 1855 kctl = snd_ctl_new1(&had_controls[i], ctx); 1856 if (!kctl) { 1857 ret = -ENOMEM; 1858 goto err; 1859 } 1860 1861 kctl->id.device = pcm->device; 1862 1863 ret = snd_ctl_add(card, kctl); 1864 if (ret < 0) 1865 goto err; 1866 } 1867 1868 /* Register channel map controls */ 1869 ret = had_register_chmap_ctls(ctx, pcm); 1870 if (ret < 0) 1871 goto err; 1872 1873 ret = had_create_jack(ctx, pcm); 1874 if (ret < 0) 1875 goto err; 1876 } 1877 1878 ret = snd_card_register(card); 1879 if (ret) 1880 goto err; 1881 1882 spin_lock_irq(&pdata->lpe_audio_slock); 1883 pdata->notify_audio_lpe = notify_audio_lpe; 1884 spin_unlock_irq(&pdata->lpe_audio_slock); 1885 1886 pm_runtime_use_autosuspend(&pdev->dev); 1887 pm_runtime_mark_last_busy(&pdev->dev); 1888 pm_runtime_set_active(&pdev->dev); 1889 1890 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); 1891 for_each_port(card_ctx, port) { 1892 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1893 1894 schedule_work(&ctx->hdmi_audio_wq); 1895 } 1896 1897 return 0; 1898 1899 err: 1900 snd_card_free(card); 1901 return ret; 1902 } 1903 1904 /* 1905 * hdmi_lpe_audio_remove - stop bridge with i915 1906 * 1907 * This function is called when the platform device is destroyed. 1908 */ 1909 static int hdmi_lpe_audio_remove(struct platform_device *pdev) 1910 { 1911 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1912 1913 snd_card_free(card_ctx->card); 1914 return 0; 1915 } 1916 1917 static const struct dev_pm_ops hdmi_lpe_audio_pm = { 1918 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) 1919 SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, 1920 hdmi_lpe_audio_runtime_resume, NULL) 1921 }; 1922 1923 static struct platform_driver hdmi_lpe_audio_driver = { 1924 .driver = { 1925 .name = "hdmi-lpe-audio", 1926 .pm = &hdmi_lpe_audio_pm, 1927 }, 1928 .probe = hdmi_lpe_audio_probe, 1929 .remove = hdmi_lpe_audio_remove, 1930 }; 1931 1932 module_platform_driver(hdmi_lpe_audio_driver); 1933 MODULE_ALIAS("platform:hdmi_lpe_audio"); 1934 1935 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); 1936 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); 1937 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); 1938 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); 1939 MODULE_DESCRIPTION("Intel HDMI Audio driver"); 1940 MODULE_LICENSE("GPL v2"); 1941 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}"); 1942