1 /* 2 * Driver for CS4231 sound chips found on Sparcs. 3 * Copyright (C) 2002 David S. Miller <davem@redhat.com> 4 * 5 * Based entirely upon drivers/sbus/audio/cs4231.c which is: 6 * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu) 7 * and also sound/isa/cs423x/cs4231_lib.c which is: 8 * Copyright (c) by Jaroslav Kysela <perex@suse.cz> 9 */ 10 11 #include <linux/config.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/moduleparam.h> 19 20 #include <sound/driver.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/info.h> 24 #include <sound/control.h> 25 #include <sound/timer.h> 26 #include <sound/initval.h> 27 #include <sound/pcm_params.h> 28 29 #include <asm/io.h> 30 #include <asm/irq.h> 31 32 #ifdef CONFIG_SBUS 33 #define SBUS_SUPPORT 34 #endif 35 36 #ifdef SBUS_SUPPORT 37 #include <asm/sbus.h> 38 #endif 39 40 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64) 41 #define EBUS_SUPPORT 42 #endif 43 44 #ifdef EBUS_SUPPORT 45 #include <linux/pci.h> 46 #include <asm/ebus.h> 47 #endif 48 49 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 50 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 52 53 module_param_array(index, int, NULL, 0444); 54 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard."); 55 module_param_array(id, charp, NULL, 0444); 56 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard."); 57 module_param_array(enable, bool, NULL, 0444); 58 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard."); 59 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller"); 60 MODULE_DESCRIPTION("Sun CS4231"); 61 MODULE_LICENSE("GPL"); 62 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}"); 63 64 #ifdef SBUS_SUPPORT 65 struct sbus_dma_info { 66 spinlock_t lock; 67 int dir; 68 void __iomem *regs; 69 }; 70 #endif 71 72 struct cs4231_dma_control { 73 void (*prepare)(struct cs4231_dma_control *dma_cont, int dir); 74 void (*enable)(struct cs4231_dma_control *dma_cont, int on); 75 int (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len); 76 unsigned int (*address)(struct cs4231_dma_control *dma_cont); 77 void (*reset)(struct snd_cs4231 *chip); 78 void (*preallocate)(struct snd_cs4231 *chip, struct snd_snd_pcm *pcm); 79 #ifdef EBUS_SUPPORT 80 struct ebus_dma_info ebus_info; 81 #endif 82 #ifdef SBUS_SUPPORT 83 struct sbus_dma_info sbus_info; 84 #endif 85 }; 86 87 struct snd_cs4231 { 88 spinlock_t lock; 89 void __iomem *port; 90 91 struct cs4231_dma_control p_dma; 92 struct cs4231_dma_control c_dma; 93 94 u32 flags; 95 #define CS4231_FLAG_EBUS 0x00000001 96 #define CS4231_FLAG_PLAYBACK 0x00000002 97 #define CS4231_FLAG_CAPTURE 0x00000004 98 99 struct snd_card *card; 100 struct snd_pcm *pcm; 101 struct snd_pcm_substream *playback_substream; 102 unsigned int p_periods_sent; 103 struct snd_pcm_substream *capture_substream; 104 unsigned int c_periods_sent; 105 struct snd_timer *timer; 106 107 unsigned short mode; 108 #define CS4231_MODE_NONE 0x0000 109 #define CS4231_MODE_PLAY 0x0001 110 #define CS4231_MODE_RECORD 0x0002 111 #define CS4231_MODE_TIMER 0x0004 112 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER) 113 114 unsigned char image[32]; /* registers image */ 115 int mce_bit; 116 int calibrate_mute; 117 struct semaphore mce_mutex; 118 struct semaphore open_mutex; 119 120 union { 121 #ifdef SBUS_SUPPORT 122 struct sbus_dev *sdev; 123 #endif 124 #ifdef EBUS_SUPPORT 125 struct pci_dev *pdev; 126 #endif 127 } dev_u; 128 unsigned int irq[2]; 129 unsigned int regs_size; 130 struct snd_cs4231 *next; 131 }; 132 133 static struct snd_cs4231 *cs4231_list; 134 135 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for 136 * now.... -DaveM 137 */ 138 139 /* IO ports */ 140 141 #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x) 142 143 /* XXX offsets are different than PC ISA chips... */ 144 #define c_d_c_CS4231REGSEL 0x0 145 #define c_d_c_CS4231REG 0x4 146 #define c_d_c_CS4231STATUS 0x8 147 #define c_d_c_CS4231PIO 0xc 148 149 /* codec registers */ 150 151 #define CS4231_LEFT_INPUT 0x00 /* left input control */ 152 #define CS4231_RIGHT_INPUT 0x01 /* right input control */ 153 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ 154 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ 155 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ 156 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ 157 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ 158 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ 159 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ 160 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ 161 #define CS4231_PIN_CTRL 0x0a /* pin control */ 162 #define CS4231_TEST_INIT 0x0b /* test and initialization */ 163 #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */ 164 #define CS4231_LOOPBACK 0x0d /* loopback control */ 165 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ 166 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ 167 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ 168 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ 169 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ 170 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ 171 #define CS4231_TIMER_LOW 0x14 /* timer low byte */ 172 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ 173 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ 174 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ 175 #define CS4236_EXT_REG 0x17 /* extended register access */ 176 #define CS4231_IRQ_STATUS 0x18 /* irq status register */ 177 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ 178 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ 179 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ 180 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ 181 #define CS4235_LEFT_MASTER 0x1b /* left master output control */ 182 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ 183 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */ 184 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ 185 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ 186 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ 187 188 /* definitions for codec register select port - CODECP( REGSEL ) */ 189 190 #define CS4231_INIT 0x80 /* CODEC is initializing */ 191 #define CS4231_MCE 0x40 /* mode change enable */ 192 #define CS4231_TRD 0x20 /* transfer request disable */ 193 194 /* definitions for codec status register - CODECP( STATUS ) */ 195 196 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ 197 198 /* definitions for codec irq status - CS4231_IRQ_STATUS */ 199 200 #define CS4231_PLAYBACK_IRQ 0x10 201 #define CS4231_RECORD_IRQ 0x20 202 #define CS4231_TIMER_IRQ 0x40 203 #define CS4231_ALL_IRQS 0x70 204 #define CS4231_REC_UNDERRUN 0x08 205 #define CS4231_REC_OVERRUN 0x04 206 #define CS4231_PLY_OVERRUN 0x02 207 #define CS4231_PLY_UNDERRUN 0x01 208 209 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ 210 211 #define CS4231_ENABLE_MIC_GAIN 0x20 212 213 #define CS4231_MIXS_LINE 0x00 214 #define CS4231_MIXS_AUX1 0x40 215 #define CS4231_MIXS_MIC 0x80 216 #define CS4231_MIXS_ALL 0xc0 217 218 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ 219 220 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ 221 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ 222 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ 223 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ 224 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ 225 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ 226 #define CS4231_STEREO 0x10 /* stereo mode */ 227 /* bits 3-1 define frequency divisor */ 228 #define CS4231_XTAL1 0x00 /* 24.576 crystal */ 229 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ 230 231 /* definitions for interface control register - CS4231_IFACE_CTRL */ 232 233 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ 234 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ 235 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ 236 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ 237 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ 238 #define CS4231_RECORD_ENABLE 0x02 /* record enable */ 239 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ 240 241 /* definitions for pin control register - CS4231_PIN_CTRL */ 242 243 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ 244 #define CS4231_XCTL1 0x40 /* external control #1 */ 245 #define CS4231_XCTL0 0x80 /* external control #0 */ 246 247 /* definitions for test and init register - CS4231_TEST_INIT */ 248 249 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ 250 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ 251 252 /* definitions for misc control register - CS4231_MISC_INFO */ 253 254 #define CS4231_MODE2 0x40 /* MODE 2 */ 255 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ 256 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ 257 258 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ 259 260 #define CS4231_DACZ 0x01 /* zero DAC when underrun */ 261 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ 262 #define CS4231_OLB 0x80 /* output level bit */ 263 264 /* SBUS DMA register defines. */ 265 266 #define APCCSR 0x10UL /* APC DMA CSR */ 267 #define APCCVA 0x20UL /* APC Capture DMA Address */ 268 #define APCCC 0x24UL /* APC Capture Count */ 269 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */ 270 #define APCCNC 0x2cUL /* APC Capture Next Count */ 271 #define APCPVA 0x30UL /* APC Play DMA Address */ 272 #define APCPC 0x34UL /* APC Play Count */ 273 #define APCPNVA 0x38UL /* APC Play DMA Next Address */ 274 #define APCPNC 0x3cUL /* APC Play Next Count */ 275 276 /* Defines for SBUS DMA-routines */ 277 278 #define APCVA 0x0UL /* APC DMA Address */ 279 #define APCC 0x4UL /* APC Count */ 280 #define APCNVA 0x8UL /* APC DMA Next Address */ 281 #define APCNC 0xcUL /* APC Next Count */ 282 #define APC_PLAY 0x30UL /* Play registers start at 0x30 */ 283 #define APC_RECORD 0x20UL /* Record registers start at 0x20 */ 284 285 /* APCCSR bits */ 286 287 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */ 288 #define APC_PLAY_INT 0x400000 /* Playback interrupt */ 289 #define APC_CAPT_INT 0x200000 /* Capture interrupt */ 290 #define APC_GENL_INT 0x100000 /* General interrupt */ 291 #define APC_XINT_ENA 0x80000 /* General ext int. enable */ 292 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */ 293 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */ 294 #define APC_XINT_GENL 0x10000 /* Error ext intr */ 295 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */ 296 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */ 297 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */ 298 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */ 299 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */ 300 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */ 301 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */ 302 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */ 303 #define APC_PPAUSE 0x80 /* Pause the play DMA */ 304 #define APC_CPAUSE 0x40 /* Pause the capture DMA */ 305 #define APC_CDC_RESET 0x20 /* CODEC RESET */ 306 #define APC_PDMA_READY 0x08 /* Play DMA Go */ 307 #define APC_CDMA_READY 0x04 /* Capture DMA Go */ 308 #define APC_CHIP_RESET 0x01 /* Reset the chip */ 309 310 /* EBUS DMA register offsets */ 311 312 #define EBDMA_CSR 0x00UL /* Control/Status */ 313 #define EBDMA_ADDR 0x04UL /* DMA Address */ 314 #define EBDMA_COUNT 0x08UL /* DMA Count */ 315 316 /* 317 * Some variables 318 */ 319 320 static unsigned char freq_bits[14] = { 321 /* 5510 */ 0x00 | CS4231_XTAL2, 322 /* 6620 */ 0x0E | CS4231_XTAL2, 323 /* 8000 */ 0x00 | CS4231_XTAL1, 324 /* 9600 */ 0x0E | CS4231_XTAL1, 325 /* 11025 */ 0x02 | CS4231_XTAL2, 326 /* 16000 */ 0x02 | CS4231_XTAL1, 327 /* 18900 */ 0x04 | CS4231_XTAL2, 328 /* 22050 */ 0x06 | CS4231_XTAL2, 329 /* 27042 */ 0x04 | CS4231_XTAL1, 330 /* 32000 */ 0x06 | CS4231_XTAL1, 331 /* 33075 */ 0x0C | CS4231_XTAL2, 332 /* 37800 */ 0x08 | CS4231_XTAL2, 333 /* 44100 */ 0x0A | CS4231_XTAL2, 334 /* 48000 */ 0x0C | CS4231_XTAL1 335 }; 336 337 static unsigned int rates[14] = { 338 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050, 339 27042, 32000, 33075, 37800, 44100, 48000 340 }; 341 342 static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 343 .count = 14, 344 .list = rates, 345 }; 346 347 static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime) 348 { 349 return snd_pcm_hw_constraint_list(runtime, 0, 350 SNDRV_PCM_HW_PARAM_RATE, 351 &hw_constraints_rates); 352 } 353 354 static unsigned char snd_cs4231_original_image[32] = 355 { 356 0x00, /* 00/00 - lic */ 357 0x00, /* 01/01 - ric */ 358 0x9f, /* 02/02 - la1ic */ 359 0x9f, /* 03/03 - ra1ic */ 360 0x9f, /* 04/04 - la2ic */ 361 0x9f, /* 05/05 - ra2ic */ 362 0xbf, /* 06/06 - loc */ 363 0xbf, /* 07/07 - roc */ 364 0x20, /* 08/08 - pdfr */ 365 CS4231_AUTOCALIB, /* 09/09 - ic */ 366 0x00, /* 0a/10 - pc */ 367 0x00, /* 0b/11 - ti */ 368 CS4231_MODE2, /* 0c/12 - mi */ 369 0x00, /* 0d/13 - lbc */ 370 0x00, /* 0e/14 - pbru */ 371 0x00, /* 0f/15 - pbrl */ 372 0x80, /* 10/16 - afei */ 373 0x01, /* 11/17 - afeii */ 374 0x9f, /* 12/18 - llic */ 375 0x9f, /* 13/19 - rlic */ 376 0x00, /* 14/20 - tlb */ 377 0x00, /* 15/21 - thb */ 378 0x00, /* 16/22 - la3mic/reserved */ 379 0x00, /* 17/23 - ra3mic/reserved */ 380 0x00, /* 18/24 - afs */ 381 0x00, /* 19/25 - lamoc/version */ 382 0x00, /* 1a/26 - mioc */ 383 0x00, /* 1b/27 - ramoc/reserved */ 384 0x20, /* 1c/28 - cdfr */ 385 0x00, /* 1d/29 - res4 */ 386 0x00, /* 1e/30 - cbru */ 387 0x00, /* 1f/31 - cbrl */ 388 }; 389 390 static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr) 391 { 392 #ifdef EBUS_SUPPORT 393 if (cp->flags & CS4231_FLAG_EBUS) { 394 return readb(reg_addr); 395 } else { 396 #endif 397 #ifdef SBUS_SUPPORT 398 return sbus_readb(reg_addr); 399 #endif 400 #ifdef EBUS_SUPPORT 401 } 402 #endif 403 } 404 405 static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, void __iomem *reg_addr) 406 { 407 #ifdef EBUS_SUPPORT 408 if (cp->flags & CS4231_FLAG_EBUS) { 409 return writeb(val, reg_addr); 410 } else { 411 #endif 412 #ifdef SBUS_SUPPORT 413 return sbus_writeb(val, reg_addr); 414 #endif 415 #ifdef EBUS_SUPPORT 416 } 417 #endif 418 } 419 420 /* 421 * Basic I/O functions 422 */ 423 424 static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg, 425 unsigned char mask, unsigned char value) 426 { 427 int timeout; 428 unsigned char tmp; 429 430 for (timeout = 250; 431 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 432 timeout--) 433 udelay(100); 434 #ifdef CONFIG_SND_DEBUG 435 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 436 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 437 #endif 438 if (chip->calibrate_mute) { 439 chip->image[reg] &= mask; 440 chip->image[reg] |= value; 441 } else { 442 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 443 mb(); 444 tmp = (chip->image[reg] & mask) | value; 445 __cs4231_writeb(chip, tmp, CS4231P(chip, REG)); 446 chip->image[reg] = tmp; 447 mb(); 448 } 449 } 450 451 static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value) 452 { 453 int timeout; 454 455 for (timeout = 250; 456 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 457 timeout--) 458 udelay(100); 459 #ifdef CONFIG_SND_DEBUG 460 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 461 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 462 #endif 463 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 464 __cs4231_writeb(chip, value, CS4231P(chip, REG)); 465 mb(); 466 } 467 468 static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value) 469 { 470 int timeout; 471 472 for (timeout = 250; 473 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 474 timeout--) 475 udelay(100); 476 #ifdef CONFIG_SND_DEBUG 477 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 478 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 479 #endif 480 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 481 __cs4231_writeb(chip, value, CS4231P(chip, REG)); 482 chip->image[reg] = value; 483 mb(); 484 } 485 486 static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg) 487 { 488 int timeout; 489 unsigned char ret; 490 491 for (timeout = 250; 492 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 493 timeout--) 494 udelay(100); 495 #ifdef CONFIG_SND_DEBUG 496 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 497 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg); 498 #endif 499 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 500 mb(); 501 ret = __cs4231_readb(chip, CS4231P(chip, REG)); 502 return ret; 503 } 504 505 /* 506 * CS4231 detection / MCE routines 507 */ 508 509 static void snd_cs4231_busy_wait(struct snd_cs4231 *chip) 510 { 511 int timeout; 512 513 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */ 514 for (timeout = 5; timeout > 0; timeout--) 515 __cs4231_readb(chip, CS4231P(chip, REGSEL)); 516 517 /* end of cleanup sequence */ 518 for (timeout = 500; 519 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 520 timeout--) 521 udelay(1000); 522 } 523 524 static void snd_cs4231_mce_up(struct snd_cs4231 *chip) 525 { 526 unsigned long flags; 527 int timeout; 528 529 spin_lock_irqsave(&chip->lock, flags); 530 for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--) 531 udelay(100); 532 #ifdef CONFIG_SND_DEBUG 533 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 534 snd_printdd("mce_up - auto calibration time out (0)\n"); 535 #endif 536 chip->mce_bit |= CS4231_MCE; 537 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL)); 538 if (timeout == 0x80) 539 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port); 540 if (!(timeout & CS4231_MCE)) 541 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL)); 542 spin_unlock_irqrestore(&chip->lock, flags); 543 } 544 545 static void snd_cs4231_mce_down(struct snd_cs4231 *chip) 546 { 547 unsigned long flags; 548 int timeout; 549 550 spin_lock_irqsave(&chip->lock, flags); 551 snd_cs4231_busy_wait(chip); 552 #ifdef CONFIG_SND_DEBUG 553 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 554 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL)); 555 #endif 556 chip->mce_bit &= ~CS4231_MCE; 557 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL)); 558 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL)); 559 if (timeout == 0x80) 560 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port); 561 if ((timeout & CS4231_MCE) == 0) { 562 spin_unlock_irqrestore(&chip->lock, flags); 563 return; 564 } 565 snd_cs4231_busy_wait(chip); 566 567 /* calibration process */ 568 569 for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--) 570 udelay(100); 571 if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) { 572 snd_printd("cs4231_mce_down - auto calibration time out (1)\n"); 573 spin_unlock_irqrestore(&chip->lock, flags); 574 return; 575 } 576 577 /* in 10ms increments, check condition, up to 250ms */ 578 timeout = 25; 579 while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) { 580 spin_unlock_irqrestore(&chip->lock, flags); 581 if (--timeout < 0) { 582 snd_printk("mce_down - auto calibration time out (2)\n"); 583 return; 584 } 585 msleep(10); 586 spin_lock_irqsave(&chip->lock, flags); 587 } 588 589 /* in 10ms increments, check condition, up to 100ms */ 590 timeout = 10; 591 while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) { 592 spin_unlock_irqrestore(&chip->lock, flags); 593 if (--timeout < 0) { 594 snd_printk("mce_down - auto calibration time out (3)\n"); 595 return; 596 } 597 msleep(10); 598 spin_lock_irqsave(&chip->lock, flags); 599 } 600 spin_unlock_irqrestore(&chip->lock, flags); 601 } 602 603 static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont, 604 struct snd_pcm_substream *substream, 605 unsigned int *periods_sent) 606 { 607 struct snd_pcm_runtime *runtime = substream->runtime; 608 609 while (1) { 610 unsigned int period_size = snd_pcm_lib_period_bytes(substream); 611 unsigned int offset = period_size * (*periods_sent); 612 613 if (period_size >= (1 << 24)) 614 BUG(); 615 616 if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size)) 617 return; 618 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods; 619 } 620 } 621 622 static void cs4231_dma_trigger(struct snd_pcm_substream *substream, 623 unsigned int what, int on) 624 { 625 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 626 struct cs4231_dma_control *dma_cont; 627 628 if (what & CS4231_PLAYBACK_ENABLE) { 629 dma_cont = &chip->p_dma; 630 if (on) { 631 dma_cont->prepare(dma_cont, 0); 632 dma_cont->enable(dma_cont, 1); 633 snd_cs4231_advance_dma(dma_cont, 634 chip->playback_substream, 635 &chip->p_periods_sent); 636 } else { 637 dma_cont->enable(dma_cont, 0); 638 } 639 } 640 if (what & CS4231_RECORD_ENABLE) { 641 dma_cont = &chip->c_dma; 642 if (on) { 643 dma_cont->prepare(dma_cont, 1); 644 dma_cont->enable(dma_cont, 1); 645 snd_cs4231_advance_dma(dma_cont, 646 chip->capture_substream, 647 &chip->c_periods_sent); 648 } else { 649 dma_cont->enable(dma_cont, 0); 650 } 651 } 652 } 653 654 static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd) 655 { 656 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 657 int result = 0; 658 659 switch (cmd) { 660 case SNDRV_PCM_TRIGGER_START: 661 case SNDRV_PCM_TRIGGER_STOP: 662 { 663 unsigned int what = 0; 664 struct snd_pcm_substream *s; 665 struct list_head *pos; 666 unsigned long flags; 667 668 snd_pcm_group_for_each(pos, substream) { 669 s = snd_pcm_group_substream_entry(pos); 670 if (s == chip->playback_substream) { 671 what |= CS4231_PLAYBACK_ENABLE; 672 snd_pcm_trigger_done(s, substream); 673 } else if (s == chip->capture_substream) { 674 what |= CS4231_RECORD_ENABLE; 675 snd_pcm_trigger_done(s, substream); 676 } 677 } 678 679 spin_lock_irqsave(&chip->lock, flags); 680 if (cmd == SNDRV_PCM_TRIGGER_START) { 681 cs4231_dma_trigger(substream, what, 1); 682 chip->image[CS4231_IFACE_CTRL] |= what; 683 } else { 684 cs4231_dma_trigger(substream, what, 0); 685 chip->image[CS4231_IFACE_CTRL] &= ~what; 686 } 687 snd_cs4231_out(chip, CS4231_IFACE_CTRL, 688 chip->image[CS4231_IFACE_CTRL]); 689 spin_unlock_irqrestore(&chip->lock, flags); 690 break; 691 } 692 default: 693 result = -EINVAL; 694 break; 695 } 696 697 return result; 698 } 699 700 /* 701 * CODEC I/O 702 */ 703 704 static unsigned char snd_cs4231_get_rate(unsigned int rate) 705 { 706 int i; 707 708 for (i = 0; i < 14; i++) 709 if (rate == rates[i]) 710 return freq_bits[i]; 711 // snd_BUG(); 712 return freq_bits[13]; 713 } 714 715 static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format, int channels) 716 { 717 unsigned char rformat; 718 719 rformat = CS4231_LINEAR_8; 720 switch (format) { 721 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break; 722 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break; 723 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break; 724 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break; 725 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break; 726 } 727 if (channels > 1) 728 rformat |= CS4231_STEREO; 729 return rformat; 730 } 731 732 static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute) 733 { 734 unsigned long flags; 735 736 mute = mute ? 1 : 0; 737 spin_lock_irqsave(&chip->lock, flags); 738 if (chip->calibrate_mute == mute) { 739 spin_unlock_irqrestore(&chip->lock, flags); 740 return; 741 } 742 if (!mute) { 743 snd_cs4231_dout(chip, CS4231_LEFT_INPUT, 744 chip->image[CS4231_LEFT_INPUT]); 745 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, 746 chip->image[CS4231_RIGHT_INPUT]); 747 snd_cs4231_dout(chip, CS4231_LOOPBACK, 748 chip->image[CS4231_LOOPBACK]); 749 } 750 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, 751 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]); 752 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, 753 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]); 754 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, 755 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]); 756 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, 757 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]); 758 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, 759 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]); 760 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, 761 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]); 762 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, 763 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]); 764 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, 765 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]); 766 snd_cs4231_dout(chip, CS4231_MONO_CTRL, 767 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]); 768 chip->calibrate_mute = mute; 769 spin_unlock_irqrestore(&chip->lock, flags); 770 } 771 772 static void snd_cs4231_playback_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params, 773 unsigned char pdfr) 774 { 775 unsigned long flags; 776 777 down(&chip->mce_mutex); 778 snd_cs4231_calibrate_mute(chip, 1); 779 780 snd_cs4231_mce_up(chip); 781 782 spin_lock_irqsave(&chip->lock, flags); 783 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 784 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ? 785 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) : 786 pdfr); 787 spin_unlock_irqrestore(&chip->lock, flags); 788 789 snd_cs4231_mce_down(chip); 790 791 snd_cs4231_calibrate_mute(chip, 0); 792 up(&chip->mce_mutex); 793 } 794 795 static void snd_cs4231_capture_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params, 796 unsigned char cdfr) 797 { 798 unsigned long flags; 799 800 down(&chip->mce_mutex); 801 snd_cs4231_calibrate_mute(chip, 1); 802 803 snd_cs4231_mce_up(chip); 804 805 spin_lock_irqsave(&chip->lock, flags); 806 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) { 807 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 808 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) | 809 (cdfr & 0x0f)); 810 spin_unlock_irqrestore(&chip->lock, flags); 811 snd_cs4231_mce_down(chip); 812 snd_cs4231_mce_up(chip); 813 spin_lock_irqsave(&chip->lock, flags); 814 } 815 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr); 816 spin_unlock_irqrestore(&chip->lock, flags); 817 818 snd_cs4231_mce_down(chip); 819 820 snd_cs4231_calibrate_mute(chip, 0); 821 up(&chip->mce_mutex); 822 } 823 824 /* 825 * Timer interface 826 */ 827 828 static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer) 829 { 830 struct snd_cs4231 *chip = snd_timer_chip(timer); 831 832 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920; 833 } 834 835 static int snd_cs4231_timer_start(struct snd_timer *timer) 836 { 837 unsigned long flags; 838 unsigned int ticks; 839 struct snd_cs4231 *chip = snd_timer_chip(timer); 840 841 spin_lock_irqsave(&chip->lock, flags); 842 ticks = timer->sticks; 843 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 || 844 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] || 845 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) { 846 snd_cs4231_out(chip, CS4231_TIMER_HIGH, 847 chip->image[CS4231_TIMER_HIGH] = 848 (unsigned char) (ticks >> 8)); 849 snd_cs4231_out(chip, CS4231_TIMER_LOW, 850 chip->image[CS4231_TIMER_LOW] = 851 (unsigned char) ticks); 852 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 853 chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE); 854 } 855 spin_unlock_irqrestore(&chip->lock, flags); 856 857 return 0; 858 } 859 860 static int snd_cs4231_timer_stop(struct snd_timer *timer) 861 { 862 unsigned long flags; 863 struct snd_cs4231 *chip = snd_timer_chip(timer); 864 865 spin_lock_irqsave(&chip->lock, flags); 866 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 867 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE); 868 spin_unlock_irqrestore(&chip->lock, flags); 869 870 return 0; 871 } 872 873 static void __init snd_cs4231_init(struct snd_cs4231 *chip) 874 { 875 unsigned long flags; 876 877 snd_cs4231_mce_down(chip); 878 879 #ifdef SNDRV_DEBUG_MCE 880 snd_printdd("init: (1)\n"); 881 #endif 882 snd_cs4231_mce_up(chip); 883 spin_lock_irqsave(&chip->lock, flags); 884 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 885 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO | 886 CS4231_CALIB_MODE); 887 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB; 888 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 889 spin_unlock_irqrestore(&chip->lock, flags); 890 snd_cs4231_mce_down(chip); 891 892 #ifdef SNDRV_DEBUG_MCE 893 snd_printdd("init: (2)\n"); 894 #endif 895 896 snd_cs4231_mce_up(chip); 897 spin_lock_irqsave(&chip->lock, flags); 898 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]); 899 spin_unlock_irqrestore(&chip->lock, flags); 900 snd_cs4231_mce_down(chip); 901 902 #ifdef SNDRV_DEBUG_MCE 903 snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]); 904 #endif 905 906 spin_lock_irqsave(&chip->lock, flags); 907 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]); 908 spin_unlock_irqrestore(&chip->lock, flags); 909 910 snd_cs4231_mce_up(chip); 911 spin_lock_irqsave(&chip->lock, flags); 912 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]); 913 spin_unlock_irqrestore(&chip->lock, flags); 914 snd_cs4231_mce_down(chip); 915 916 #ifdef SNDRV_DEBUG_MCE 917 snd_printdd("init: (4)\n"); 918 #endif 919 920 snd_cs4231_mce_up(chip); 921 spin_lock_irqsave(&chip->lock, flags); 922 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]); 923 spin_unlock_irqrestore(&chip->lock, flags); 924 snd_cs4231_mce_down(chip); 925 926 #ifdef SNDRV_DEBUG_MCE 927 snd_printdd("init: (5)\n"); 928 #endif 929 } 930 931 static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode) 932 { 933 unsigned long flags; 934 935 down(&chip->open_mutex); 936 if ((chip->mode & mode)) { 937 up(&chip->open_mutex); 938 return -EAGAIN; 939 } 940 if (chip->mode & CS4231_MODE_OPEN) { 941 chip->mode |= mode; 942 up(&chip->open_mutex); 943 return 0; 944 } 945 /* ok. now enable and ack CODEC IRQ */ 946 spin_lock_irqsave(&chip->lock, flags); 947 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 948 CS4231_RECORD_IRQ | 949 CS4231_TIMER_IRQ); 950 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 951 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 952 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 953 954 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 955 CS4231_RECORD_IRQ | 956 CS4231_TIMER_IRQ); 957 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 958 959 spin_unlock_irqrestore(&chip->lock, flags); 960 961 chip->mode = mode; 962 up(&chip->open_mutex); 963 return 0; 964 } 965 966 static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode) 967 { 968 unsigned long flags; 969 970 down(&chip->open_mutex); 971 chip->mode &= ~mode; 972 if (chip->mode & CS4231_MODE_OPEN) { 973 up(&chip->open_mutex); 974 return; 975 } 976 snd_cs4231_calibrate_mute(chip, 1); 977 978 /* disable IRQ */ 979 spin_lock_irqsave(&chip->lock, flags); 980 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 981 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 982 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 983 984 /* now disable record & playback */ 985 986 if (chip->image[CS4231_IFACE_CTRL] & 987 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 988 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) { 989 spin_unlock_irqrestore(&chip->lock, flags); 990 snd_cs4231_mce_up(chip); 991 spin_lock_irqsave(&chip->lock, flags); 992 chip->image[CS4231_IFACE_CTRL] &= 993 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 994 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO); 995 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 996 spin_unlock_irqrestore(&chip->lock, flags); 997 snd_cs4231_mce_down(chip); 998 spin_lock_irqsave(&chip->lock, flags); 999 } 1000 1001 /* clear IRQ again */ 1002 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 1003 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 1004 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 1005 spin_unlock_irqrestore(&chip->lock, flags); 1006 1007 snd_cs4231_calibrate_mute(chip, 0); 1008 1009 chip->mode = 0; 1010 up(&chip->open_mutex); 1011 } 1012 1013 /* 1014 * timer open/close 1015 */ 1016 1017 static int snd_cs4231_timer_open(struct snd_timer *timer) 1018 { 1019 struct snd_cs4231 *chip = snd_timer_chip(timer); 1020 snd_cs4231_open(chip, CS4231_MODE_TIMER); 1021 return 0; 1022 } 1023 1024 static int snd_cs4231_timer_close(struct snd_timer * timer) 1025 { 1026 struct snd_cs4231 *chip = snd_timer_chip(timer); 1027 snd_cs4231_close(chip, CS4231_MODE_TIMER); 1028 return 0; 1029 } 1030 1031 static struct snd_timer_hardware snd_cs4231_timer_table = 1032 { 1033 .flags = SNDRV_TIMER_HW_AUTO, 1034 .resolution = 9945, 1035 .ticks = 65535, 1036 .open = snd_cs4231_timer_open, 1037 .close = snd_cs4231_timer_close, 1038 .c_resolution = snd_cs4231_timer_resolution, 1039 .start = snd_cs4231_timer_start, 1040 .stop = snd_cs4231_timer_stop, 1041 }; 1042 1043 /* 1044 * ok.. exported functions.. 1045 */ 1046 1047 static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream, 1048 struct snd_pcm_hw_params *hw_params) 1049 { 1050 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1051 unsigned char new_pdfr; 1052 int err; 1053 1054 if ((err = snd_pcm_lib_malloc_pages(substream, 1055 params_buffer_bytes(hw_params))) < 0) 1056 return err; 1057 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), 1058 params_channels(hw_params)) | 1059 snd_cs4231_get_rate(params_rate(hw_params)); 1060 snd_cs4231_playback_format(chip, hw_params, new_pdfr); 1061 1062 return 0; 1063 } 1064 1065 static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream) 1066 { 1067 return snd_pcm_lib_free_pages(substream); 1068 } 1069 1070 static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream) 1071 { 1072 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1073 struct snd_pcm_runtime *runtime = substream->runtime; 1074 unsigned long flags; 1075 1076 spin_lock_irqsave(&chip->lock, flags); 1077 1078 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | 1079 CS4231_PLAYBACK_PIO); 1080 1081 if (runtime->period_size > 0xffff + 1) 1082 BUG(); 1083 1084 chip->p_periods_sent = 0; 1085 spin_unlock_irqrestore(&chip->lock, flags); 1086 1087 return 0; 1088 } 1089 1090 static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream, 1091 struct snd_pcm_hw_params *hw_params) 1092 { 1093 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1094 unsigned char new_cdfr; 1095 int err; 1096 1097 if ((err = snd_pcm_lib_malloc_pages(substream, 1098 params_buffer_bytes(hw_params))) < 0) 1099 return err; 1100 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), 1101 params_channels(hw_params)) | 1102 snd_cs4231_get_rate(params_rate(hw_params)); 1103 snd_cs4231_capture_format(chip, hw_params, new_cdfr); 1104 1105 return 0; 1106 } 1107 1108 static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream) 1109 { 1110 return snd_pcm_lib_free_pages(substream); 1111 } 1112 1113 static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream) 1114 { 1115 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1116 unsigned long flags; 1117 1118 spin_lock_irqsave(&chip->lock, flags); 1119 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | 1120 CS4231_RECORD_PIO); 1121 1122 1123 chip->c_periods_sent = 0; 1124 spin_unlock_irqrestore(&chip->lock, flags); 1125 1126 return 0; 1127 } 1128 1129 static void snd_cs4231_overrange(struct snd_cs4231 *chip) 1130 { 1131 unsigned long flags; 1132 unsigned char res; 1133 1134 spin_lock_irqsave(&chip->lock, flags); 1135 res = snd_cs4231_in(chip, CS4231_TEST_INIT); 1136 spin_unlock_irqrestore(&chip->lock, flags); 1137 1138 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */ 1139 chip->capture_substream->runtime->overrange++; 1140 } 1141 1142 static void snd_cs4231_play_callback(struct snd_cs4231 *chip) 1143 { 1144 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) { 1145 snd_pcm_period_elapsed(chip->playback_substream); 1146 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream, 1147 &chip->p_periods_sent); 1148 } 1149 } 1150 1151 static void snd_cs4231_capture_callback(struct snd_cs4231 *chip) 1152 { 1153 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) { 1154 snd_pcm_period_elapsed(chip->capture_substream); 1155 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream, 1156 &chip->c_periods_sent); 1157 } 1158 } 1159 1160 static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream) 1161 { 1162 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1163 struct cs4231_dma_control *dma_cont = &chip->p_dma; 1164 size_t ptr; 1165 1166 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) 1167 return 0; 1168 ptr = dma_cont->address(dma_cont); 1169 if (ptr != 0) 1170 ptr -= substream->runtime->dma_addr; 1171 1172 return bytes_to_frames(substream->runtime, ptr); 1173 } 1174 1175 static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream) 1176 { 1177 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1178 struct cs4231_dma_control *dma_cont = &chip->c_dma; 1179 size_t ptr; 1180 1181 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)) 1182 return 0; 1183 ptr = dma_cont->address(dma_cont); 1184 if (ptr != 0) 1185 ptr -= substream->runtime->dma_addr; 1186 1187 return bytes_to_frames(substream->runtime, ptr); 1188 } 1189 1190 /* 1191 1192 */ 1193 1194 static int __init snd_cs4231_probe(struct snd_cs4231 *chip) 1195 { 1196 unsigned long flags; 1197 int i, id, vers; 1198 unsigned char *ptr; 1199 1200 id = vers = 0; 1201 for (i = 0; i < 50; i++) { 1202 mb(); 1203 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 1204 udelay(2000); 1205 else { 1206 spin_lock_irqsave(&chip->lock, flags); 1207 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2); 1208 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f; 1209 vers = snd_cs4231_in(chip, CS4231_VERSION); 1210 spin_unlock_irqrestore(&chip->lock, flags); 1211 if (id == 0x0a) 1212 break; /* this is valid value */ 1213 } 1214 } 1215 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id); 1216 if (id != 0x0a) 1217 return -ENODEV; /* no valid device found */ 1218 1219 spin_lock_irqsave(&chip->lock, flags); 1220 1221 1222 /* Reset DMA engine (sbus only). */ 1223 chip->p_dma.reset(chip); 1224 1225 __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */ 1226 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); 1227 mb(); 1228 1229 spin_unlock_irqrestore(&chip->lock, flags); 1230 1231 chip->image[CS4231_MISC_INFO] = CS4231_MODE2; 1232 chip->image[CS4231_IFACE_CTRL] = 1233 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA; 1234 chip->image[CS4231_ALT_FEATURE_1] = 0x80; 1235 chip->image[CS4231_ALT_FEATURE_2] = 0x01; 1236 if (vers & 0x20) 1237 chip->image[CS4231_ALT_FEATURE_2] |= 0x02; 1238 1239 ptr = (unsigned char *) &chip->image; 1240 1241 snd_cs4231_mce_down(chip); 1242 1243 spin_lock_irqsave(&chip->lock, flags); 1244 1245 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */ 1246 snd_cs4231_out(chip, i, *ptr++); 1247 1248 spin_unlock_irqrestore(&chip->lock, flags); 1249 1250 snd_cs4231_mce_up(chip); 1251 1252 snd_cs4231_mce_down(chip); 1253 1254 mdelay(2); 1255 1256 return 0; /* all things are ok.. */ 1257 } 1258 1259 static struct snd_pcm_hardware snd_cs4231_playback = 1260 { 1261 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1262 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1263 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | 1264 SNDRV_PCM_FMTBIT_IMA_ADPCM | 1265 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | 1266 SNDRV_PCM_FMTBIT_S16_BE), 1267 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, 1268 .rate_min = 5510, 1269 .rate_max = 48000, 1270 .channels_min = 1, 1271 .channels_max = 2, 1272 .buffer_bytes_max = (32*1024), 1273 .period_bytes_min = 4096, 1274 .period_bytes_max = (32*1024), 1275 .periods_min = 1, 1276 .periods_max = 1024, 1277 }; 1278 1279 static struct snd_pcm_hardware snd_cs4231_capture = 1280 { 1281 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1282 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1283 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | 1284 SNDRV_PCM_FMTBIT_IMA_ADPCM | 1285 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | 1286 SNDRV_PCM_FMTBIT_S16_BE), 1287 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, 1288 .rate_min = 5510, 1289 .rate_max = 48000, 1290 .channels_min = 1, 1291 .channels_max = 2, 1292 .buffer_bytes_max = (32*1024), 1293 .period_bytes_min = 4096, 1294 .period_bytes_max = (32*1024), 1295 .periods_min = 1, 1296 .periods_max = 1024, 1297 }; 1298 1299 static int snd_cs4231_playback_open(struct snd_pcm_substream *substream) 1300 { 1301 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1302 struct snd_pcm_runtime *runtime = substream->runtime; 1303 int err; 1304 1305 runtime->hw = snd_cs4231_playback; 1306 1307 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) { 1308 snd_free_pages(runtime->dma_area, runtime->dma_bytes); 1309 return err; 1310 } 1311 chip->playback_substream = substream; 1312 chip->p_periods_sent = 0; 1313 snd_pcm_set_sync(substream); 1314 snd_cs4231_xrate(runtime); 1315 1316 return 0; 1317 } 1318 1319 static int snd_cs4231_capture_open(struct snd_pcm_substream *substream) 1320 { 1321 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1322 struct snd_pcm_runtime *runtime = substream->runtime; 1323 int err; 1324 1325 runtime->hw = snd_cs4231_capture; 1326 1327 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) { 1328 snd_free_pages(runtime->dma_area, runtime->dma_bytes); 1329 return err; 1330 } 1331 chip->capture_substream = substream; 1332 chip->c_periods_sent = 0; 1333 snd_pcm_set_sync(substream); 1334 snd_cs4231_xrate(runtime); 1335 1336 return 0; 1337 } 1338 1339 static int snd_cs4231_playback_close(struct snd_pcm_substream *substream) 1340 { 1341 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1342 1343 snd_cs4231_close(chip, CS4231_MODE_PLAY); 1344 chip->playback_substream = NULL; 1345 1346 return 0; 1347 } 1348 1349 static int snd_cs4231_capture_close(struct snd_pcm_substream *substream) 1350 { 1351 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1352 1353 snd_cs4231_close(chip, CS4231_MODE_RECORD); 1354 chip->capture_substream = NULL; 1355 1356 return 0; 1357 } 1358 1359 /* XXX We can do some power-management, in particular on EBUS using 1360 * XXX the audio AUXIO register... 1361 */ 1362 1363 static struct snd_pcm_ops snd_cs4231_playback_ops = { 1364 .open = snd_cs4231_playback_open, 1365 .close = snd_cs4231_playback_close, 1366 .ioctl = snd_pcm_lib_ioctl, 1367 .hw_params = snd_cs4231_playback_hw_params, 1368 .hw_free = snd_cs4231_playback_hw_free, 1369 .prepare = snd_cs4231_playback_prepare, 1370 .trigger = snd_cs4231_trigger, 1371 .pointer = snd_cs4231_playback_pointer, 1372 }; 1373 1374 static struct snd_pcm_ops snd_cs4231_capture_ops = { 1375 .open = snd_cs4231_capture_open, 1376 .close = snd_cs4231_capture_close, 1377 .ioctl = snd_pcm_lib_ioctl, 1378 .hw_params = snd_cs4231_capture_hw_params, 1379 .hw_free = snd_cs4231_capture_hw_free, 1380 .prepare = snd_cs4231_capture_prepare, 1381 .trigger = snd_cs4231_trigger, 1382 .pointer = snd_cs4231_capture_pointer, 1383 }; 1384 1385 static int __init snd_cs4231_pcm(struct snd_cs4231 *chip) 1386 { 1387 struct snd_pcm *pcm; 1388 int err; 1389 1390 if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0) 1391 return err; 1392 1393 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops); 1394 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops); 1395 1396 /* global setup */ 1397 pcm->private_data = chip; 1398 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1399 strcpy(pcm->name, "CS4231"); 1400 1401 chip->p_dma.preallocate(chip, pcm); 1402 1403 chip->pcm = pcm; 1404 1405 return 0; 1406 } 1407 1408 static int __init snd_cs4231_timer(struct snd_cs4231 *chip) 1409 { 1410 struct snd_timer *timer; 1411 struct snd_timer_id tid; 1412 int err; 1413 1414 /* Timer initialization */ 1415 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 1416 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 1417 tid.card = chip->card->number; 1418 tid.device = 0; 1419 tid.subdevice = 0; 1420 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0) 1421 return err; 1422 strcpy(timer->name, "CS4231"); 1423 timer->private_data = chip; 1424 timer->hw = snd_cs4231_timer_table; 1425 chip->timer = timer; 1426 1427 return 0; 1428 } 1429 1430 /* 1431 * MIXER part 1432 */ 1433 1434 static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, 1435 struct snd_ctl_elem_info *uinfo) 1436 { 1437 static char *texts[4] = { 1438 "Line", "CD", "Mic", "Mix" 1439 }; 1440 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1441 1442 snd_assert(chip->card != NULL, return -EINVAL); 1443 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1444 uinfo->count = 2; 1445 uinfo->value.enumerated.items = 4; 1446 if (uinfo->value.enumerated.item > 3) 1447 uinfo->value.enumerated.item = 3; 1448 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1449 1450 return 0; 1451 } 1452 1453 static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, 1454 struct snd_ctl_elem_value *ucontrol) 1455 { 1456 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1457 unsigned long flags; 1458 1459 spin_lock_irqsave(&chip->lock, flags); 1460 ucontrol->value.enumerated.item[0] = 1461 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6; 1462 ucontrol->value.enumerated.item[1] = 1463 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6; 1464 spin_unlock_irqrestore(&chip->lock, flags); 1465 1466 return 0; 1467 } 1468 1469 static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, 1470 struct snd_ctl_elem_value *ucontrol) 1471 { 1472 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1473 unsigned long flags; 1474 unsigned short left, right; 1475 int change; 1476 1477 if (ucontrol->value.enumerated.item[0] > 3 || 1478 ucontrol->value.enumerated.item[1] > 3) 1479 return -EINVAL; 1480 left = ucontrol->value.enumerated.item[0] << 6; 1481 right = ucontrol->value.enumerated.item[1] << 6; 1482 1483 spin_lock_irqsave(&chip->lock, flags); 1484 1485 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left; 1486 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right; 1487 change = left != chip->image[CS4231_LEFT_INPUT] || 1488 right != chip->image[CS4231_RIGHT_INPUT]; 1489 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left); 1490 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right); 1491 1492 spin_unlock_irqrestore(&chip->lock, flags); 1493 1494 return change; 1495 } 1496 1497 static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, 1498 struct snd_ctl_elem_info *uinfo) 1499 { 1500 int mask = (kcontrol->private_value >> 16) & 0xff; 1501 1502 uinfo->type = (mask == 1) ? 1503 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1504 uinfo->count = 1; 1505 uinfo->value.integer.min = 0; 1506 uinfo->value.integer.max = mask; 1507 1508 return 0; 1509 } 1510 1511 static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, 1512 struct snd_ctl_elem_value *ucontrol) 1513 { 1514 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1515 unsigned long flags; 1516 int reg = kcontrol->private_value & 0xff; 1517 int shift = (kcontrol->private_value >> 8) & 0xff; 1518 int mask = (kcontrol->private_value >> 16) & 0xff; 1519 int invert = (kcontrol->private_value >> 24) & 0xff; 1520 1521 spin_lock_irqsave(&chip->lock, flags); 1522 1523 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; 1524 1525 spin_unlock_irqrestore(&chip->lock, flags); 1526 1527 if (invert) 1528 ucontrol->value.integer.value[0] = 1529 (mask - ucontrol->value.integer.value[0]); 1530 1531 return 0; 1532 } 1533 1534 static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, 1535 struct snd_ctl_elem_value *ucontrol) 1536 { 1537 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1538 unsigned long flags; 1539 int reg = kcontrol->private_value & 0xff; 1540 int shift = (kcontrol->private_value >> 8) & 0xff; 1541 int mask = (kcontrol->private_value >> 16) & 0xff; 1542 int invert = (kcontrol->private_value >> 24) & 0xff; 1543 int change; 1544 unsigned short val; 1545 1546 val = (ucontrol->value.integer.value[0] & mask); 1547 if (invert) 1548 val = mask - val; 1549 val <<= shift; 1550 1551 spin_lock_irqsave(&chip->lock, flags); 1552 1553 val = (chip->image[reg] & ~(mask << shift)) | val; 1554 change = val != chip->image[reg]; 1555 snd_cs4231_out(chip, reg, val); 1556 1557 spin_unlock_irqrestore(&chip->lock, flags); 1558 1559 return change; 1560 } 1561 1562 static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, 1563 struct snd_ctl_elem_info *uinfo) 1564 { 1565 int mask = (kcontrol->private_value >> 24) & 0xff; 1566 1567 uinfo->type = mask == 1 ? 1568 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1569 uinfo->count = 2; 1570 uinfo->value.integer.min = 0; 1571 uinfo->value.integer.max = mask; 1572 1573 return 0; 1574 } 1575 1576 static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, 1577 struct snd_ctl_elem_value *ucontrol) 1578 { 1579 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1580 unsigned long flags; 1581 int left_reg = kcontrol->private_value & 0xff; 1582 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1583 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1584 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1585 int mask = (kcontrol->private_value >> 24) & 0xff; 1586 int invert = (kcontrol->private_value >> 22) & 1; 1587 1588 spin_lock_irqsave(&chip->lock, flags); 1589 1590 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask; 1591 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask; 1592 1593 spin_unlock_irqrestore(&chip->lock, flags); 1594 1595 if (invert) { 1596 ucontrol->value.integer.value[0] = 1597 (mask - ucontrol->value.integer.value[0]); 1598 ucontrol->value.integer.value[1] = 1599 (mask - ucontrol->value.integer.value[1]); 1600 } 1601 1602 return 0; 1603 } 1604 1605 static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, 1606 struct snd_ctl_elem_value *ucontrol) 1607 { 1608 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1609 unsigned long flags; 1610 int left_reg = kcontrol->private_value & 0xff; 1611 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1612 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1613 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1614 int mask = (kcontrol->private_value >> 24) & 0xff; 1615 int invert = (kcontrol->private_value >> 22) & 1; 1616 int change; 1617 unsigned short val1, val2; 1618 1619 val1 = ucontrol->value.integer.value[0] & mask; 1620 val2 = ucontrol->value.integer.value[1] & mask; 1621 if (invert) { 1622 val1 = mask - val1; 1623 val2 = mask - val2; 1624 } 1625 val1 <<= shift_left; 1626 val2 <<= shift_right; 1627 1628 spin_lock_irqsave(&chip->lock, flags); 1629 1630 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; 1631 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; 1632 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg]; 1633 snd_cs4231_out(chip, left_reg, val1); 1634 snd_cs4231_out(chip, right_reg, val2); 1635 1636 spin_unlock_irqrestore(&chip->lock, flags); 1637 1638 return change; 1639 } 1640 1641 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ 1642 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1643 .info = snd_cs4231_info_single, \ 1644 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \ 1645 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } 1646 1647 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ 1648 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1649 .info = snd_cs4231_info_double, \ 1650 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \ 1651 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } 1652 1653 static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = { 1654 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1), 1655 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1), 1656 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1), 1657 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1), 1658 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1), 1659 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1), 1660 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1), 1661 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1), 1662 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1), 1663 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1), 1664 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1), 1665 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0), 1666 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0), 1667 { 1668 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1669 .name = "Capture Source", 1670 .info = snd_cs4231_info_mux, 1671 .get = snd_cs4231_get_mux, 1672 .put = snd_cs4231_put_mux, 1673 }, 1674 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0), 1675 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0), 1676 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1), 1677 /* SPARC specific uses of XCTL{0,1} general purpose outputs. */ 1678 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1), 1679 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1) 1680 }; 1681 1682 static int __init snd_cs4231_mixer(struct snd_cs4231 *chip) 1683 { 1684 struct snd_card *card; 1685 int err, idx; 1686 1687 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL); 1688 1689 card = chip->card; 1690 1691 strcpy(card->mixername, chip->pcm->name); 1692 1693 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) { 1694 if ((err = snd_ctl_add(card, 1695 snd_ctl_new1(&snd_cs4231_controls[idx], 1696 chip))) < 0) 1697 return err; 1698 } 1699 return 0; 1700 } 1701 1702 static int dev; 1703 1704 static int __init cs4231_attach_begin(struct snd_card **rcard) 1705 { 1706 struct snd_card *card; 1707 1708 *rcard = NULL; 1709 1710 if (dev >= SNDRV_CARDS) 1711 return -ENODEV; 1712 1713 if (!enable[dev]) { 1714 dev++; 1715 return -ENOENT; 1716 } 1717 1718 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1719 if (card == NULL) 1720 return -ENOMEM; 1721 1722 strcpy(card->driver, "CS4231"); 1723 strcpy(card->shortname, "Sun CS4231"); 1724 1725 *rcard = card; 1726 return 0; 1727 } 1728 1729 static int __init cs4231_attach_finish(struct snd_card *card, struct snd_cs4231 *chip) 1730 { 1731 int err; 1732 1733 if ((err = snd_cs4231_pcm(chip)) < 0) 1734 goto out_err; 1735 1736 if ((err = snd_cs4231_mixer(chip)) < 0) 1737 goto out_err; 1738 1739 if ((err = snd_cs4231_timer(chip)) < 0) 1740 goto out_err; 1741 1742 if ((err = snd_card_register(card)) < 0) 1743 goto out_err; 1744 1745 chip->next = cs4231_list; 1746 cs4231_list = chip; 1747 1748 dev++; 1749 return 0; 1750 1751 out_err: 1752 snd_card_free(card); 1753 return err; 1754 } 1755 1756 #ifdef SBUS_SUPPORT 1757 1758 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1759 { 1760 unsigned long flags; 1761 unsigned char status; 1762 u32 csr; 1763 struct snd_cs4231 *chip = dev_id; 1764 1765 /*This is IRQ is not raised by the cs4231*/ 1766 if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ)) 1767 return IRQ_NONE; 1768 1769 /* ACK the APC interrupt. */ 1770 csr = sbus_readl(chip->port + APCCSR); 1771 1772 sbus_writel(csr, chip->port + APCCSR); 1773 1774 if ((csr & APC_PDMA_READY) && 1775 (csr & APC_PLAY_INT) && 1776 (csr & APC_XINT_PNVA) && 1777 !(csr & APC_XINT_EMPT)) 1778 snd_cs4231_play_callback(chip); 1779 1780 if ((csr & APC_CDMA_READY) && 1781 (csr & APC_CAPT_INT) && 1782 (csr & APC_XINT_CNVA) && 1783 !(csr & APC_XINT_EMPT)) 1784 snd_cs4231_capture_callback(chip); 1785 1786 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS); 1787 1788 if (status & CS4231_TIMER_IRQ) { 1789 if (chip->timer) 1790 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1791 } 1792 1793 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY)) 1794 snd_cs4231_overrange(chip); 1795 1796 /* ACK the CS4231 interrupt. */ 1797 spin_lock_irqsave(&chip->lock, flags); 1798 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0); 1799 spin_unlock_irqrestore(&chip->lock, flags); 1800 1801 return 0; 1802 } 1803 1804 /* 1805 * SBUS DMA routines 1806 */ 1807 1808 static int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len) 1809 { 1810 unsigned long flags; 1811 u32 test, csr; 1812 int err; 1813 struct sbus_dma_info *base = &dma_cont->sbus_info; 1814 1815 if (len >= (1 << 24)) 1816 return -EINVAL; 1817 spin_lock_irqsave(&base->lock, flags); 1818 csr = sbus_readl(base->regs + APCCSR); 1819 err = -EINVAL; 1820 test = APC_CDMA_READY; 1821 if ( base->dir == APC_PLAY ) 1822 test = APC_PDMA_READY; 1823 if (!(csr & test)) 1824 goto out; 1825 err = -EBUSY; 1826 csr = sbus_readl(base->regs + APCCSR); 1827 test = APC_XINT_CNVA; 1828 if ( base->dir == APC_PLAY ) 1829 test = APC_XINT_PNVA; 1830 if (!(csr & test)) 1831 goto out; 1832 err = 0; 1833 sbus_writel(bus_addr, base->regs + base->dir + APCNVA); 1834 sbus_writel(len, base->regs + base->dir + APCNC); 1835 out: 1836 spin_unlock_irqrestore(&base->lock, flags); 1837 return err; 1838 } 1839 1840 static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d) 1841 { 1842 unsigned long flags; 1843 u32 csr, test; 1844 struct sbus_dma_info *base = &dma_cont->sbus_info; 1845 1846 spin_lock_irqsave(&base->lock, flags); 1847 csr = sbus_readl(base->regs + APCCSR); 1848 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA | 1849 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL | 1850 APC_XINT_PENA; 1851 if ( base->dir == APC_RECORD ) 1852 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA | 1853 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL; 1854 csr |= test; 1855 sbus_writel(csr, base->regs + APCCSR); 1856 spin_unlock_irqrestore(&base->lock, flags); 1857 } 1858 1859 static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on) 1860 { 1861 unsigned long flags; 1862 u32 csr, shift; 1863 struct sbus_dma_info *base = &dma_cont->sbus_info; 1864 1865 spin_lock_irqsave(&base->lock, flags); 1866 if (!on) { 1867 if (base->dir == APC_PLAY) { 1868 sbus_writel(0, base->regs + base->dir + APCNVA); 1869 sbus_writel(1, base->regs + base->dir + APCC); 1870 } 1871 else 1872 { 1873 sbus_writel(0, base->regs + base->dir + APCNC); 1874 sbus_writel(0, base->regs + base->dir + APCVA); 1875 } 1876 } 1877 udelay(600); 1878 csr = sbus_readl(base->regs + APCCSR); 1879 shift = 0; 1880 if ( base->dir == APC_PLAY ) 1881 shift = 1; 1882 if (on) 1883 csr &= ~(APC_CPAUSE << shift); 1884 else 1885 csr |= (APC_CPAUSE << shift); 1886 sbus_writel(csr, base->regs + APCCSR); 1887 if (on) 1888 csr |= (APC_CDMA_READY << shift); 1889 else 1890 csr &= ~(APC_CDMA_READY << shift); 1891 sbus_writel(csr, base->regs + APCCSR); 1892 1893 spin_unlock_irqrestore(&base->lock, flags); 1894 } 1895 1896 static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont) 1897 { 1898 struct sbus_dma_info *base = &dma_cont->sbus_info; 1899 1900 return sbus_readl(base->regs + base->dir + APCVA); 1901 } 1902 1903 static void sbus_dma_reset(struct snd_cs4231 *chip) 1904 { 1905 sbus_writel(APC_CHIP_RESET, chip->port + APCCSR); 1906 sbus_writel(0x00, chip->port + APCCSR); 1907 sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET, 1908 chip->port + APCCSR); 1909 1910 udelay(20); 1911 1912 sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET, 1913 chip->port + APCCSR); 1914 sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA | 1915 APC_XINT_PENA | 1916 APC_XINT_CENA), 1917 chip->port + APCCSR); 1918 } 1919 1920 static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm) 1921 { 1922 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS, 1923 snd_dma_sbus_data(chip->dev_u.sdev), 1924 64*1024, 128*1024); 1925 } 1926 1927 /* 1928 * Init and exit routines 1929 */ 1930 1931 static int snd_cs4231_sbus_free(struct snd_cs4231 *chip) 1932 { 1933 if (chip->irq[0]) 1934 free_irq(chip->irq[0], chip); 1935 1936 if (chip->port) 1937 sbus_iounmap(chip->port, chip->regs_size); 1938 1939 kfree(chip); 1940 1941 return 0; 1942 } 1943 1944 static int snd_cs4231_sbus_dev_free(struct snd_device *device) 1945 { 1946 struct snd_cs4231 *cp = device->device_data; 1947 1948 return snd_cs4231_sbus_free(cp); 1949 } 1950 1951 static struct snd_device_ops snd_cs4231_sbus_dev_ops = { 1952 .dev_free = snd_cs4231_sbus_dev_free, 1953 }; 1954 1955 static int __init snd_cs4231_sbus_create(struct snd_card *card, 1956 struct sbus_dev *sdev, 1957 int dev, 1958 struct snd_cs4231 **rchip) 1959 { 1960 struct snd_cs4231 *chip; 1961 int err; 1962 1963 *rchip = NULL; 1964 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1965 if (chip == NULL) 1966 return -ENOMEM; 1967 1968 spin_lock_init(&chip->lock); 1969 spin_lock_init(&chip->c_dma.sbus_info.lock); 1970 spin_lock_init(&chip->p_dma.sbus_info.lock); 1971 init_MUTEX(&chip->mce_mutex); 1972 init_MUTEX(&chip->open_mutex); 1973 chip->card = card; 1974 chip->dev_u.sdev = sdev; 1975 chip->regs_size = sdev->reg_addrs[0].reg_size; 1976 memcpy(&chip->image, &snd_cs4231_original_image, 1977 sizeof(snd_cs4231_original_image)); 1978 1979 chip->port = sbus_ioremap(&sdev->resource[0], 0, 1980 chip->regs_size, "cs4231"); 1981 if (!chip->port) { 1982 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); 1983 return -EIO; 1984 } 1985 1986 chip->c_dma.sbus_info.regs = chip->port; 1987 chip->p_dma.sbus_info.regs = chip->port; 1988 chip->c_dma.sbus_info.dir = APC_RECORD; 1989 chip->p_dma.sbus_info.dir = APC_PLAY; 1990 1991 chip->p_dma.prepare = sbus_dma_prepare; 1992 chip->p_dma.enable = sbus_dma_enable; 1993 chip->p_dma.request = sbus_dma_request; 1994 chip->p_dma.address = sbus_dma_addr; 1995 chip->p_dma.reset = sbus_dma_reset; 1996 chip->p_dma.preallocate = sbus_dma_preallocate; 1997 1998 chip->c_dma.prepare = sbus_dma_prepare; 1999 chip->c_dma.enable = sbus_dma_enable; 2000 chip->c_dma.request = sbus_dma_request; 2001 chip->c_dma.address = sbus_dma_addr; 2002 chip->c_dma.reset = sbus_dma_reset; 2003 chip->c_dma.preallocate = sbus_dma_preallocate; 2004 2005 if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt, 2006 SA_SHIRQ, "cs4231", chip)) { 2007 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n", 2008 dev, 2009 __irq_itoa(sdev->irqs[0])); 2010 snd_cs4231_sbus_free(chip); 2011 return -EBUSY; 2012 } 2013 chip->irq[0] = sdev->irqs[0]; 2014 2015 if (snd_cs4231_probe(chip) < 0) { 2016 snd_cs4231_sbus_free(chip); 2017 return -ENODEV; 2018 } 2019 snd_cs4231_init(chip); 2020 2021 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, 2022 chip, &snd_cs4231_sbus_dev_ops)) < 0) { 2023 snd_cs4231_sbus_free(chip); 2024 return err; 2025 } 2026 2027 *rchip = chip; 2028 return 0; 2029 } 2030 2031 static int __init cs4231_sbus_attach(struct sbus_dev *sdev) 2032 { 2033 struct resource *rp = &sdev->resource[0]; 2034 struct snd_cs4231 *cp; 2035 struct snd_card *card; 2036 int err; 2037 2038 err = cs4231_attach_begin(&card); 2039 if (err) 2040 return err; 2041 2042 sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s", 2043 card->shortname, 2044 rp->flags & 0xffL, 2045 rp->start, 2046 __irq_itoa(sdev->irqs[0])); 2047 2048 if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) { 2049 snd_card_free(card); 2050 return err; 2051 } 2052 2053 return cs4231_attach_finish(card, cp); 2054 } 2055 #endif 2056 2057 #ifdef EBUS_SUPPORT 2058 2059 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie) 2060 { 2061 struct snd_cs4231 *chip = cookie; 2062 2063 snd_cs4231_play_callback(chip); 2064 } 2065 2066 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie) 2067 { 2068 struct snd_cs4231 *chip = cookie; 2069 2070 snd_cs4231_capture_callback(chip); 2071 } 2072 2073 /* 2074 * EBUS DMA wrappers 2075 */ 2076 2077 static int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len) 2078 { 2079 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len); 2080 } 2081 2082 static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on) 2083 { 2084 ebus_dma_enable(&dma_cont->ebus_info, on); 2085 } 2086 2087 static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir) 2088 { 2089 ebus_dma_prepare(&dma_cont->ebus_info, dir); 2090 } 2091 2092 static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont) 2093 { 2094 return ebus_dma_addr(&dma_cont->ebus_info); 2095 } 2096 2097 static void _ebus_dma_reset(struct snd_cs4231 *chip) 2098 { 2099 return; 2100 } 2101 2102 static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm) 2103 { 2104 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 2105 snd_dma_pci_data(chip->dev_u.pdev), 2106 64*1024, 128*1024); 2107 } 2108 2109 /* 2110 * Init and exit routines 2111 */ 2112 2113 static int snd_cs4231_ebus_free(struct snd_cs4231 *chip) 2114 { 2115 if (chip->c_dma.ebus_info.regs) { 2116 ebus_dma_unregister(&chip->c_dma.ebus_info); 2117 iounmap(chip->c_dma.ebus_info.regs); 2118 } 2119 if (chip->p_dma.ebus_info.regs) { 2120 ebus_dma_unregister(&chip->p_dma.ebus_info); 2121 iounmap(chip->p_dma.ebus_info.regs); 2122 } 2123 2124 if (chip->port) 2125 iounmap(chip->port); 2126 2127 kfree(chip); 2128 2129 return 0; 2130 } 2131 2132 static int snd_cs4231_ebus_dev_free(struct snd_device *device) 2133 { 2134 struct snd_cs4231 *cp = device->device_data; 2135 2136 return snd_cs4231_ebus_free(cp); 2137 } 2138 2139 static struct snd_device_ops snd_cs4231_ebus_dev_ops = { 2140 .dev_free = snd_cs4231_ebus_dev_free, 2141 }; 2142 2143 static int __init snd_cs4231_ebus_create(struct snd_card *card, 2144 struct linux_ebus_device *edev, 2145 int dev, 2146 struct snd_cs4231 **rchip) 2147 { 2148 struct snd_cs4231 *chip; 2149 int err; 2150 2151 *rchip = NULL; 2152 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2153 if (chip == NULL) 2154 return -ENOMEM; 2155 2156 spin_lock_init(&chip->lock); 2157 spin_lock_init(&chip->c_dma.ebus_info.lock); 2158 spin_lock_init(&chip->p_dma.ebus_info.lock); 2159 init_MUTEX(&chip->mce_mutex); 2160 init_MUTEX(&chip->open_mutex); 2161 chip->flags |= CS4231_FLAG_EBUS; 2162 chip->card = card; 2163 chip->dev_u.pdev = edev->bus->self; 2164 memcpy(&chip->image, &snd_cs4231_original_image, 2165 sizeof(snd_cs4231_original_image)); 2166 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)"); 2167 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; 2168 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback; 2169 chip->c_dma.ebus_info.client_cookie = chip; 2170 chip->c_dma.ebus_info.irq = edev->irqs[0]; 2171 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)"); 2172 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; 2173 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback; 2174 chip->p_dma.ebus_info.client_cookie = chip; 2175 chip->p_dma.ebus_info.irq = edev->irqs[1]; 2176 2177 chip->p_dma.prepare = _ebus_dma_prepare; 2178 chip->p_dma.enable = _ebus_dma_enable; 2179 chip->p_dma.request = _ebus_dma_request; 2180 chip->p_dma.address = _ebus_dma_addr; 2181 chip->p_dma.reset = _ebus_dma_reset; 2182 chip->p_dma.preallocate = _ebus_dma_preallocate; 2183 2184 chip->c_dma.prepare = _ebus_dma_prepare; 2185 chip->c_dma.enable = _ebus_dma_enable; 2186 chip->c_dma.request = _ebus_dma_request; 2187 chip->c_dma.address = _ebus_dma_addr; 2188 chip->c_dma.reset = _ebus_dma_reset; 2189 chip->c_dma.preallocate = _ebus_dma_preallocate; 2190 2191 chip->port = ioremap(edev->resource[0].start, 0x10); 2192 chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10); 2193 chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10); 2194 if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) { 2195 snd_cs4231_ebus_free(chip); 2196 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); 2197 return -EIO; 2198 } 2199 2200 if (ebus_dma_register(&chip->c_dma.ebus_info)) { 2201 snd_cs4231_ebus_free(chip); 2202 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev); 2203 return -EBUSY; 2204 } 2205 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) { 2206 snd_cs4231_ebus_free(chip); 2207 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev); 2208 return -EBUSY; 2209 } 2210 2211 if (ebus_dma_register(&chip->p_dma.ebus_info)) { 2212 snd_cs4231_ebus_free(chip); 2213 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev); 2214 return -EBUSY; 2215 } 2216 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) { 2217 snd_cs4231_ebus_free(chip); 2218 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev); 2219 return -EBUSY; 2220 } 2221 2222 if (snd_cs4231_probe(chip) < 0) { 2223 snd_cs4231_ebus_free(chip); 2224 return -ENODEV; 2225 } 2226 snd_cs4231_init(chip); 2227 2228 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, 2229 chip, &snd_cs4231_ebus_dev_ops)) < 0) { 2230 snd_cs4231_ebus_free(chip); 2231 return err; 2232 } 2233 2234 *rchip = chip; 2235 return 0; 2236 } 2237 2238 static int __init cs4231_ebus_attach(struct linux_ebus_device *edev) 2239 { 2240 struct snd_card *card; 2241 struct snd_cs4231 *chip; 2242 int err; 2243 2244 err = cs4231_attach_begin(&card); 2245 if (err) 2246 return err; 2247 2248 sprintf(card->longname, "%s at 0x%lx, irq %s", 2249 card->shortname, 2250 edev->resource[0].start, 2251 __irq_itoa(edev->irqs[0])); 2252 2253 if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) { 2254 snd_card_free(card); 2255 return err; 2256 } 2257 2258 return cs4231_attach_finish(card, chip); 2259 } 2260 #endif 2261 2262 static int __init cs4231_init(void) 2263 { 2264 #ifdef SBUS_SUPPORT 2265 struct sbus_bus *sbus; 2266 struct sbus_dev *sdev; 2267 #endif 2268 #ifdef EBUS_SUPPORT 2269 struct linux_ebus *ebus; 2270 struct linux_ebus_device *edev; 2271 #endif 2272 int found; 2273 2274 found = 0; 2275 2276 #ifdef SBUS_SUPPORT 2277 for_all_sbusdev(sdev, sbus) { 2278 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) { 2279 if (cs4231_sbus_attach(sdev) == 0) 2280 found++; 2281 } 2282 } 2283 #endif 2284 #ifdef EBUS_SUPPORT 2285 for_each_ebus(ebus) { 2286 for_each_ebusdev(edev, ebus) { 2287 int match = 0; 2288 2289 if (!strcmp(edev->prom_name, "SUNW,CS4231")) { 2290 match = 1; 2291 } else if (!strcmp(edev->prom_name, "audio")) { 2292 char compat[16]; 2293 2294 prom_getstring(edev->prom_node, "compatible", 2295 compat, sizeof(compat)); 2296 compat[15] = '\0'; 2297 if (!strcmp(compat, "SUNW,CS4231")) 2298 match = 1; 2299 } 2300 2301 if (match && 2302 cs4231_ebus_attach(edev) == 0) 2303 found++; 2304 } 2305 } 2306 #endif 2307 2308 2309 return (found > 0) ? 0 : -EIO; 2310 } 2311 2312 static void __exit cs4231_exit(void) 2313 { 2314 struct snd_cs4231 *p = cs4231_list; 2315 2316 while (p != NULL) { 2317 struct snd_cs4231 *next = p->next; 2318 2319 snd_card_free(p->card); 2320 2321 p = next; 2322 } 2323 2324 cs4231_list = NULL; 2325 } 2326 2327 module_init(cs4231_init); 2328 module_exit(cs4231_exit); 2329