1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for CS4231 sound chips found on Sparcs. 4 * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net> 5 * 6 * Based entirely upon drivers/sbus/audio/cs4231.c which is: 7 * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu) 8 * and also sound/isa/cs423x/cs4231_lib.c which is: 9 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/delay.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/moduleparam.h> 18 #include <linux/irq.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/info.h> 26 #include <sound/control.h> 27 #include <sound/timer.h> 28 #include <sound/initval.h> 29 #include <sound/pcm_params.h> 30 31 #ifdef CONFIG_SBUS 32 #define SBUS_SUPPORT 33 #endif 34 35 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64) 36 #define EBUS_SUPPORT 37 #include <linux/pci.h> 38 #include <asm/ebus_dma.h> 39 #endif 40 41 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 42 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 43 /* Enable this card */ 44 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 45 46 module_param_array(index, int, NULL, 0444); 47 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard."); 48 module_param_array(id, charp, NULL, 0444); 49 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard."); 50 module_param_array(enable, bool, NULL, 0444); 51 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard."); 52 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller"); 53 MODULE_DESCRIPTION("Sun CS4231"); 54 MODULE_LICENSE("GPL"); 55 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}"); 56 57 #ifdef SBUS_SUPPORT 58 struct sbus_dma_info { 59 spinlock_t lock; /* DMA access lock */ 60 int dir; 61 void __iomem *regs; 62 }; 63 #endif 64 65 struct snd_cs4231; 66 struct cs4231_dma_control { 67 void (*prepare)(struct cs4231_dma_control *dma_cont, 68 int dir); 69 void (*enable)(struct cs4231_dma_control *dma_cont, int on); 70 int (*request)(struct cs4231_dma_control *dma_cont, 71 dma_addr_t bus_addr, size_t len); 72 unsigned int (*address)(struct cs4231_dma_control *dma_cont); 73 #ifdef EBUS_SUPPORT 74 struct ebus_dma_info ebus_info; 75 #endif 76 #ifdef SBUS_SUPPORT 77 struct sbus_dma_info sbus_info; 78 #endif 79 }; 80 81 struct snd_cs4231 { 82 spinlock_t lock; /* registers access lock */ 83 void __iomem *port; 84 85 struct cs4231_dma_control p_dma; 86 struct cs4231_dma_control c_dma; 87 88 u32 flags; 89 #define CS4231_FLAG_EBUS 0x00000001 90 #define CS4231_FLAG_PLAYBACK 0x00000002 91 #define CS4231_FLAG_CAPTURE 0x00000004 92 93 struct snd_card *card; 94 struct snd_pcm *pcm; 95 struct snd_pcm_substream *playback_substream; 96 unsigned int p_periods_sent; 97 struct snd_pcm_substream *capture_substream; 98 unsigned int c_periods_sent; 99 struct snd_timer *timer; 100 101 unsigned short mode; 102 #define CS4231_MODE_NONE 0x0000 103 #define CS4231_MODE_PLAY 0x0001 104 #define CS4231_MODE_RECORD 0x0002 105 #define CS4231_MODE_TIMER 0x0004 106 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \ 107 CS4231_MODE_TIMER) 108 109 unsigned char image[32]; /* registers image */ 110 int mce_bit; 111 int calibrate_mute; 112 struct mutex mce_mutex; /* mutex for mce register */ 113 struct mutex open_mutex; /* mutex for ALSA open/close */ 114 115 struct platform_device *op; 116 unsigned int irq[2]; 117 unsigned int regs_size; 118 struct snd_cs4231 *next; 119 }; 120 121 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for 122 * now.... -DaveM 123 */ 124 125 /* IO ports */ 126 #include <sound/cs4231-regs.h> 127 128 /* XXX offsets are different than PC ISA chips... */ 129 #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2)) 130 131 /* SBUS DMA register defines. */ 132 133 #define APCCSR 0x10UL /* APC DMA CSR */ 134 #define APCCVA 0x20UL /* APC Capture DMA Address */ 135 #define APCCC 0x24UL /* APC Capture Count */ 136 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */ 137 #define APCCNC 0x2cUL /* APC Capture Next Count */ 138 #define APCPVA 0x30UL /* APC Play DMA Address */ 139 #define APCPC 0x34UL /* APC Play Count */ 140 #define APCPNVA 0x38UL /* APC Play DMA Next Address */ 141 #define APCPNC 0x3cUL /* APC Play Next Count */ 142 143 /* Defines for SBUS DMA-routines */ 144 145 #define APCVA 0x0UL /* APC DMA Address */ 146 #define APCC 0x4UL /* APC Count */ 147 #define APCNVA 0x8UL /* APC DMA Next Address */ 148 #define APCNC 0xcUL /* APC Next Count */ 149 #define APC_PLAY 0x30UL /* Play registers start at 0x30 */ 150 #define APC_RECORD 0x20UL /* Record registers start at 0x20 */ 151 152 /* APCCSR bits */ 153 154 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */ 155 #define APC_PLAY_INT 0x400000 /* Playback interrupt */ 156 #define APC_CAPT_INT 0x200000 /* Capture interrupt */ 157 #define APC_GENL_INT 0x100000 /* General interrupt */ 158 #define APC_XINT_ENA 0x80000 /* General ext int. enable */ 159 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */ 160 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */ 161 #define APC_XINT_GENL 0x10000 /* Error ext intr */ 162 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */ 163 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */ 164 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */ 165 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */ 166 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */ 167 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */ 168 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */ 169 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */ 170 #define APC_PPAUSE 0x80 /* Pause the play DMA */ 171 #define APC_CPAUSE 0x40 /* Pause the capture DMA */ 172 #define APC_CDC_RESET 0x20 /* CODEC RESET */ 173 #define APC_PDMA_READY 0x08 /* Play DMA Go */ 174 #define APC_CDMA_READY 0x04 /* Capture DMA Go */ 175 #define APC_CHIP_RESET 0x01 /* Reset the chip */ 176 177 /* EBUS DMA register offsets */ 178 179 #define EBDMA_CSR 0x00UL /* Control/Status */ 180 #define EBDMA_ADDR 0x04UL /* DMA Address */ 181 #define EBDMA_COUNT 0x08UL /* DMA Count */ 182 183 /* 184 * Some variables 185 */ 186 187 static const unsigned char freq_bits[14] = { 188 /* 5510 */ 0x00 | CS4231_XTAL2, 189 /* 6620 */ 0x0E | CS4231_XTAL2, 190 /* 8000 */ 0x00 | CS4231_XTAL1, 191 /* 9600 */ 0x0E | CS4231_XTAL1, 192 /* 11025 */ 0x02 | CS4231_XTAL2, 193 /* 16000 */ 0x02 | CS4231_XTAL1, 194 /* 18900 */ 0x04 | CS4231_XTAL2, 195 /* 22050 */ 0x06 | CS4231_XTAL2, 196 /* 27042 */ 0x04 | CS4231_XTAL1, 197 /* 32000 */ 0x06 | CS4231_XTAL1, 198 /* 33075 */ 0x0C | CS4231_XTAL2, 199 /* 37800 */ 0x08 | CS4231_XTAL2, 200 /* 44100 */ 0x0A | CS4231_XTAL2, 201 /* 48000 */ 0x0C | CS4231_XTAL1 202 }; 203 204 static const unsigned int rates[14] = { 205 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050, 206 27042, 32000, 33075, 37800, 44100, 48000 207 }; 208 209 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { 210 .count = ARRAY_SIZE(rates), 211 .list = rates, 212 }; 213 214 static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime) 215 { 216 return snd_pcm_hw_constraint_list(runtime, 0, 217 SNDRV_PCM_HW_PARAM_RATE, 218 &hw_constraints_rates); 219 } 220 221 static const unsigned char snd_cs4231_original_image[32] = 222 { 223 0x00, /* 00/00 - lic */ 224 0x00, /* 01/01 - ric */ 225 0x9f, /* 02/02 - la1ic */ 226 0x9f, /* 03/03 - ra1ic */ 227 0x9f, /* 04/04 - la2ic */ 228 0x9f, /* 05/05 - ra2ic */ 229 0xbf, /* 06/06 - loc */ 230 0xbf, /* 07/07 - roc */ 231 0x20, /* 08/08 - pdfr */ 232 CS4231_AUTOCALIB, /* 09/09 - ic */ 233 0x00, /* 0a/10 - pc */ 234 0x00, /* 0b/11 - ti */ 235 CS4231_MODE2, /* 0c/12 - mi */ 236 0x00, /* 0d/13 - lbc */ 237 0x00, /* 0e/14 - pbru */ 238 0x00, /* 0f/15 - pbrl */ 239 0x80, /* 10/16 - afei */ 240 0x01, /* 11/17 - afeii */ 241 0x9f, /* 12/18 - llic */ 242 0x9f, /* 13/19 - rlic */ 243 0x00, /* 14/20 - tlb */ 244 0x00, /* 15/21 - thb */ 245 0x00, /* 16/22 - la3mic/reserved */ 246 0x00, /* 17/23 - ra3mic/reserved */ 247 0x00, /* 18/24 - afs */ 248 0x00, /* 19/25 - lamoc/version */ 249 0x00, /* 1a/26 - mioc */ 250 0x00, /* 1b/27 - ramoc/reserved */ 251 0x20, /* 1c/28 - cdfr */ 252 0x00, /* 1d/29 - res4 */ 253 0x00, /* 1e/30 - cbru */ 254 0x00, /* 1f/31 - cbrl */ 255 }; 256 257 static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr) 258 { 259 if (cp->flags & CS4231_FLAG_EBUS) 260 return readb(reg_addr); 261 else 262 return sbus_readb(reg_addr); 263 } 264 265 static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, 266 void __iomem *reg_addr) 267 { 268 if (cp->flags & CS4231_FLAG_EBUS) 269 return writeb(val, reg_addr); 270 else 271 return sbus_writeb(val, reg_addr); 272 } 273 274 /* 275 * Basic I/O functions 276 */ 277 278 static void snd_cs4231_ready(struct snd_cs4231 *chip) 279 { 280 int timeout; 281 282 for (timeout = 250; timeout > 0; timeout--) { 283 int val = __cs4231_readb(chip, CS4231U(chip, REGSEL)); 284 if ((val & CS4231_INIT) == 0) 285 break; 286 udelay(100); 287 } 288 } 289 290 static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, 291 unsigned char value) 292 { 293 snd_cs4231_ready(chip); 294 #ifdef CONFIG_SND_DEBUG 295 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT) 296 snd_printdd("out: auto calibration time out - reg = 0x%x, " 297 "value = 0x%x\n", 298 reg, value); 299 #endif 300 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL)); 301 wmb(); 302 __cs4231_writeb(chip, value, CS4231U(chip, REG)); 303 mb(); 304 } 305 306 static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg, 307 unsigned char mask, unsigned char value) 308 { 309 unsigned char tmp = (chip->image[reg] & mask) | value; 310 311 chip->image[reg] = tmp; 312 if (!chip->calibrate_mute) 313 snd_cs4231_dout(chip, reg, tmp); 314 } 315 316 static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, 317 unsigned char value) 318 { 319 snd_cs4231_dout(chip, reg, value); 320 chip->image[reg] = value; 321 mb(); 322 } 323 324 static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg) 325 { 326 snd_cs4231_ready(chip); 327 #ifdef CONFIG_SND_DEBUG 328 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT) 329 snd_printdd("in: auto calibration time out - reg = 0x%x\n", 330 reg); 331 #endif 332 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL)); 333 mb(); 334 return __cs4231_readb(chip, CS4231U(chip, REG)); 335 } 336 337 /* 338 * CS4231 detection / MCE routines 339 */ 340 341 static void snd_cs4231_busy_wait(struct snd_cs4231 *chip) 342 { 343 int timeout; 344 345 /* looks like this sequence is proper for CS4231A chip (GUS MAX) */ 346 for (timeout = 5; timeout > 0; timeout--) 347 __cs4231_readb(chip, CS4231U(chip, REGSEL)); 348 349 /* end of cleanup sequence */ 350 for (timeout = 500; timeout > 0; timeout--) { 351 int val = __cs4231_readb(chip, CS4231U(chip, REGSEL)); 352 if ((val & CS4231_INIT) == 0) 353 break; 354 msleep(1); 355 } 356 } 357 358 static void snd_cs4231_mce_up(struct snd_cs4231 *chip) 359 { 360 unsigned long flags; 361 int timeout; 362 363 spin_lock_irqsave(&chip->lock, flags); 364 snd_cs4231_ready(chip); 365 #ifdef CONFIG_SND_DEBUG 366 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT) 367 snd_printdd("mce_up - auto calibration time out (0)\n"); 368 #endif 369 chip->mce_bit |= CS4231_MCE; 370 timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL)); 371 if (timeout == 0x80) 372 snd_printdd("mce_up [%p]: serious init problem - " 373 "codec still busy\n", 374 chip->port); 375 if (!(timeout & CS4231_MCE)) 376 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), 377 CS4231U(chip, REGSEL)); 378 spin_unlock_irqrestore(&chip->lock, flags); 379 } 380 381 static void snd_cs4231_mce_down(struct snd_cs4231 *chip) 382 { 383 unsigned long flags, timeout; 384 int reg; 385 386 snd_cs4231_busy_wait(chip); 387 spin_lock_irqsave(&chip->lock, flags); 388 #ifdef CONFIG_SND_DEBUG 389 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT) 390 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", 391 CS4231U(chip, REGSEL)); 392 #endif 393 chip->mce_bit &= ~CS4231_MCE; 394 reg = __cs4231_readb(chip, CS4231U(chip, REGSEL)); 395 __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f), 396 CS4231U(chip, REGSEL)); 397 if (reg == 0x80) 398 snd_printdd("mce_down [%p]: serious init problem " 399 "- codec still busy\n", chip->port); 400 if ((reg & CS4231_MCE) == 0) { 401 spin_unlock_irqrestore(&chip->lock, flags); 402 return; 403 } 404 405 /* 406 * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low. 407 */ 408 timeout = jiffies + msecs_to_jiffies(250); 409 do { 410 spin_unlock_irqrestore(&chip->lock, flags); 411 msleep(1); 412 spin_lock_irqsave(&chip->lock, flags); 413 reg = snd_cs4231_in(chip, CS4231_TEST_INIT); 414 reg &= CS4231_CALIB_IN_PROGRESS; 415 } while (reg && time_before(jiffies, timeout)); 416 spin_unlock_irqrestore(&chip->lock, flags); 417 418 if (reg) 419 snd_printk(KERN_ERR 420 "mce_down - auto calibration time out (2)\n"); 421 } 422 423 static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont, 424 struct snd_pcm_substream *substream, 425 unsigned int *periods_sent) 426 { 427 struct snd_pcm_runtime *runtime = substream->runtime; 428 429 while (1) { 430 unsigned int period_size = snd_pcm_lib_period_bytes(substream); 431 unsigned int offset = period_size * (*periods_sent); 432 433 if (WARN_ON(period_size >= (1 << 24))) 434 return; 435 436 if (dma_cont->request(dma_cont, 437 runtime->dma_addr + offset, period_size)) 438 return; 439 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods; 440 } 441 } 442 443 static void cs4231_dma_trigger(struct snd_pcm_substream *substream, 444 unsigned int what, int on) 445 { 446 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 447 struct cs4231_dma_control *dma_cont; 448 449 if (what & CS4231_PLAYBACK_ENABLE) { 450 dma_cont = &chip->p_dma; 451 if (on) { 452 dma_cont->prepare(dma_cont, 0); 453 dma_cont->enable(dma_cont, 1); 454 snd_cs4231_advance_dma(dma_cont, 455 chip->playback_substream, 456 &chip->p_periods_sent); 457 } else { 458 dma_cont->enable(dma_cont, 0); 459 } 460 } 461 if (what & CS4231_RECORD_ENABLE) { 462 dma_cont = &chip->c_dma; 463 if (on) { 464 dma_cont->prepare(dma_cont, 1); 465 dma_cont->enable(dma_cont, 1); 466 snd_cs4231_advance_dma(dma_cont, 467 chip->capture_substream, 468 &chip->c_periods_sent); 469 } else { 470 dma_cont->enable(dma_cont, 0); 471 } 472 } 473 } 474 475 static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd) 476 { 477 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 478 int result = 0; 479 480 switch (cmd) { 481 case SNDRV_PCM_TRIGGER_START: 482 case SNDRV_PCM_TRIGGER_STOP: 483 { 484 unsigned int what = 0; 485 struct snd_pcm_substream *s; 486 unsigned long flags; 487 488 snd_pcm_group_for_each_entry(s, substream) { 489 if (s == chip->playback_substream) { 490 what |= CS4231_PLAYBACK_ENABLE; 491 snd_pcm_trigger_done(s, substream); 492 } else if (s == chip->capture_substream) { 493 what |= CS4231_RECORD_ENABLE; 494 snd_pcm_trigger_done(s, substream); 495 } 496 } 497 498 spin_lock_irqsave(&chip->lock, flags); 499 if (cmd == SNDRV_PCM_TRIGGER_START) { 500 cs4231_dma_trigger(substream, what, 1); 501 chip->image[CS4231_IFACE_CTRL] |= what; 502 } else { 503 cs4231_dma_trigger(substream, what, 0); 504 chip->image[CS4231_IFACE_CTRL] &= ~what; 505 } 506 snd_cs4231_out(chip, CS4231_IFACE_CTRL, 507 chip->image[CS4231_IFACE_CTRL]); 508 spin_unlock_irqrestore(&chip->lock, flags); 509 break; 510 } 511 default: 512 result = -EINVAL; 513 break; 514 } 515 516 return result; 517 } 518 519 /* 520 * CODEC I/O 521 */ 522 523 static unsigned char snd_cs4231_get_rate(unsigned int rate) 524 { 525 int i; 526 527 for (i = 0; i < 14; i++) 528 if (rate == rates[i]) 529 return freq_bits[i]; 530 531 return freq_bits[13]; 532 } 533 534 static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format, 535 int channels) 536 { 537 unsigned char rformat; 538 539 rformat = CS4231_LINEAR_8; 540 switch (format) { 541 case SNDRV_PCM_FORMAT_MU_LAW: 542 rformat = CS4231_ULAW_8; 543 break; 544 case SNDRV_PCM_FORMAT_A_LAW: 545 rformat = CS4231_ALAW_8; 546 break; 547 case SNDRV_PCM_FORMAT_S16_LE: 548 rformat = CS4231_LINEAR_16; 549 break; 550 case SNDRV_PCM_FORMAT_S16_BE: 551 rformat = CS4231_LINEAR_16_BIG; 552 break; 553 case SNDRV_PCM_FORMAT_IMA_ADPCM: 554 rformat = CS4231_ADPCM_16; 555 break; 556 } 557 if (channels > 1) 558 rformat |= CS4231_STEREO; 559 return rformat; 560 } 561 562 static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute) 563 { 564 unsigned long flags; 565 566 mute = mute ? 1 : 0; 567 spin_lock_irqsave(&chip->lock, flags); 568 if (chip->calibrate_mute == mute) { 569 spin_unlock_irqrestore(&chip->lock, flags); 570 return; 571 } 572 if (!mute) { 573 snd_cs4231_dout(chip, CS4231_LEFT_INPUT, 574 chip->image[CS4231_LEFT_INPUT]); 575 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, 576 chip->image[CS4231_RIGHT_INPUT]); 577 snd_cs4231_dout(chip, CS4231_LOOPBACK, 578 chip->image[CS4231_LOOPBACK]); 579 } 580 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, 581 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]); 582 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, 583 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]); 584 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, 585 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]); 586 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, 587 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]); 588 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, 589 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]); 590 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, 591 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]); 592 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, 593 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]); 594 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, 595 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]); 596 snd_cs4231_dout(chip, CS4231_MONO_CTRL, 597 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]); 598 chip->calibrate_mute = mute; 599 spin_unlock_irqrestore(&chip->lock, flags); 600 } 601 602 static void snd_cs4231_playback_format(struct snd_cs4231 *chip, 603 struct snd_pcm_hw_params *params, 604 unsigned char pdfr) 605 { 606 unsigned long flags; 607 608 mutex_lock(&chip->mce_mutex); 609 snd_cs4231_calibrate_mute(chip, 1); 610 611 snd_cs4231_mce_up(chip); 612 613 spin_lock_irqsave(&chip->lock, flags); 614 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 615 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ? 616 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) : 617 pdfr); 618 spin_unlock_irqrestore(&chip->lock, flags); 619 620 snd_cs4231_mce_down(chip); 621 622 snd_cs4231_calibrate_mute(chip, 0); 623 mutex_unlock(&chip->mce_mutex); 624 } 625 626 static void snd_cs4231_capture_format(struct snd_cs4231 *chip, 627 struct snd_pcm_hw_params *params, 628 unsigned char cdfr) 629 { 630 unsigned long flags; 631 632 mutex_lock(&chip->mce_mutex); 633 snd_cs4231_calibrate_mute(chip, 1); 634 635 snd_cs4231_mce_up(chip); 636 637 spin_lock_irqsave(&chip->lock, flags); 638 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) { 639 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 640 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) | 641 (cdfr & 0x0f)); 642 spin_unlock_irqrestore(&chip->lock, flags); 643 snd_cs4231_mce_down(chip); 644 snd_cs4231_mce_up(chip); 645 spin_lock_irqsave(&chip->lock, flags); 646 } 647 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr); 648 spin_unlock_irqrestore(&chip->lock, flags); 649 650 snd_cs4231_mce_down(chip); 651 652 snd_cs4231_calibrate_mute(chip, 0); 653 mutex_unlock(&chip->mce_mutex); 654 } 655 656 /* 657 * Timer interface 658 */ 659 660 static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer) 661 { 662 struct snd_cs4231 *chip = snd_timer_chip(timer); 663 664 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920; 665 } 666 667 static int snd_cs4231_timer_start(struct snd_timer *timer) 668 { 669 unsigned long flags; 670 unsigned int ticks; 671 struct snd_cs4231 *chip = snd_timer_chip(timer); 672 673 spin_lock_irqsave(&chip->lock, flags); 674 ticks = timer->sticks; 675 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 || 676 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] || 677 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) { 678 snd_cs4231_out(chip, CS4231_TIMER_HIGH, 679 chip->image[CS4231_TIMER_HIGH] = 680 (unsigned char) (ticks >> 8)); 681 snd_cs4231_out(chip, CS4231_TIMER_LOW, 682 chip->image[CS4231_TIMER_LOW] = 683 (unsigned char) ticks); 684 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 685 chip->image[CS4231_ALT_FEATURE_1] | 686 CS4231_TIMER_ENABLE); 687 } 688 spin_unlock_irqrestore(&chip->lock, flags); 689 690 return 0; 691 } 692 693 static int snd_cs4231_timer_stop(struct snd_timer *timer) 694 { 695 unsigned long flags; 696 struct snd_cs4231 *chip = snd_timer_chip(timer); 697 698 spin_lock_irqsave(&chip->lock, flags); 699 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE; 700 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 701 chip->image[CS4231_ALT_FEATURE_1]); 702 spin_unlock_irqrestore(&chip->lock, flags); 703 704 return 0; 705 } 706 707 static void snd_cs4231_init(struct snd_cs4231 *chip) 708 { 709 unsigned long flags; 710 711 snd_cs4231_mce_down(chip); 712 713 #ifdef SNDRV_DEBUG_MCE 714 snd_printdd("init: (1)\n"); 715 #endif 716 snd_cs4231_mce_up(chip); 717 spin_lock_irqsave(&chip->lock, flags); 718 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | 719 CS4231_PLAYBACK_PIO | 720 CS4231_RECORD_ENABLE | 721 CS4231_RECORD_PIO | 722 CS4231_CALIB_MODE); 723 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB; 724 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 725 spin_unlock_irqrestore(&chip->lock, flags); 726 snd_cs4231_mce_down(chip); 727 728 #ifdef SNDRV_DEBUG_MCE 729 snd_printdd("init: (2)\n"); 730 #endif 731 732 snd_cs4231_mce_up(chip); 733 spin_lock_irqsave(&chip->lock, flags); 734 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 735 chip->image[CS4231_ALT_FEATURE_1]); 736 spin_unlock_irqrestore(&chip->lock, flags); 737 snd_cs4231_mce_down(chip); 738 739 #ifdef SNDRV_DEBUG_MCE 740 snd_printdd("init: (3) - afei = 0x%x\n", 741 chip->image[CS4231_ALT_FEATURE_1]); 742 #endif 743 744 spin_lock_irqsave(&chip->lock, flags); 745 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, 746 chip->image[CS4231_ALT_FEATURE_2]); 747 spin_unlock_irqrestore(&chip->lock, flags); 748 749 snd_cs4231_mce_up(chip); 750 spin_lock_irqsave(&chip->lock, flags); 751 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 752 chip->image[CS4231_PLAYBK_FORMAT]); 753 spin_unlock_irqrestore(&chip->lock, flags); 754 snd_cs4231_mce_down(chip); 755 756 #ifdef SNDRV_DEBUG_MCE 757 snd_printdd("init: (4)\n"); 758 #endif 759 760 snd_cs4231_mce_up(chip); 761 spin_lock_irqsave(&chip->lock, flags); 762 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]); 763 spin_unlock_irqrestore(&chip->lock, flags); 764 snd_cs4231_mce_down(chip); 765 766 #ifdef SNDRV_DEBUG_MCE 767 snd_printdd("init: (5)\n"); 768 #endif 769 } 770 771 static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode) 772 { 773 unsigned long flags; 774 775 mutex_lock(&chip->open_mutex); 776 if ((chip->mode & mode)) { 777 mutex_unlock(&chip->open_mutex); 778 return -EAGAIN; 779 } 780 if (chip->mode & CS4231_MODE_OPEN) { 781 chip->mode |= mode; 782 mutex_unlock(&chip->open_mutex); 783 return 0; 784 } 785 /* ok. now enable and ack CODEC IRQ */ 786 spin_lock_irqsave(&chip->lock, flags); 787 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 788 CS4231_RECORD_IRQ | 789 CS4231_TIMER_IRQ); 790 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 791 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */ 792 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */ 793 794 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 795 CS4231_RECORD_IRQ | 796 CS4231_TIMER_IRQ); 797 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 798 799 spin_unlock_irqrestore(&chip->lock, flags); 800 801 chip->mode = mode; 802 mutex_unlock(&chip->open_mutex); 803 return 0; 804 } 805 806 static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode) 807 { 808 unsigned long flags; 809 810 mutex_lock(&chip->open_mutex); 811 chip->mode &= ~mode; 812 if (chip->mode & CS4231_MODE_OPEN) { 813 mutex_unlock(&chip->open_mutex); 814 return; 815 } 816 snd_cs4231_calibrate_mute(chip, 1); 817 818 /* disable IRQ */ 819 spin_lock_irqsave(&chip->lock, flags); 820 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 821 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */ 822 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */ 823 824 /* now disable record & playback */ 825 826 if (chip->image[CS4231_IFACE_CTRL] & 827 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 828 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) { 829 spin_unlock_irqrestore(&chip->lock, flags); 830 snd_cs4231_mce_up(chip); 831 spin_lock_irqsave(&chip->lock, flags); 832 chip->image[CS4231_IFACE_CTRL] &= 833 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 834 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO); 835 snd_cs4231_out(chip, CS4231_IFACE_CTRL, 836 chip->image[CS4231_IFACE_CTRL]); 837 spin_unlock_irqrestore(&chip->lock, flags); 838 snd_cs4231_mce_down(chip); 839 spin_lock_irqsave(&chip->lock, flags); 840 } 841 842 /* clear IRQ again */ 843 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 844 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */ 845 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */ 846 spin_unlock_irqrestore(&chip->lock, flags); 847 848 snd_cs4231_calibrate_mute(chip, 0); 849 850 chip->mode = 0; 851 mutex_unlock(&chip->open_mutex); 852 } 853 854 /* 855 * timer open/close 856 */ 857 858 static int snd_cs4231_timer_open(struct snd_timer *timer) 859 { 860 struct snd_cs4231 *chip = snd_timer_chip(timer); 861 snd_cs4231_open(chip, CS4231_MODE_TIMER); 862 return 0; 863 } 864 865 static int snd_cs4231_timer_close(struct snd_timer *timer) 866 { 867 struct snd_cs4231 *chip = snd_timer_chip(timer); 868 snd_cs4231_close(chip, CS4231_MODE_TIMER); 869 return 0; 870 } 871 872 static const struct snd_timer_hardware snd_cs4231_timer_table = { 873 .flags = SNDRV_TIMER_HW_AUTO, 874 .resolution = 9945, 875 .ticks = 65535, 876 .open = snd_cs4231_timer_open, 877 .close = snd_cs4231_timer_close, 878 .c_resolution = snd_cs4231_timer_resolution, 879 .start = snd_cs4231_timer_start, 880 .stop = snd_cs4231_timer_stop, 881 }; 882 883 /* 884 * ok.. exported functions.. 885 */ 886 887 static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream, 888 struct snd_pcm_hw_params *hw_params) 889 { 890 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 891 unsigned char new_pdfr; 892 893 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), 894 params_channels(hw_params)) | 895 snd_cs4231_get_rate(params_rate(hw_params)); 896 snd_cs4231_playback_format(chip, hw_params, new_pdfr); 897 898 return 0; 899 } 900 901 static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream) 902 { 903 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 904 struct snd_pcm_runtime *runtime = substream->runtime; 905 unsigned long flags; 906 int ret = 0; 907 908 spin_lock_irqsave(&chip->lock, flags); 909 910 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | 911 CS4231_PLAYBACK_PIO); 912 913 if (WARN_ON(runtime->period_size > 0xffff + 1)) { 914 ret = -EINVAL; 915 goto out; 916 } 917 918 chip->p_periods_sent = 0; 919 920 out: 921 spin_unlock_irqrestore(&chip->lock, flags); 922 923 return ret; 924 } 925 926 static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream, 927 struct snd_pcm_hw_params *hw_params) 928 { 929 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 930 unsigned char new_cdfr; 931 932 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), 933 params_channels(hw_params)) | 934 snd_cs4231_get_rate(params_rate(hw_params)); 935 snd_cs4231_capture_format(chip, hw_params, new_cdfr); 936 937 return 0; 938 } 939 940 static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream) 941 { 942 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 943 unsigned long flags; 944 945 spin_lock_irqsave(&chip->lock, flags); 946 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | 947 CS4231_RECORD_PIO); 948 949 950 chip->c_periods_sent = 0; 951 spin_unlock_irqrestore(&chip->lock, flags); 952 953 return 0; 954 } 955 956 static void snd_cs4231_overrange(struct snd_cs4231 *chip) 957 { 958 unsigned long flags; 959 unsigned char res; 960 961 spin_lock_irqsave(&chip->lock, flags); 962 res = snd_cs4231_in(chip, CS4231_TEST_INIT); 963 spin_unlock_irqrestore(&chip->lock, flags); 964 965 /* detect overrange only above 0dB; may be user selectable? */ 966 if (res & (0x08 | 0x02)) 967 chip->capture_substream->runtime->overrange++; 968 } 969 970 static void snd_cs4231_play_callback(struct snd_cs4231 *chip) 971 { 972 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) { 973 snd_pcm_period_elapsed(chip->playback_substream); 974 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream, 975 &chip->p_periods_sent); 976 } 977 } 978 979 static void snd_cs4231_capture_callback(struct snd_cs4231 *chip) 980 { 981 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) { 982 snd_pcm_period_elapsed(chip->capture_substream); 983 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream, 984 &chip->c_periods_sent); 985 } 986 } 987 988 static snd_pcm_uframes_t snd_cs4231_playback_pointer( 989 struct snd_pcm_substream *substream) 990 { 991 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 992 struct cs4231_dma_control *dma_cont = &chip->p_dma; 993 size_t ptr; 994 995 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) 996 return 0; 997 ptr = dma_cont->address(dma_cont); 998 if (ptr != 0) 999 ptr -= substream->runtime->dma_addr; 1000 1001 return bytes_to_frames(substream->runtime, ptr); 1002 } 1003 1004 static snd_pcm_uframes_t snd_cs4231_capture_pointer( 1005 struct snd_pcm_substream *substream) 1006 { 1007 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1008 struct cs4231_dma_control *dma_cont = &chip->c_dma; 1009 size_t ptr; 1010 1011 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)) 1012 return 0; 1013 ptr = dma_cont->address(dma_cont); 1014 if (ptr != 0) 1015 ptr -= substream->runtime->dma_addr; 1016 1017 return bytes_to_frames(substream->runtime, ptr); 1018 } 1019 1020 static int snd_cs4231_probe(struct snd_cs4231 *chip) 1021 { 1022 unsigned long flags; 1023 int i; 1024 int id = 0; 1025 int vers = 0; 1026 unsigned char *ptr; 1027 1028 for (i = 0; i < 50; i++) { 1029 mb(); 1030 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT) 1031 msleep(2); 1032 else { 1033 spin_lock_irqsave(&chip->lock, flags); 1034 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2); 1035 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f; 1036 vers = snd_cs4231_in(chip, CS4231_VERSION); 1037 spin_unlock_irqrestore(&chip->lock, flags); 1038 if (id == 0x0a) 1039 break; /* this is valid value */ 1040 } 1041 } 1042 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id); 1043 if (id != 0x0a) 1044 return -ENODEV; /* no valid device found */ 1045 1046 spin_lock_irqsave(&chip->lock, flags); 1047 1048 /* clear any pendings IRQ */ 1049 __cs4231_readb(chip, CS4231U(chip, STATUS)); 1050 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); 1051 mb(); 1052 1053 spin_unlock_irqrestore(&chip->lock, flags); 1054 1055 chip->image[CS4231_MISC_INFO] = CS4231_MODE2; 1056 chip->image[CS4231_IFACE_CTRL] = 1057 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA; 1058 chip->image[CS4231_ALT_FEATURE_1] = 0x80; 1059 chip->image[CS4231_ALT_FEATURE_2] = 0x01; 1060 if (vers & 0x20) 1061 chip->image[CS4231_ALT_FEATURE_2] |= 0x02; 1062 1063 ptr = (unsigned char *) &chip->image; 1064 1065 snd_cs4231_mce_down(chip); 1066 1067 spin_lock_irqsave(&chip->lock, flags); 1068 1069 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */ 1070 snd_cs4231_out(chip, i, *ptr++); 1071 1072 spin_unlock_irqrestore(&chip->lock, flags); 1073 1074 snd_cs4231_mce_up(chip); 1075 1076 snd_cs4231_mce_down(chip); 1077 1078 mdelay(2); 1079 1080 return 0; /* all things are ok.. */ 1081 } 1082 1083 static const struct snd_pcm_hardware snd_cs4231_playback = { 1084 .info = SNDRV_PCM_INFO_MMAP | 1085 SNDRV_PCM_INFO_INTERLEAVED | 1086 SNDRV_PCM_INFO_MMAP_VALID | 1087 SNDRV_PCM_INFO_SYNC_START, 1088 .formats = SNDRV_PCM_FMTBIT_MU_LAW | 1089 SNDRV_PCM_FMTBIT_A_LAW | 1090 SNDRV_PCM_FMTBIT_IMA_ADPCM | 1091 SNDRV_PCM_FMTBIT_U8 | 1092 SNDRV_PCM_FMTBIT_S16_LE | 1093 SNDRV_PCM_FMTBIT_S16_BE, 1094 .rates = SNDRV_PCM_RATE_KNOT | 1095 SNDRV_PCM_RATE_8000_48000, 1096 .rate_min = 5510, 1097 .rate_max = 48000, 1098 .channels_min = 1, 1099 .channels_max = 2, 1100 .buffer_bytes_max = 32 * 1024, 1101 .period_bytes_min = 64, 1102 .period_bytes_max = 32 * 1024, 1103 .periods_min = 1, 1104 .periods_max = 1024, 1105 }; 1106 1107 static const struct snd_pcm_hardware snd_cs4231_capture = { 1108 .info = SNDRV_PCM_INFO_MMAP | 1109 SNDRV_PCM_INFO_INTERLEAVED | 1110 SNDRV_PCM_INFO_MMAP_VALID | 1111 SNDRV_PCM_INFO_SYNC_START, 1112 .formats = SNDRV_PCM_FMTBIT_MU_LAW | 1113 SNDRV_PCM_FMTBIT_A_LAW | 1114 SNDRV_PCM_FMTBIT_IMA_ADPCM | 1115 SNDRV_PCM_FMTBIT_U8 | 1116 SNDRV_PCM_FMTBIT_S16_LE | 1117 SNDRV_PCM_FMTBIT_S16_BE, 1118 .rates = SNDRV_PCM_RATE_KNOT | 1119 SNDRV_PCM_RATE_8000_48000, 1120 .rate_min = 5510, 1121 .rate_max = 48000, 1122 .channels_min = 1, 1123 .channels_max = 2, 1124 .buffer_bytes_max = 32 * 1024, 1125 .period_bytes_min = 64, 1126 .period_bytes_max = 32 * 1024, 1127 .periods_min = 1, 1128 .periods_max = 1024, 1129 }; 1130 1131 static int snd_cs4231_playback_open(struct snd_pcm_substream *substream) 1132 { 1133 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1134 struct snd_pcm_runtime *runtime = substream->runtime; 1135 int err; 1136 1137 runtime->hw = snd_cs4231_playback; 1138 1139 err = snd_cs4231_open(chip, CS4231_MODE_PLAY); 1140 if (err < 0) 1141 return err; 1142 chip->playback_substream = substream; 1143 chip->p_periods_sent = 0; 1144 snd_pcm_set_sync(substream); 1145 snd_cs4231_xrate(runtime); 1146 1147 return 0; 1148 } 1149 1150 static int snd_cs4231_capture_open(struct snd_pcm_substream *substream) 1151 { 1152 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1153 struct snd_pcm_runtime *runtime = substream->runtime; 1154 int err; 1155 1156 runtime->hw = snd_cs4231_capture; 1157 1158 err = snd_cs4231_open(chip, CS4231_MODE_RECORD); 1159 if (err < 0) 1160 return err; 1161 chip->capture_substream = substream; 1162 chip->c_periods_sent = 0; 1163 snd_pcm_set_sync(substream); 1164 snd_cs4231_xrate(runtime); 1165 1166 return 0; 1167 } 1168 1169 static int snd_cs4231_playback_close(struct snd_pcm_substream *substream) 1170 { 1171 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1172 1173 snd_cs4231_close(chip, CS4231_MODE_PLAY); 1174 chip->playback_substream = NULL; 1175 1176 return 0; 1177 } 1178 1179 static int snd_cs4231_capture_close(struct snd_pcm_substream *substream) 1180 { 1181 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); 1182 1183 snd_cs4231_close(chip, CS4231_MODE_RECORD); 1184 chip->capture_substream = NULL; 1185 1186 return 0; 1187 } 1188 1189 /* XXX We can do some power-management, in particular on EBUS using 1190 * XXX the audio AUXIO register... 1191 */ 1192 1193 static const struct snd_pcm_ops snd_cs4231_playback_ops = { 1194 .open = snd_cs4231_playback_open, 1195 .close = snd_cs4231_playback_close, 1196 .hw_params = snd_cs4231_playback_hw_params, 1197 .prepare = snd_cs4231_playback_prepare, 1198 .trigger = snd_cs4231_trigger, 1199 .pointer = snd_cs4231_playback_pointer, 1200 }; 1201 1202 static const struct snd_pcm_ops snd_cs4231_capture_ops = { 1203 .open = snd_cs4231_capture_open, 1204 .close = snd_cs4231_capture_close, 1205 .hw_params = snd_cs4231_capture_hw_params, 1206 .prepare = snd_cs4231_capture_prepare, 1207 .trigger = snd_cs4231_trigger, 1208 .pointer = snd_cs4231_capture_pointer, 1209 }; 1210 1211 static int snd_cs4231_pcm(struct snd_card *card) 1212 { 1213 struct snd_cs4231 *chip = card->private_data; 1214 struct snd_pcm *pcm; 1215 int err; 1216 1217 err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm); 1218 if (err < 0) 1219 return err; 1220 1221 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1222 &snd_cs4231_playback_ops); 1223 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 1224 &snd_cs4231_capture_ops); 1225 1226 /* global setup */ 1227 pcm->private_data = chip; 1228 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1229 strcpy(pcm->name, "CS4231"); 1230 1231 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1232 &chip->op->dev, 64 * 1024, 128 * 1024); 1233 1234 chip->pcm = pcm; 1235 1236 return 0; 1237 } 1238 1239 static int snd_cs4231_timer(struct snd_card *card) 1240 { 1241 struct snd_cs4231 *chip = card->private_data; 1242 struct snd_timer *timer; 1243 struct snd_timer_id tid; 1244 int err; 1245 1246 /* Timer initialization */ 1247 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 1248 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 1249 tid.card = card->number; 1250 tid.device = 0; 1251 tid.subdevice = 0; 1252 err = snd_timer_new(card, "CS4231", &tid, &timer); 1253 if (err < 0) 1254 return err; 1255 strcpy(timer->name, "CS4231"); 1256 timer->private_data = chip; 1257 timer->hw = snd_cs4231_timer_table; 1258 chip->timer = timer; 1259 1260 return 0; 1261 } 1262 1263 /* 1264 * MIXER part 1265 */ 1266 1267 static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, 1268 struct snd_ctl_elem_info *uinfo) 1269 { 1270 static const char * const texts[4] = { 1271 "Line", "CD", "Mic", "Mix" 1272 }; 1273 1274 return snd_ctl_enum_info(uinfo, 2, 4, texts); 1275 } 1276 1277 static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, 1278 struct snd_ctl_elem_value *ucontrol) 1279 { 1280 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1281 unsigned long flags; 1282 1283 spin_lock_irqsave(&chip->lock, flags); 1284 ucontrol->value.enumerated.item[0] = 1285 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6; 1286 ucontrol->value.enumerated.item[1] = 1287 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6; 1288 spin_unlock_irqrestore(&chip->lock, flags); 1289 1290 return 0; 1291 } 1292 1293 static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, 1294 struct snd_ctl_elem_value *ucontrol) 1295 { 1296 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1297 unsigned long flags; 1298 unsigned short left, right; 1299 int change; 1300 1301 if (ucontrol->value.enumerated.item[0] > 3 || 1302 ucontrol->value.enumerated.item[1] > 3) 1303 return -EINVAL; 1304 left = ucontrol->value.enumerated.item[0] << 6; 1305 right = ucontrol->value.enumerated.item[1] << 6; 1306 1307 spin_lock_irqsave(&chip->lock, flags); 1308 1309 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left; 1310 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right; 1311 change = left != chip->image[CS4231_LEFT_INPUT] || 1312 right != chip->image[CS4231_RIGHT_INPUT]; 1313 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left); 1314 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right); 1315 1316 spin_unlock_irqrestore(&chip->lock, flags); 1317 1318 return change; 1319 } 1320 1321 static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, 1322 struct snd_ctl_elem_info *uinfo) 1323 { 1324 int mask = (kcontrol->private_value >> 16) & 0xff; 1325 1326 uinfo->type = (mask == 1) ? 1327 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1328 uinfo->count = 1; 1329 uinfo->value.integer.min = 0; 1330 uinfo->value.integer.max = mask; 1331 1332 return 0; 1333 } 1334 1335 static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, 1336 struct snd_ctl_elem_value *ucontrol) 1337 { 1338 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1339 unsigned long flags; 1340 int reg = kcontrol->private_value & 0xff; 1341 int shift = (kcontrol->private_value >> 8) & 0xff; 1342 int mask = (kcontrol->private_value >> 16) & 0xff; 1343 int invert = (kcontrol->private_value >> 24) & 0xff; 1344 1345 spin_lock_irqsave(&chip->lock, flags); 1346 1347 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; 1348 1349 spin_unlock_irqrestore(&chip->lock, flags); 1350 1351 if (invert) 1352 ucontrol->value.integer.value[0] = 1353 (mask - ucontrol->value.integer.value[0]); 1354 1355 return 0; 1356 } 1357 1358 static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, 1359 struct snd_ctl_elem_value *ucontrol) 1360 { 1361 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1362 unsigned long flags; 1363 int reg = kcontrol->private_value & 0xff; 1364 int shift = (kcontrol->private_value >> 8) & 0xff; 1365 int mask = (kcontrol->private_value >> 16) & 0xff; 1366 int invert = (kcontrol->private_value >> 24) & 0xff; 1367 int change; 1368 unsigned short val; 1369 1370 val = (ucontrol->value.integer.value[0] & mask); 1371 if (invert) 1372 val = mask - val; 1373 val <<= shift; 1374 1375 spin_lock_irqsave(&chip->lock, flags); 1376 1377 val = (chip->image[reg] & ~(mask << shift)) | val; 1378 change = val != chip->image[reg]; 1379 snd_cs4231_out(chip, reg, val); 1380 1381 spin_unlock_irqrestore(&chip->lock, flags); 1382 1383 return change; 1384 } 1385 1386 static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, 1387 struct snd_ctl_elem_info *uinfo) 1388 { 1389 int mask = (kcontrol->private_value >> 24) & 0xff; 1390 1391 uinfo->type = mask == 1 ? 1392 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1393 uinfo->count = 2; 1394 uinfo->value.integer.min = 0; 1395 uinfo->value.integer.max = mask; 1396 1397 return 0; 1398 } 1399 1400 static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, 1401 struct snd_ctl_elem_value *ucontrol) 1402 { 1403 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1404 unsigned long flags; 1405 int left_reg = kcontrol->private_value & 0xff; 1406 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1407 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1408 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1409 int mask = (kcontrol->private_value >> 24) & 0xff; 1410 int invert = (kcontrol->private_value >> 22) & 1; 1411 1412 spin_lock_irqsave(&chip->lock, flags); 1413 1414 ucontrol->value.integer.value[0] = 1415 (chip->image[left_reg] >> shift_left) & mask; 1416 ucontrol->value.integer.value[1] = 1417 (chip->image[right_reg] >> shift_right) & mask; 1418 1419 spin_unlock_irqrestore(&chip->lock, flags); 1420 1421 if (invert) { 1422 ucontrol->value.integer.value[0] = 1423 (mask - ucontrol->value.integer.value[0]); 1424 ucontrol->value.integer.value[1] = 1425 (mask - ucontrol->value.integer.value[1]); 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, 1432 struct snd_ctl_elem_value *ucontrol) 1433 { 1434 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); 1435 unsigned long flags; 1436 int left_reg = kcontrol->private_value & 0xff; 1437 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1438 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1439 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1440 int mask = (kcontrol->private_value >> 24) & 0xff; 1441 int invert = (kcontrol->private_value >> 22) & 1; 1442 int change; 1443 unsigned short val1, val2; 1444 1445 val1 = ucontrol->value.integer.value[0] & mask; 1446 val2 = ucontrol->value.integer.value[1] & mask; 1447 if (invert) { 1448 val1 = mask - val1; 1449 val2 = mask - val2; 1450 } 1451 val1 <<= shift_left; 1452 val2 <<= shift_right; 1453 1454 spin_lock_irqsave(&chip->lock, flags); 1455 1456 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; 1457 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; 1458 change = val1 != chip->image[left_reg]; 1459 change |= val2 != chip->image[right_reg]; 1460 snd_cs4231_out(chip, left_reg, val1); 1461 snd_cs4231_out(chip, right_reg, val2); 1462 1463 spin_unlock_irqrestore(&chip->lock, flags); 1464 1465 return change; 1466 } 1467 1468 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ 1469 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \ 1470 .info = snd_cs4231_info_single, \ 1471 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \ 1472 .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) } 1473 1474 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \ 1475 shift_right, mask, invert) \ 1476 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \ 1477 .info = snd_cs4231_info_double, \ 1478 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \ 1479 .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \ 1480 ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) } 1481 1482 static const struct snd_kcontrol_new snd_cs4231_controls[] = { 1483 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, 1484 CS4231_RIGHT_OUTPUT, 7, 7, 1, 1), 1485 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, 1486 CS4231_RIGHT_OUTPUT, 0, 0, 63, 1), 1487 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, 1488 CS4231_RIGHT_LINE_IN, 7, 7, 1, 1), 1489 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, 1490 CS4231_RIGHT_LINE_IN, 0, 0, 31, 1), 1491 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, 1492 CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1), 1493 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, 1494 CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1), 1495 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, 1496 CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1), 1497 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, 1498 CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1), 1499 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1), 1500 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1), 1501 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1), 1502 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0), 1503 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 1504 15, 0), 1505 { 1506 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1507 .name = "Capture Source", 1508 .info = snd_cs4231_info_mux, 1509 .get = snd_cs4231_get_mux, 1510 .put = snd_cs4231_put_mux, 1511 }, 1512 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1513 1, 0), 1514 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0), 1515 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1), 1516 /* SPARC specific uses of XCTL{0,1} general purpose outputs. */ 1517 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1), 1518 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1) 1519 }; 1520 1521 static int snd_cs4231_mixer(struct snd_card *card) 1522 { 1523 struct snd_cs4231 *chip = card->private_data; 1524 int err, idx; 1525 1526 if (snd_BUG_ON(!chip || !chip->pcm)) 1527 return -EINVAL; 1528 1529 strcpy(card->mixername, chip->pcm->name); 1530 1531 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) { 1532 err = snd_ctl_add(card, 1533 snd_ctl_new1(&snd_cs4231_controls[idx], chip)); 1534 if (err < 0) 1535 return err; 1536 } 1537 return 0; 1538 } 1539 1540 static int dev; 1541 1542 static int cs4231_attach_begin(struct platform_device *op, 1543 struct snd_card **rcard) 1544 { 1545 struct snd_card *card; 1546 struct snd_cs4231 *chip; 1547 int err; 1548 1549 *rcard = NULL; 1550 1551 if (dev >= SNDRV_CARDS) 1552 return -ENODEV; 1553 1554 if (!enable[dev]) { 1555 dev++; 1556 return -ENOENT; 1557 } 1558 1559 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE, 1560 sizeof(struct snd_cs4231), &card); 1561 if (err < 0) 1562 return err; 1563 1564 strcpy(card->driver, "CS4231"); 1565 strcpy(card->shortname, "Sun CS4231"); 1566 1567 chip = card->private_data; 1568 chip->card = card; 1569 1570 *rcard = card; 1571 return 0; 1572 } 1573 1574 static int cs4231_attach_finish(struct snd_card *card) 1575 { 1576 struct snd_cs4231 *chip = card->private_data; 1577 int err; 1578 1579 err = snd_cs4231_pcm(card); 1580 if (err < 0) 1581 goto out_err; 1582 1583 err = snd_cs4231_mixer(card); 1584 if (err < 0) 1585 goto out_err; 1586 1587 err = snd_cs4231_timer(card); 1588 if (err < 0) 1589 goto out_err; 1590 1591 err = snd_card_register(card); 1592 if (err < 0) 1593 goto out_err; 1594 1595 dev_set_drvdata(&chip->op->dev, chip); 1596 1597 dev++; 1598 return 0; 1599 1600 out_err: 1601 snd_card_free(card); 1602 return err; 1603 } 1604 1605 #ifdef SBUS_SUPPORT 1606 1607 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id) 1608 { 1609 unsigned long flags; 1610 unsigned char status; 1611 u32 csr; 1612 struct snd_cs4231 *chip = dev_id; 1613 1614 /*This is IRQ is not raised by the cs4231*/ 1615 if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ)) 1616 return IRQ_NONE; 1617 1618 /* ACK the APC interrupt. */ 1619 csr = sbus_readl(chip->port + APCCSR); 1620 1621 sbus_writel(csr, chip->port + APCCSR); 1622 1623 if ((csr & APC_PDMA_READY) && 1624 (csr & APC_PLAY_INT) && 1625 (csr & APC_XINT_PNVA) && 1626 !(csr & APC_XINT_EMPT)) 1627 snd_cs4231_play_callback(chip); 1628 1629 if ((csr & APC_CDMA_READY) && 1630 (csr & APC_CAPT_INT) && 1631 (csr & APC_XINT_CNVA) && 1632 !(csr & APC_XINT_EMPT)) 1633 snd_cs4231_capture_callback(chip); 1634 1635 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS); 1636 1637 if (status & CS4231_TIMER_IRQ) { 1638 if (chip->timer) 1639 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1640 } 1641 1642 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY)) 1643 snd_cs4231_overrange(chip); 1644 1645 /* ACK the CS4231 interrupt. */ 1646 spin_lock_irqsave(&chip->lock, flags); 1647 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0); 1648 spin_unlock_irqrestore(&chip->lock, flags); 1649 1650 return IRQ_HANDLED; 1651 } 1652 1653 /* 1654 * SBUS DMA routines 1655 */ 1656 1657 static int sbus_dma_request(struct cs4231_dma_control *dma_cont, 1658 dma_addr_t bus_addr, size_t len) 1659 { 1660 unsigned long flags; 1661 u32 test, csr; 1662 int err; 1663 struct sbus_dma_info *base = &dma_cont->sbus_info; 1664 1665 if (len >= (1 << 24)) 1666 return -EINVAL; 1667 spin_lock_irqsave(&base->lock, flags); 1668 csr = sbus_readl(base->regs + APCCSR); 1669 err = -EINVAL; 1670 test = APC_CDMA_READY; 1671 if (base->dir == APC_PLAY) 1672 test = APC_PDMA_READY; 1673 if (!(csr & test)) 1674 goto out; 1675 err = -EBUSY; 1676 test = APC_XINT_CNVA; 1677 if (base->dir == APC_PLAY) 1678 test = APC_XINT_PNVA; 1679 if (!(csr & test)) 1680 goto out; 1681 err = 0; 1682 sbus_writel(bus_addr, base->regs + base->dir + APCNVA); 1683 sbus_writel(len, base->regs + base->dir + APCNC); 1684 out: 1685 spin_unlock_irqrestore(&base->lock, flags); 1686 return err; 1687 } 1688 1689 static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d) 1690 { 1691 unsigned long flags; 1692 u32 csr, test; 1693 struct sbus_dma_info *base = &dma_cont->sbus_info; 1694 1695 spin_lock_irqsave(&base->lock, flags); 1696 csr = sbus_readl(base->regs + APCCSR); 1697 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA | 1698 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL | 1699 APC_XINT_PENA; 1700 if (base->dir == APC_RECORD) 1701 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA | 1702 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL; 1703 csr |= test; 1704 sbus_writel(csr, base->regs + APCCSR); 1705 spin_unlock_irqrestore(&base->lock, flags); 1706 } 1707 1708 static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on) 1709 { 1710 unsigned long flags; 1711 u32 csr, shift; 1712 struct sbus_dma_info *base = &dma_cont->sbus_info; 1713 1714 spin_lock_irqsave(&base->lock, flags); 1715 if (!on) { 1716 sbus_writel(0, base->regs + base->dir + APCNC); 1717 sbus_writel(0, base->regs + base->dir + APCNVA); 1718 if (base->dir == APC_PLAY) { 1719 sbus_writel(0, base->regs + base->dir + APCC); 1720 sbus_writel(0, base->regs + base->dir + APCVA); 1721 } 1722 1723 udelay(1200); 1724 } 1725 csr = sbus_readl(base->regs + APCCSR); 1726 shift = 0; 1727 if (base->dir == APC_PLAY) 1728 shift = 1; 1729 if (on) 1730 csr &= ~(APC_CPAUSE << shift); 1731 else 1732 csr |= (APC_CPAUSE << shift); 1733 sbus_writel(csr, base->regs + APCCSR); 1734 if (on) 1735 csr |= (APC_CDMA_READY << shift); 1736 else 1737 csr &= ~(APC_CDMA_READY << shift); 1738 sbus_writel(csr, base->regs + APCCSR); 1739 1740 spin_unlock_irqrestore(&base->lock, flags); 1741 } 1742 1743 static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont) 1744 { 1745 struct sbus_dma_info *base = &dma_cont->sbus_info; 1746 1747 return sbus_readl(base->regs + base->dir + APCVA); 1748 } 1749 1750 /* 1751 * Init and exit routines 1752 */ 1753 1754 static int snd_cs4231_sbus_free(struct snd_cs4231 *chip) 1755 { 1756 struct platform_device *op = chip->op; 1757 1758 if (chip->irq[0]) 1759 free_irq(chip->irq[0], chip); 1760 1761 if (chip->port) 1762 of_iounmap(&op->resource[0], chip->port, chip->regs_size); 1763 1764 return 0; 1765 } 1766 1767 static int snd_cs4231_sbus_dev_free(struct snd_device *device) 1768 { 1769 struct snd_cs4231 *cp = device->device_data; 1770 1771 return snd_cs4231_sbus_free(cp); 1772 } 1773 1774 static const struct snd_device_ops snd_cs4231_sbus_dev_ops = { 1775 .dev_free = snd_cs4231_sbus_dev_free, 1776 }; 1777 1778 static int snd_cs4231_sbus_create(struct snd_card *card, 1779 struct platform_device *op, 1780 int dev) 1781 { 1782 struct snd_cs4231 *chip = card->private_data; 1783 int err; 1784 1785 spin_lock_init(&chip->lock); 1786 spin_lock_init(&chip->c_dma.sbus_info.lock); 1787 spin_lock_init(&chip->p_dma.sbus_info.lock); 1788 mutex_init(&chip->mce_mutex); 1789 mutex_init(&chip->open_mutex); 1790 chip->op = op; 1791 chip->regs_size = resource_size(&op->resource[0]); 1792 memcpy(&chip->image, &snd_cs4231_original_image, 1793 sizeof(snd_cs4231_original_image)); 1794 1795 chip->port = of_ioremap(&op->resource[0], 0, 1796 chip->regs_size, "cs4231"); 1797 if (!chip->port) { 1798 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); 1799 return -EIO; 1800 } 1801 1802 chip->c_dma.sbus_info.regs = chip->port; 1803 chip->p_dma.sbus_info.regs = chip->port; 1804 chip->c_dma.sbus_info.dir = APC_RECORD; 1805 chip->p_dma.sbus_info.dir = APC_PLAY; 1806 1807 chip->p_dma.prepare = sbus_dma_prepare; 1808 chip->p_dma.enable = sbus_dma_enable; 1809 chip->p_dma.request = sbus_dma_request; 1810 chip->p_dma.address = sbus_dma_addr; 1811 1812 chip->c_dma.prepare = sbus_dma_prepare; 1813 chip->c_dma.enable = sbus_dma_enable; 1814 chip->c_dma.request = sbus_dma_request; 1815 chip->c_dma.address = sbus_dma_addr; 1816 1817 if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt, 1818 IRQF_SHARED, "cs4231", chip)) { 1819 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n", 1820 dev, op->archdata.irqs[0]); 1821 snd_cs4231_sbus_free(chip); 1822 return -EBUSY; 1823 } 1824 chip->irq[0] = op->archdata.irqs[0]; 1825 1826 if (snd_cs4231_probe(chip) < 0) { 1827 snd_cs4231_sbus_free(chip); 1828 return -ENODEV; 1829 } 1830 snd_cs4231_init(chip); 1831 1832 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, 1833 chip, &snd_cs4231_sbus_dev_ops)) < 0) { 1834 snd_cs4231_sbus_free(chip); 1835 return err; 1836 } 1837 1838 return 0; 1839 } 1840 1841 static int cs4231_sbus_probe(struct platform_device *op) 1842 { 1843 struct resource *rp = &op->resource[0]; 1844 struct snd_card *card; 1845 int err; 1846 1847 err = cs4231_attach_begin(op, &card); 1848 if (err) 1849 return err; 1850 1851 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d", 1852 card->shortname, 1853 rp->flags & 0xffL, 1854 (unsigned long long)rp->start, 1855 op->archdata.irqs[0]); 1856 1857 err = snd_cs4231_sbus_create(card, op, dev); 1858 if (err < 0) { 1859 snd_card_free(card); 1860 return err; 1861 } 1862 1863 return cs4231_attach_finish(card); 1864 } 1865 #endif 1866 1867 #ifdef EBUS_SUPPORT 1868 1869 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, 1870 void *cookie) 1871 { 1872 struct snd_cs4231 *chip = cookie; 1873 1874 snd_cs4231_play_callback(chip); 1875 } 1876 1877 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, 1878 int event, void *cookie) 1879 { 1880 struct snd_cs4231 *chip = cookie; 1881 1882 snd_cs4231_capture_callback(chip); 1883 } 1884 1885 /* 1886 * EBUS DMA wrappers 1887 */ 1888 1889 static int _ebus_dma_request(struct cs4231_dma_control *dma_cont, 1890 dma_addr_t bus_addr, size_t len) 1891 { 1892 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len); 1893 } 1894 1895 static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on) 1896 { 1897 ebus_dma_enable(&dma_cont->ebus_info, on); 1898 } 1899 1900 static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir) 1901 { 1902 ebus_dma_prepare(&dma_cont->ebus_info, dir); 1903 } 1904 1905 static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont) 1906 { 1907 return ebus_dma_addr(&dma_cont->ebus_info); 1908 } 1909 1910 /* 1911 * Init and exit routines 1912 */ 1913 1914 static int snd_cs4231_ebus_free(struct snd_cs4231 *chip) 1915 { 1916 struct platform_device *op = chip->op; 1917 1918 if (chip->c_dma.ebus_info.regs) { 1919 ebus_dma_unregister(&chip->c_dma.ebus_info); 1920 of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10); 1921 } 1922 if (chip->p_dma.ebus_info.regs) { 1923 ebus_dma_unregister(&chip->p_dma.ebus_info); 1924 of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10); 1925 } 1926 1927 if (chip->port) 1928 of_iounmap(&op->resource[0], chip->port, 0x10); 1929 1930 return 0; 1931 } 1932 1933 static int snd_cs4231_ebus_dev_free(struct snd_device *device) 1934 { 1935 struct snd_cs4231 *cp = device->device_data; 1936 1937 return snd_cs4231_ebus_free(cp); 1938 } 1939 1940 static const struct snd_device_ops snd_cs4231_ebus_dev_ops = { 1941 .dev_free = snd_cs4231_ebus_dev_free, 1942 }; 1943 1944 static int snd_cs4231_ebus_create(struct snd_card *card, 1945 struct platform_device *op, 1946 int dev) 1947 { 1948 struct snd_cs4231 *chip = card->private_data; 1949 int err; 1950 1951 spin_lock_init(&chip->lock); 1952 spin_lock_init(&chip->c_dma.ebus_info.lock); 1953 spin_lock_init(&chip->p_dma.ebus_info.lock); 1954 mutex_init(&chip->mce_mutex); 1955 mutex_init(&chip->open_mutex); 1956 chip->flags |= CS4231_FLAG_EBUS; 1957 chip->op = op; 1958 memcpy(&chip->image, &snd_cs4231_original_image, 1959 sizeof(snd_cs4231_original_image)); 1960 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)"); 1961 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; 1962 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback; 1963 chip->c_dma.ebus_info.client_cookie = chip; 1964 chip->c_dma.ebus_info.irq = op->archdata.irqs[0]; 1965 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)"); 1966 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; 1967 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback; 1968 chip->p_dma.ebus_info.client_cookie = chip; 1969 chip->p_dma.ebus_info.irq = op->archdata.irqs[1]; 1970 1971 chip->p_dma.prepare = _ebus_dma_prepare; 1972 chip->p_dma.enable = _ebus_dma_enable; 1973 chip->p_dma.request = _ebus_dma_request; 1974 chip->p_dma.address = _ebus_dma_addr; 1975 1976 chip->c_dma.prepare = _ebus_dma_prepare; 1977 chip->c_dma.enable = _ebus_dma_enable; 1978 chip->c_dma.request = _ebus_dma_request; 1979 chip->c_dma.address = _ebus_dma_addr; 1980 1981 chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231"); 1982 chip->p_dma.ebus_info.regs = 1983 of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma"); 1984 chip->c_dma.ebus_info.regs = 1985 of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma"); 1986 if (!chip->port || !chip->p_dma.ebus_info.regs || 1987 !chip->c_dma.ebus_info.regs) { 1988 snd_cs4231_ebus_free(chip); 1989 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); 1990 return -EIO; 1991 } 1992 1993 if (ebus_dma_register(&chip->c_dma.ebus_info)) { 1994 snd_cs4231_ebus_free(chip); 1995 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", 1996 dev); 1997 return -EBUSY; 1998 } 1999 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) { 2000 snd_cs4231_ebus_free(chip); 2001 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", 2002 dev); 2003 return -EBUSY; 2004 } 2005 2006 if (ebus_dma_register(&chip->p_dma.ebus_info)) { 2007 snd_cs4231_ebus_free(chip); 2008 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", 2009 dev); 2010 return -EBUSY; 2011 } 2012 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) { 2013 snd_cs4231_ebus_free(chip); 2014 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev); 2015 return -EBUSY; 2016 } 2017 2018 if (snd_cs4231_probe(chip) < 0) { 2019 snd_cs4231_ebus_free(chip); 2020 return -ENODEV; 2021 } 2022 snd_cs4231_init(chip); 2023 2024 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, 2025 chip, &snd_cs4231_ebus_dev_ops)) < 0) { 2026 snd_cs4231_ebus_free(chip); 2027 return err; 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int cs4231_ebus_probe(struct platform_device *op) 2034 { 2035 struct snd_card *card; 2036 int err; 2037 2038 err = cs4231_attach_begin(op, &card); 2039 if (err) 2040 return err; 2041 2042 sprintf(card->longname, "%s at 0x%llx, irq %d", 2043 card->shortname, 2044 op->resource[0].start, 2045 op->archdata.irqs[0]); 2046 2047 err = snd_cs4231_ebus_create(card, op, dev); 2048 if (err < 0) { 2049 snd_card_free(card); 2050 return err; 2051 } 2052 2053 return cs4231_attach_finish(card); 2054 } 2055 #endif 2056 2057 static int cs4231_probe(struct platform_device *op) 2058 { 2059 #ifdef EBUS_SUPPORT 2060 if (of_node_name_eq(op->dev.of_node->parent, "ebus")) 2061 return cs4231_ebus_probe(op); 2062 #endif 2063 #ifdef SBUS_SUPPORT 2064 if (of_node_name_eq(op->dev.of_node->parent, "sbus") || 2065 of_node_name_eq(op->dev.of_node->parent, "sbi")) 2066 return cs4231_sbus_probe(op); 2067 #endif 2068 return -ENODEV; 2069 } 2070 2071 static int cs4231_remove(struct platform_device *op) 2072 { 2073 struct snd_cs4231 *chip = dev_get_drvdata(&op->dev); 2074 2075 snd_card_free(chip->card); 2076 2077 return 0; 2078 } 2079 2080 static const struct of_device_id cs4231_match[] = { 2081 { 2082 .name = "SUNW,CS4231", 2083 }, 2084 { 2085 .name = "audio", 2086 .compatible = "SUNW,CS4231", 2087 }, 2088 {}, 2089 }; 2090 2091 MODULE_DEVICE_TABLE(of, cs4231_match); 2092 2093 static struct platform_driver cs4231_driver = { 2094 .driver = { 2095 .name = "audio", 2096 .of_match_table = cs4231_match, 2097 }, 2098 .probe = cs4231_probe, 2099 .remove = cs4231_remove, 2100 }; 2101 2102 module_platform_driver(cs4231_driver); 2103