1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) ST-Ericsson SA 2012 4 * 5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6 * for ST-Ericsson. 7 * 8 * License terms: 9 */ 10 11 12 #ifndef UX500_MSP_I2S_H 13 #define UX500_MSP_I2S_H 14 15 #include <linux/platform_device.h> 16 #include <linux/platform_data/asoc-ux500-msp.h> 17 18 #define MSP_INPUT_FREQ_APB 48000000 19 20 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), 21 * 32 bits accesses (stereo). 22 ***/ 23 enum msp_stereo_mode { 24 MSP_MONO, 25 MSP_STEREO 26 }; 27 28 /* Direction (Transmit/Receive mode) */ 29 enum msp_direction { 30 MSP_TX = 1, 31 MSP_RX = 2 32 }; 33 34 /* Transmit and receive configuration register */ 35 #define MSP_BIG_ENDIAN 0x00000000 36 #define MSP_LITTLE_ENDIAN 0x00001000 37 #define MSP_UNEXPECTED_FS_ABORT 0x00000000 38 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000 39 #define MSP_NON_MODE_BIT_MASK 0x00009000 40 41 /* Global configuration register */ 42 #define RX_ENABLE 0x00000001 43 #define RX_FIFO_ENABLE 0x00000002 44 #define RX_SYNC_SRG 0x00000010 45 #define RX_CLK_POL_RISING 0x00000020 46 #define RX_CLK_SEL_SRG 0x00000040 47 #define TX_ENABLE 0x00000100 48 #define TX_FIFO_ENABLE 0x00000200 49 #define TX_SYNC_SRG_PROG 0x00001800 50 #define TX_SYNC_SRG_AUTO 0x00001000 51 #define TX_CLK_POL_RISING 0x00002000 52 #define TX_CLK_SEL_SRG 0x00004000 53 #define TX_EXTRA_DELAY_ENABLE 0x00008000 54 #define SRG_ENABLE 0x00010000 55 #define FRAME_GEN_ENABLE 0x00100000 56 #define SRG_CLK_SEL_APB 0x00000000 57 #define RX_FIFO_SYNC_HI 0x00000000 58 #define TX_FIFO_SYNC_HI 0x00000000 59 #define SPI_CLK_MODE_NORMAL 0x00000000 60 61 #define MSP_FRAME_SIZE_AUTO -1 62 63 #define MSP_DR 0x00 64 #define MSP_GCR 0x04 65 #define MSP_TCF 0x08 66 #define MSP_RCF 0x0c 67 #define MSP_SRG 0x10 68 #define MSP_FLR 0x14 69 #define MSP_DMACR 0x18 70 71 #define MSP_IMSC 0x20 72 #define MSP_RIS 0x24 73 #define MSP_MIS 0x28 74 #define MSP_ICR 0x2c 75 #define MSP_MCR 0x30 76 #define MSP_RCV 0x34 77 #define MSP_RCM 0x38 78 79 #define MSP_TCE0 0x40 80 #define MSP_TCE1 0x44 81 #define MSP_TCE2 0x48 82 #define MSP_TCE3 0x4c 83 84 #define MSP_RCE0 0x60 85 #define MSP_RCE1 0x64 86 #define MSP_RCE2 0x68 87 #define MSP_RCE3 0x6c 88 #define MSP_IODLY 0x70 89 90 #define MSP_ITCR 0x80 91 #define MSP_ITIP 0x84 92 #define MSP_ITOP 0x88 93 #define MSP_TSTDR 0x8c 94 95 #define MSP_PID0 0xfe0 96 #define MSP_PID1 0xfe4 97 #define MSP_PID2 0xfe8 98 #define MSP_PID3 0xfec 99 100 #define MSP_CID0 0xff0 101 #define MSP_CID1 0xff4 102 #define MSP_CID2 0xff8 103 #define MSP_CID3 0xffc 104 105 /* Protocol dependant parameters list */ 106 #define RX_ENABLE_MASK BIT(0) 107 #define RX_FIFO_ENABLE_MASK BIT(1) 108 #define RX_FSYNC_MASK BIT(2) 109 #define DIRECT_COMPANDING_MASK BIT(3) 110 #define RX_SYNC_SEL_MASK BIT(4) 111 #define RX_CLK_POL_MASK BIT(5) 112 #define RX_CLK_SEL_MASK BIT(6) 113 #define LOOPBACK_MASK BIT(7) 114 #define TX_ENABLE_MASK BIT(8) 115 #define TX_FIFO_ENABLE_MASK BIT(9) 116 #define TX_FSYNC_MASK BIT(10) 117 #define TX_MSP_TDR_TSR BIT(11) 118 #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11)) 119 #define TX_CLK_POL_MASK BIT(13) 120 #define TX_CLK_SEL_MASK BIT(14) 121 #define TX_EXTRA_DELAY_MASK BIT(15) 122 #define SRG_ENABLE_MASK BIT(16) 123 #define SRG_CLK_POL_MASK BIT(17) 124 #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18)) 125 #define FRAME_GEN_EN_MASK BIT(20) 126 #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21)) 127 #define SPI_BURST_MODE_MASK BIT(23) 128 129 #define RXEN_SHIFT 0 130 #define RFFEN_SHIFT 1 131 #define RFSPOL_SHIFT 2 132 #define DCM_SHIFT 3 133 #define RFSSEL_SHIFT 4 134 #define RCKPOL_SHIFT 5 135 #define RCKSEL_SHIFT 6 136 #define LBM_SHIFT 7 137 #define TXEN_SHIFT 8 138 #define TFFEN_SHIFT 9 139 #define TFSPOL_SHIFT 10 140 #define TFSSEL_SHIFT 11 141 #define TCKPOL_SHIFT 13 142 #define TCKSEL_SHIFT 14 143 #define TXDDL_SHIFT 15 144 #define SGEN_SHIFT 16 145 #define SCKPOL_SHIFT 17 146 #define SCKSEL_SHIFT 18 147 #define FGEN_SHIFT 20 148 #define SPICKM_SHIFT 21 149 #define TBSWAP_SHIFT 28 150 151 #define RCKPOL_MASK BIT(0) 152 #define TCKPOL_MASK BIT(0) 153 #define SPICKM_MASK (BIT(1) | BIT(0)) 154 #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT) 155 #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT) 156 157 #define P1ELEN_SHIFT 0 158 #define P1FLEN_SHIFT 3 159 #define DTYP_SHIFT 10 160 #define ENDN_SHIFT 12 161 #define DDLY_SHIFT 13 162 #define FSIG_SHIFT 15 163 #define P2ELEN_SHIFT 16 164 #define P2FLEN_SHIFT 19 165 #define P2SM_SHIFT 26 166 #define P2EN_SHIFT 27 167 #define FSYNC_SHIFT 15 168 169 #define P1ELEN_MASK 0x00000007 170 #define P2ELEN_MASK 0x00070000 171 #define P1FLEN_MASK 0x00000378 172 #define P2FLEN_MASK 0x03780000 173 #define DDLY_MASK 0x00003000 174 #define DTYP_MASK 0x00000600 175 #define P2SM_MASK 0x04000000 176 #define P2EN_MASK 0x08000000 177 #define ENDN_MASK 0x00001000 178 #define TFSPOL_MASK 0x00000400 179 #define TBSWAP_MASK 0x30000000 180 #define COMPANDING_MODE_MASK 0x00000c00 181 #define FSYNC_MASK 0x00008000 182 183 #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK) 184 #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK) 185 #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK) 186 #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK) 187 #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK) 188 #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK) 189 #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK) 190 #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK) 191 #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK) 192 #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK) 193 #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK) 194 #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \ 195 COMPANDING_MODE_MASK) 196 #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK) 197 198 /* Flag register */ 199 #define RX_BUSY BIT(0) 200 #define RX_FIFO_EMPTY BIT(1) 201 #define RX_FIFO_FULL BIT(2) 202 #define TX_BUSY BIT(3) 203 #define TX_FIFO_EMPTY BIT(4) 204 #define TX_FIFO_FULL BIT(5) 205 206 #define RBUSY_SHIFT 0 207 #define RFE_SHIFT 1 208 #define RFU_SHIFT 2 209 #define TBUSY_SHIFT 3 210 #define TFE_SHIFT 4 211 #define TFU_SHIFT 5 212 213 /* Multichannel control register */ 214 #define RMCEN_SHIFT 0 215 #define RMCSF_SHIFT 1 216 #define RCMPM_SHIFT 3 217 #define TMCEN_SHIFT 5 218 #define TNCSF_SHIFT 6 219 220 /* Sample rate generator register */ 221 #define SCKDIV_SHIFT 0 222 #define FRWID_SHIFT 10 223 #define FRPER_SHIFT 16 224 225 #define SCK_DIV_MASK 0x0000003FF 226 #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00) 227 #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000) 228 229 /* DMA controller register */ 230 #define RX_DMA_ENABLE BIT(0) 231 #define TX_DMA_ENABLE BIT(1) 232 233 #define RDMAE_SHIFT 0 234 #define TDMAE_SHIFT 1 235 236 /* Interrupt Register */ 237 #define RX_SERVICE_INT BIT(0) 238 #define RX_OVERRUN_ERROR_INT BIT(1) 239 #define RX_FSYNC_ERR_INT BIT(2) 240 #define RX_FSYNC_INT BIT(3) 241 #define TX_SERVICE_INT BIT(4) 242 #define TX_UNDERRUN_ERR_INT BIT(5) 243 #define TX_FSYNC_ERR_INT BIT(6) 244 #define TX_FSYNC_INT BIT(7) 245 #define ALL_INT 0x000000ff 246 247 /* MSP test control register */ 248 #define MSP_ITCR_ITEN BIT(0) 249 #define MSP_ITCR_TESTFIFO BIT(1) 250 251 #define RMCEN_BIT 0 252 #define RMCSF_BIT 1 253 #define RCMPM_BIT 3 254 #define TMCEN_BIT 5 255 #define TNCSF_BIT 6 256 257 /* Single or dual phase mode */ 258 enum msp_phase_mode { 259 MSP_SINGLE_PHASE, 260 MSP_DUAL_PHASE 261 }; 262 263 /* Frame length */ 264 enum msp_frame_length { 265 MSP_FRAME_LEN_1 = 0, 266 MSP_FRAME_LEN_2 = 1, 267 MSP_FRAME_LEN_4 = 3, 268 MSP_FRAME_LEN_8 = 7, 269 MSP_FRAME_LEN_12 = 11, 270 MSP_FRAME_LEN_16 = 15, 271 MSP_FRAME_LEN_20 = 19, 272 MSP_FRAME_LEN_32 = 31, 273 MSP_FRAME_LEN_48 = 47, 274 MSP_FRAME_LEN_64 = 63 275 }; 276 277 /* Element length */ 278 enum msp_elem_length { 279 MSP_ELEM_LEN_8 = 0, 280 MSP_ELEM_LEN_10 = 1, 281 MSP_ELEM_LEN_12 = 2, 282 MSP_ELEM_LEN_14 = 3, 283 MSP_ELEM_LEN_16 = 4, 284 MSP_ELEM_LEN_20 = 5, 285 MSP_ELEM_LEN_24 = 6, 286 MSP_ELEM_LEN_32 = 7 287 }; 288 289 enum msp_data_xfer_width { 290 MSP_DATA_TRANSFER_WIDTH_BYTE, 291 MSP_DATA_TRANSFER_WIDTH_HALFWORD, 292 MSP_DATA_TRANSFER_WIDTH_WORD 293 }; 294 295 enum msp_frame_sync { 296 MSP_FSYNC_UNIGNORE = 0, 297 MSP_FSYNC_IGNORE = 1, 298 }; 299 300 enum msp_phase2_start_mode { 301 MSP_PHASE2_START_MODE_IMEDIATE, 302 MSP_PHASE2_START_MODE_FSYNC 303 }; 304 305 enum msp_btf { 306 MSP_BTF_MS_BIT_FIRST = 0, 307 MSP_BTF_LS_BIT_FIRST = 1 308 }; 309 310 enum msp_fsync_pol { 311 MSP_FSYNC_POL_ACT_HI = 0, 312 MSP_FSYNC_POL_ACT_LO = 1 313 }; 314 315 /* Data delay (in bit clock cycles) */ 316 enum msp_delay { 317 MSP_DELAY_0 = 0, 318 MSP_DELAY_1 = 1, 319 MSP_DELAY_2 = 2, 320 MSP_DELAY_3 = 3 321 }; 322 323 /* Configurations of clocks (transmit, receive or sample rate generator) */ 324 enum msp_edge { 325 MSP_FALLING_EDGE = 0, 326 MSP_RISING_EDGE = 1, 327 }; 328 329 enum msp_hws { 330 MSP_SWAP_NONE = 0, 331 MSP_SWAP_BYTE_PER_WORD = 1, 332 MSP_SWAP_BYTE_PER_HALF_WORD = 2, 333 MSP_SWAP_HALF_WORD_PER_WORD = 3 334 }; 335 336 enum msp_compress_mode { 337 MSP_COMPRESS_MODE_LINEAR = 0, 338 MSP_COMPRESS_MODE_MU_LAW = 2, 339 MSP_COMPRESS_MODE_A_LAW = 3 340 }; 341 342 enum msp_expand_mode { 343 MSP_EXPAND_MODE_LINEAR = 0, 344 MSP_EXPAND_MODE_LINEAR_SIGNED = 1, 345 MSP_EXPAND_MODE_MU_LAW = 2, 346 MSP_EXPAND_MODE_A_LAW = 3 347 }; 348 349 #define MSP_FRAME_PERIOD_IN_MONO_MODE 256 350 #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 351 #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 352 353 enum msp_protocol { 354 MSP_I2S_PROTOCOL, 355 MSP_PCM_PROTOCOL, 356 MSP_PCM_COMPAND_PROTOCOL, 357 MSP_INVALID_PROTOCOL 358 }; 359 360 /* 361 * No of registers to backup during 362 * suspend resume 363 */ 364 #define MAX_MSP_BACKUP_REGS 36 365 366 enum i2s_direction_t { 367 MSP_DIR_TX = 0x01, 368 MSP_DIR_RX = 0x02, 369 }; 370 371 enum msp_data_size { 372 MSP_DATA_BITS_DEFAULT = -1, 373 MSP_DATA_BITS_8 = 0x00, 374 MSP_DATA_BITS_10, 375 MSP_DATA_BITS_12, 376 MSP_DATA_BITS_14, 377 MSP_DATA_BITS_16, 378 MSP_DATA_BITS_20, 379 MSP_DATA_BITS_24, 380 MSP_DATA_BITS_32, 381 }; 382 383 enum msp_state { 384 MSP_STATE_IDLE = 0, 385 MSP_STATE_CONFIGURED = 1, 386 MSP_STATE_RUNNING = 2, 387 }; 388 389 enum msp_rx_comparison_enable_mode { 390 MSP_COMPARISON_DISABLED = 0, 391 MSP_COMPARISON_NONEQUAL_ENABLED = 2, 392 MSP_COMPARISON_EQUAL_ENABLED = 3 393 }; 394 395 struct msp_multichannel_config { 396 bool rx_multichannel_enable; 397 bool tx_multichannel_enable; 398 enum msp_rx_comparison_enable_mode rx_comparison_enable_mode; 399 u8 padding; 400 u32 comparison_value; 401 u32 comparison_mask; 402 u32 rx_channel_0_enable; 403 u32 rx_channel_1_enable; 404 u32 rx_channel_2_enable; 405 u32 rx_channel_3_enable; 406 u32 tx_channel_0_enable; 407 u32 tx_channel_1_enable; 408 u32 tx_channel_2_enable; 409 u32 tx_channel_3_enable; 410 }; 411 412 struct msp_protdesc { 413 u32 rx_phase_mode; 414 u32 tx_phase_mode; 415 u32 rx_phase2_start_mode; 416 u32 tx_phase2_start_mode; 417 u32 rx_byte_order; 418 u32 tx_byte_order; 419 u32 rx_frame_len_1; 420 u32 rx_frame_len_2; 421 u32 tx_frame_len_1; 422 u32 tx_frame_len_2; 423 u32 rx_elem_len_1; 424 u32 rx_elem_len_2; 425 u32 tx_elem_len_1; 426 u32 tx_elem_len_2; 427 u32 rx_data_delay; 428 u32 tx_data_delay; 429 u32 rx_clk_pol; 430 u32 tx_clk_pol; 431 u32 rx_fsync_pol; 432 u32 tx_fsync_pol; 433 u32 rx_half_word_swap; 434 u32 tx_half_word_swap; 435 u32 compression_mode; 436 u32 expansion_mode; 437 u32 frame_sync_ignore; 438 u32 frame_period; 439 u32 frame_width; 440 u32 clocks_per_frame; 441 }; 442 443 struct ux500_msp_config { 444 unsigned int f_inputclk; 445 unsigned int rx_clk_sel; 446 unsigned int tx_clk_sel; 447 unsigned int srg_clk_sel; 448 unsigned int rx_fsync_pol; 449 unsigned int tx_fsync_pol; 450 unsigned int rx_fsync_sel; 451 unsigned int tx_fsync_sel; 452 unsigned int rx_fifo_config; 453 unsigned int tx_fifo_config; 454 unsigned int loopback_enable; 455 unsigned int tx_data_enable; 456 unsigned int default_protdesc; 457 struct msp_protdesc protdesc; 458 int multichannel_configured; 459 struct msp_multichannel_config multichannel_config; 460 unsigned int direction; 461 unsigned int protocol; 462 unsigned int frame_freq; 463 enum msp_data_size data_size; 464 unsigned int def_elem_len; 465 unsigned int iodelay; 466 }; 467 468 struct ux500_msp_dma_params { 469 unsigned int data_size; 470 dma_addr_t tx_rx_addr; 471 struct stedma40_chan_cfg *dma_cfg; 472 }; 473 474 struct ux500_msp { 475 int id; 476 void __iomem *registers; 477 struct device *dev; 478 struct ux500_msp_dma_params playback_dma_data; 479 struct ux500_msp_dma_params capture_dma_data; 480 enum msp_state msp_state; 481 int def_elem_len; 482 unsigned int dir_busy; 483 int loopback_enable; 484 unsigned int f_bitclk; 485 }; 486 487 struct msp_i2s_platform_data; 488 int ux500_msp_i2s_init_msp(struct platform_device *pdev, 489 struct ux500_msp **msp_p, 490 struct msp_i2s_platform_data *platform_data); 491 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, 492 struct ux500_msp *msp); 493 int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config); 494 int ux500_msp_i2s_close(struct ux500_msp *msp, 495 unsigned int dir); 496 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, 497 int direction); 498 499 #endif 500