1 /* 2 * Copyright (C) ST-Ericsson SA 2012 3 * 4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 5 * for ST-Ericsson. 6 * 7 * License terms: 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14 15 #ifndef UX500_MSP_I2S_H 16 #define UX500_MSP_I2S_H 17 18 #include <linux/platform_device.h> 19 20 #define MSP_INPUT_FREQ_APB 48000000 21 22 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), 23 * 32 bits accesses (stereo). 24 ***/ 25 enum msp_stereo_mode { 26 MSP_MONO, 27 MSP_STEREO 28 }; 29 30 /* Direction (Transmit/Receive mode) */ 31 enum msp_direction { 32 MSP_TX = 1, 33 MSP_RX = 2 34 }; 35 36 /* Transmit and receive configuration register */ 37 #define MSP_BIG_ENDIAN 0x00000000 38 #define MSP_LITTLE_ENDIAN 0x00001000 39 #define MSP_UNEXPECTED_FS_ABORT 0x00000000 40 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000 41 #define MSP_NON_MODE_BIT_MASK 0x00009000 42 43 /* Global configuration register */ 44 #define RX_ENABLE 0x00000001 45 #define RX_FIFO_ENABLE 0x00000002 46 #define RX_SYNC_SRG 0x00000010 47 #define RX_CLK_POL_RISING 0x00000020 48 #define RX_CLK_SEL_SRG 0x00000040 49 #define TX_ENABLE 0x00000100 50 #define TX_FIFO_ENABLE 0x00000200 51 #define TX_SYNC_SRG_PROG 0x00001800 52 #define TX_SYNC_SRG_AUTO 0x00001000 53 #define TX_CLK_POL_RISING 0x00002000 54 #define TX_CLK_SEL_SRG 0x00004000 55 #define TX_EXTRA_DELAY_ENABLE 0x00008000 56 #define SRG_ENABLE 0x00010000 57 #define FRAME_GEN_ENABLE 0x00100000 58 #define SRG_CLK_SEL_APB 0x00000000 59 #define RX_FIFO_SYNC_HI 0x00000000 60 #define TX_FIFO_SYNC_HI 0x00000000 61 #define SPI_CLK_MODE_NORMAL 0x00000000 62 63 #define MSP_FRAME_SIZE_AUTO -1 64 65 #define MSP_DR 0x00 66 #define MSP_GCR 0x04 67 #define MSP_TCF 0x08 68 #define MSP_RCF 0x0c 69 #define MSP_SRG 0x10 70 #define MSP_FLR 0x14 71 #define MSP_DMACR 0x18 72 73 #define MSP_IMSC 0x20 74 #define MSP_RIS 0x24 75 #define MSP_MIS 0x28 76 #define MSP_ICR 0x2c 77 #define MSP_MCR 0x30 78 #define MSP_RCV 0x34 79 #define MSP_RCM 0x38 80 81 #define MSP_TCE0 0x40 82 #define MSP_TCE1 0x44 83 #define MSP_TCE2 0x48 84 #define MSP_TCE3 0x4c 85 86 #define MSP_RCE0 0x60 87 #define MSP_RCE1 0x64 88 #define MSP_RCE2 0x68 89 #define MSP_RCE3 0x6c 90 #define MSP_IODLY 0x70 91 92 #define MSP_ITCR 0x80 93 #define MSP_ITIP 0x84 94 #define MSP_ITOP 0x88 95 #define MSP_TSTDR 0x8c 96 97 #define MSP_PID0 0xfe0 98 #define MSP_PID1 0xfe4 99 #define MSP_PID2 0xfe8 100 #define MSP_PID3 0xfec 101 102 #define MSP_CID0 0xff0 103 #define MSP_CID1 0xff4 104 #define MSP_CID2 0xff8 105 #define MSP_CID3 0xffc 106 107 /* Protocol dependant parameters list */ 108 #define RX_ENABLE_MASK BIT(0) 109 #define RX_FIFO_ENABLE_MASK BIT(1) 110 #define RX_FSYNC_MASK BIT(2) 111 #define DIRECT_COMPANDING_MASK BIT(3) 112 #define RX_SYNC_SEL_MASK BIT(4) 113 #define RX_CLK_POL_MASK BIT(5) 114 #define RX_CLK_SEL_MASK BIT(6) 115 #define LOOPBACK_MASK BIT(7) 116 #define TX_ENABLE_MASK BIT(8) 117 #define TX_FIFO_ENABLE_MASK BIT(9) 118 #define TX_FSYNC_MASK BIT(10) 119 #define TX_MSP_TDR_TSR BIT(11) 120 #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11)) 121 #define TX_CLK_POL_MASK BIT(13) 122 #define TX_CLK_SEL_MASK BIT(14) 123 #define TX_EXTRA_DELAY_MASK BIT(15) 124 #define SRG_ENABLE_MASK BIT(16) 125 #define SRG_CLK_POL_MASK BIT(17) 126 #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18)) 127 #define FRAME_GEN_EN_MASK BIT(20) 128 #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21)) 129 #define SPI_BURST_MODE_MASK BIT(23) 130 131 #define RXEN_SHIFT 0 132 #define RFFEN_SHIFT 1 133 #define RFSPOL_SHIFT 2 134 #define DCM_SHIFT 3 135 #define RFSSEL_SHIFT 4 136 #define RCKPOL_SHIFT 5 137 #define RCKSEL_SHIFT 6 138 #define LBM_SHIFT 7 139 #define TXEN_SHIFT 8 140 #define TFFEN_SHIFT 9 141 #define TFSPOL_SHIFT 10 142 #define TFSSEL_SHIFT 11 143 #define TCKPOL_SHIFT 13 144 #define TCKSEL_SHIFT 14 145 #define TXDDL_SHIFT 15 146 #define SGEN_SHIFT 16 147 #define SCKPOL_SHIFT 17 148 #define SCKSEL_SHIFT 18 149 #define FGEN_SHIFT 20 150 #define SPICKM_SHIFT 21 151 #define TBSWAP_SHIFT 28 152 153 #define RCKPOL_MASK BIT(0) 154 #define TCKPOL_MASK BIT(0) 155 #define SPICKM_MASK (BIT(1) | BIT(0)) 156 #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT) 157 #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT) 158 159 #define P1ELEN_SHIFT 0 160 #define P1FLEN_SHIFT 3 161 #define DTYP_SHIFT 10 162 #define ENDN_SHIFT 12 163 #define DDLY_SHIFT 13 164 #define FSIG_SHIFT 15 165 #define P2ELEN_SHIFT 16 166 #define P2FLEN_SHIFT 19 167 #define P2SM_SHIFT 26 168 #define P2EN_SHIFT 27 169 #define FSYNC_SHIFT 15 170 171 #define P1ELEN_MASK 0x00000007 172 #define P2ELEN_MASK 0x00070000 173 #define P1FLEN_MASK 0x00000378 174 #define P2FLEN_MASK 0x03780000 175 #define DDLY_MASK 0x00003000 176 #define DTYP_MASK 0x00000600 177 #define P2SM_MASK 0x04000000 178 #define P2EN_MASK 0x08000000 179 #define ENDN_MASK 0x00001000 180 #define TFSPOL_MASK 0x00000400 181 #define TBSWAP_MASK 0x30000000 182 #define COMPANDING_MODE_MASK 0x00000c00 183 #define FSYNC_MASK 0x00008000 184 185 #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK) 186 #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK) 187 #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK) 188 #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK) 189 #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK) 190 #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK) 191 #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK) 192 #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK) 193 #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK) 194 #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK) 195 #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK) 196 #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \ 197 COMPANDING_MODE_MASK) 198 #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK) 199 200 /* Flag register */ 201 #define RX_BUSY BIT(0) 202 #define RX_FIFO_EMPTY BIT(1) 203 #define RX_FIFO_FULL BIT(2) 204 #define TX_BUSY BIT(3) 205 #define TX_FIFO_EMPTY BIT(4) 206 #define TX_FIFO_FULL BIT(5) 207 208 #define RBUSY_SHIFT 0 209 #define RFE_SHIFT 1 210 #define RFU_SHIFT 2 211 #define TBUSY_SHIFT 3 212 #define TFE_SHIFT 4 213 #define TFU_SHIFT 5 214 215 /* Multichannel control register */ 216 #define RMCEN_SHIFT 0 217 #define RMCSF_SHIFT 1 218 #define RCMPM_SHIFT 3 219 #define TMCEN_SHIFT 5 220 #define TNCSF_SHIFT 6 221 222 /* Sample rate generator register */ 223 #define SCKDIV_SHIFT 0 224 #define FRWID_SHIFT 10 225 #define FRPER_SHIFT 16 226 227 #define SCK_DIV_MASK 0x0000003FF 228 #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00) 229 #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000) 230 231 /* DMA controller register */ 232 #define RX_DMA_ENABLE BIT(0) 233 #define TX_DMA_ENABLE BIT(1) 234 235 #define RDMAE_SHIFT 0 236 #define TDMAE_SHIFT 1 237 238 /* Interrupt Register */ 239 #define RX_SERVICE_INT BIT(0) 240 #define RX_OVERRUN_ERROR_INT BIT(1) 241 #define RX_FSYNC_ERR_INT BIT(2) 242 #define RX_FSYNC_INT BIT(3) 243 #define TX_SERVICE_INT BIT(4) 244 #define TX_UNDERRUN_ERR_INT BIT(5) 245 #define TX_FSYNC_ERR_INT BIT(6) 246 #define TX_FSYNC_INT BIT(7) 247 #define ALL_INT 0x000000ff 248 249 /* MSP test control register */ 250 #define MSP_ITCR_ITEN BIT(0) 251 #define MSP_ITCR_TESTFIFO BIT(1) 252 253 #define RMCEN_BIT 0 254 #define RMCSF_BIT 1 255 #define RCMPM_BIT 3 256 #define TMCEN_BIT 5 257 #define TNCSF_BIT 6 258 259 /* Single or dual phase mode */ 260 enum msp_phase_mode { 261 MSP_SINGLE_PHASE, 262 MSP_DUAL_PHASE 263 }; 264 265 /* Frame length */ 266 enum msp_frame_length { 267 MSP_FRAME_LEN_1 = 0, 268 MSP_FRAME_LEN_2 = 1, 269 MSP_FRAME_LEN_4 = 3, 270 MSP_FRAME_LEN_8 = 7, 271 MSP_FRAME_LEN_12 = 11, 272 MSP_FRAME_LEN_16 = 15, 273 MSP_FRAME_LEN_20 = 19, 274 MSP_FRAME_LEN_32 = 31, 275 MSP_FRAME_LEN_48 = 47, 276 MSP_FRAME_LEN_64 = 63 277 }; 278 279 /* Element length */ 280 enum msp_elem_length { 281 MSP_ELEM_LEN_8 = 0, 282 MSP_ELEM_LEN_10 = 1, 283 MSP_ELEM_LEN_12 = 2, 284 MSP_ELEM_LEN_14 = 3, 285 MSP_ELEM_LEN_16 = 4, 286 MSP_ELEM_LEN_20 = 5, 287 MSP_ELEM_LEN_24 = 6, 288 MSP_ELEM_LEN_32 = 7 289 }; 290 291 enum msp_data_xfer_width { 292 MSP_DATA_TRANSFER_WIDTH_BYTE, 293 MSP_DATA_TRANSFER_WIDTH_HALFWORD, 294 MSP_DATA_TRANSFER_WIDTH_WORD 295 }; 296 297 enum msp_frame_sync { 298 MSP_FSYNC_UNIGNORE = 0, 299 MSP_FSYNC_IGNORE = 1, 300 }; 301 302 enum msp_phase2_start_mode { 303 MSP_PHASE2_START_MODE_IMEDIATE, 304 MSP_PHASE2_START_MODE_FSYNC 305 }; 306 307 enum msp_btf { 308 MSP_BTF_MS_BIT_FIRST = 0, 309 MSP_BTF_LS_BIT_FIRST = 1 310 }; 311 312 enum msp_fsync_pol { 313 MSP_FSYNC_POL_ACT_HI = 0, 314 MSP_FSYNC_POL_ACT_LO = 1 315 }; 316 317 /* Data delay (in bit clock cycles) */ 318 enum msp_delay { 319 MSP_DELAY_0 = 0, 320 MSP_DELAY_1 = 1, 321 MSP_DELAY_2 = 2, 322 MSP_DELAY_3 = 3 323 }; 324 325 /* Configurations of clocks (transmit, receive or sample rate generator) */ 326 enum msp_edge { 327 MSP_FALLING_EDGE = 0, 328 MSP_RISING_EDGE = 1, 329 }; 330 331 enum msp_hws { 332 MSP_SWAP_NONE = 0, 333 MSP_SWAP_BYTE_PER_WORD = 1, 334 MSP_SWAP_BYTE_PER_HALF_WORD = 2, 335 MSP_SWAP_HALF_WORD_PER_WORD = 3 336 }; 337 338 enum msp_compress_mode { 339 MSP_COMPRESS_MODE_LINEAR = 0, 340 MSP_COMPRESS_MODE_MU_LAW = 2, 341 MSP_COMPRESS_MODE_A_LAW = 3 342 }; 343 344 enum msp_spi_burst_mode { 345 MSP_SPI_BURST_MODE_DISABLE = 0, 346 MSP_SPI_BURST_MODE_ENABLE = 1 347 }; 348 349 enum msp_expand_mode { 350 MSP_EXPAND_MODE_LINEAR = 0, 351 MSP_EXPAND_MODE_LINEAR_SIGNED = 1, 352 MSP_EXPAND_MODE_MU_LAW = 2, 353 MSP_EXPAND_MODE_A_LAW = 3 354 }; 355 356 #define MSP_FRAME_PERIOD_IN_MONO_MODE 256 357 #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 358 #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 359 360 enum msp_protocol { 361 MSP_I2S_PROTOCOL, 362 MSP_PCM_PROTOCOL, 363 MSP_PCM_COMPAND_PROTOCOL, 364 MSP_INVALID_PROTOCOL 365 }; 366 367 /* 368 * No of registers to backup during 369 * suspend resume 370 */ 371 #define MAX_MSP_BACKUP_REGS 36 372 373 enum enum_i2s_controller { 374 MSP_0_I2S_CONTROLLER = 0, 375 MSP_1_I2S_CONTROLLER, 376 MSP_2_I2S_CONTROLLER, 377 MSP_3_I2S_CONTROLLER, 378 }; 379 380 enum i2s_direction_t { 381 MSP_DIR_TX = 0x01, 382 MSP_DIR_RX = 0x02, 383 }; 384 385 enum msp_data_size { 386 MSP_DATA_BITS_DEFAULT = -1, 387 MSP_DATA_BITS_8 = 0x00, 388 MSP_DATA_BITS_10, 389 MSP_DATA_BITS_12, 390 MSP_DATA_BITS_14, 391 MSP_DATA_BITS_16, 392 MSP_DATA_BITS_20, 393 MSP_DATA_BITS_24, 394 MSP_DATA_BITS_32, 395 }; 396 397 enum msp_state { 398 MSP_STATE_IDLE = 0, 399 MSP_STATE_CONFIGURED = 1, 400 MSP_STATE_RUNNING = 2, 401 }; 402 403 enum msp_rx_comparison_enable_mode { 404 MSP_COMPARISON_DISABLED = 0, 405 MSP_COMPARISON_NONEQUAL_ENABLED = 2, 406 MSP_COMPARISON_EQUAL_ENABLED = 3 407 }; 408 409 struct msp_multichannel_config { 410 bool rx_multichannel_enable; 411 bool tx_multichannel_enable; 412 enum msp_rx_comparison_enable_mode rx_comparison_enable_mode; 413 u8 padding; 414 u32 comparison_value; 415 u32 comparison_mask; 416 u32 rx_channel_0_enable; 417 u32 rx_channel_1_enable; 418 u32 rx_channel_2_enable; 419 u32 rx_channel_3_enable; 420 u32 tx_channel_0_enable; 421 u32 tx_channel_1_enable; 422 u32 tx_channel_2_enable; 423 u32 tx_channel_3_enable; 424 }; 425 426 struct msp_protdesc { 427 u32 rx_phase_mode; 428 u32 tx_phase_mode; 429 u32 rx_phase2_start_mode; 430 u32 tx_phase2_start_mode; 431 u32 rx_byte_order; 432 u32 tx_byte_order; 433 u32 rx_frame_len_1; 434 u32 rx_frame_len_2; 435 u32 tx_frame_len_1; 436 u32 tx_frame_len_2; 437 u32 rx_elem_len_1; 438 u32 rx_elem_len_2; 439 u32 tx_elem_len_1; 440 u32 tx_elem_len_2; 441 u32 rx_data_delay; 442 u32 tx_data_delay; 443 u32 rx_clk_pol; 444 u32 tx_clk_pol; 445 u32 rx_fsync_pol; 446 u32 tx_fsync_pol; 447 u32 rx_half_word_swap; 448 u32 tx_half_word_swap; 449 u32 compression_mode; 450 u32 expansion_mode; 451 u32 frame_sync_ignore; 452 u32 frame_period; 453 u32 frame_width; 454 u32 clocks_per_frame; 455 }; 456 457 struct i2s_message { 458 enum i2s_direction_t i2s_direction; 459 void *txdata; 460 void *rxdata; 461 size_t txbytes; 462 size_t rxbytes; 463 int dma_flag; 464 int tx_offset; 465 int rx_offset; 466 bool cyclic_dma; 467 dma_addr_t buf_addr; 468 size_t buf_len; 469 size_t period_len; 470 }; 471 472 struct i2s_controller { 473 struct module *owner; 474 unsigned int id; 475 unsigned int class; 476 const struct i2s_algorithm *algo; /* the algorithm to access the bus */ 477 void *data; 478 struct mutex bus_lock; 479 struct device dev; /* the controller device */ 480 char name[48]; 481 }; 482 483 struct ux500_msp_config { 484 unsigned int f_inputclk; 485 unsigned int rx_clk_sel; 486 unsigned int tx_clk_sel; 487 unsigned int srg_clk_sel; 488 unsigned int rx_fsync_pol; 489 unsigned int tx_fsync_pol; 490 unsigned int rx_fsync_sel; 491 unsigned int tx_fsync_sel; 492 unsigned int rx_fifo_config; 493 unsigned int tx_fifo_config; 494 unsigned int spi_clk_mode; 495 unsigned int spi_burst_mode; 496 unsigned int loopback_enable; 497 unsigned int tx_data_enable; 498 unsigned int default_protdesc; 499 struct msp_protdesc protdesc; 500 int multichannel_configured; 501 struct msp_multichannel_config multichannel_config; 502 unsigned int direction; 503 unsigned int protocol; 504 unsigned int frame_freq; 505 unsigned int frame_size; 506 enum msp_data_size data_size; 507 unsigned int def_elem_len; 508 unsigned int iodelay; 509 void (*handler) (void *data); 510 void *tx_callback_data; 511 void *rx_callback_data; 512 }; 513 514 struct ux500_msp { 515 enum enum_i2s_controller id; 516 void __iomem *registers; 517 struct device *dev; 518 struct i2s_controller *i2s_cont; 519 struct stedma40_chan_cfg *dma_cfg_rx; 520 struct stedma40_chan_cfg *dma_cfg_tx; 521 struct dma_chan *tx_pipeid; 522 struct dma_chan *rx_pipeid; 523 enum msp_state msp_state; 524 int (*transfer) (struct ux500_msp *msp, struct i2s_message *message); 525 struct timer_list notify_timer; 526 int def_elem_len; 527 unsigned int dir_busy; 528 int loopback_enable; 529 u32 backup_regs[MAX_MSP_BACKUP_REGS]; 530 unsigned int f_bitclk; 531 /* Pin modes */ 532 struct pinctrl *pinctrl_p; 533 struct pinctrl_state *pinctrl_def; 534 struct pinctrl_state *pinctrl_sleep; 535 /* Reference Count */ 536 int pinctrl_rxtx_ref; 537 }; 538 539 struct ux500_msp_dma_params { 540 unsigned int data_size; 541 struct stedma40_chan_cfg *dma_cfg; 542 }; 543 544 struct msp_i2s_platform_data; 545 int ux500_msp_i2s_init_msp(struct platform_device *pdev, 546 struct ux500_msp **msp_p, 547 struct msp_i2s_platform_data *platform_data); 548 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, 549 struct ux500_msp *msp); 550 int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config); 551 int ux500_msp_i2s_close(struct ux500_msp *msp, 552 unsigned int dir); 553 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, 554 int direction); 555 556 #endif 557