1 /* 2 * Copyright (C) ST-Ericsson SA 2012 3 * 4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 5 * Roger Nilsson <roger.xr.nilsson@stericsson.com>, 6 * Sandeep Kaushik <sandeep.kaushik@st.com> 7 * for ST-Ericsson. 8 * 9 * License terms: 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as published 13 * by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/platform_data/asoc-ux500-msp.h> 24 25 #include <sound/soc.h> 26 27 #include "ux500_msp_i2s.h" 28 29 /* MSP1/3 Tx/Rx usage protection */ 30 static DEFINE_SPINLOCK(msp_rxtx_lock); 31 32 /* Protocol desciptors */ 33 static const struct msp_protdesc prot_descs[] = { 34 { /* I2S */ 35 MSP_SINGLE_PHASE, 36 MSP_SINGLE_PHASE, 37 MSP_PHASE2_START_MODE_IMEDIATE, 38 MSP_PHASE2_START_MODE_IMEDIATE, 39 MSP_BTF_MS_BIT_FIRST, 40 MSP_BTF_MS_BIT_FIRST, 41 MSP_FRAME_LEN_1, 42 MSP_FRAME_LEN_1, 43 MSP_FRAME_LEN_1, 44 MSP_FRAME_LEN_1, 45 MSP_ELEM_LEN_32, 46 MSP_ELEM_LEN_32, 47 MSP_ELEM_LEN_32, 48 MSP_ELEM_LEN_32, 49 MSP_DELAY_1, 50 MSP_DELAY_1, 51 MSP_RISING_EDGE, 52 MSP_FALLING_EDGE, 53 MSP_FSYNC_POL_ACT_LO, 54 MSP_FSYNC_POL_ACT_LO, 55 MSP_SWAP_NONE, 56 MSP_SWAP_NONE, 57 MSP_COMPRESS_MODE_LINEAR, 58 MSP_EXPAND_MODE_LINEAR, 59 MSP_FSYNC_IGNORE, 60 31, 61 15, 62 32, 63 }, { /* PCM */ 64 MSP_DUAL_PHASE, 65 MSP_DUAL_PHASE, 66 MSP_PHASE2_START_MODE_FSYNC, 67 MSP_PHASE2_START_MODE_FSYNC, 68 MSP_BTF_MS_BIT_FIRST, 69 MSP_BTF_MS_BIT_FIRST, 70 MSP_FRAME_LEN_1, 71 MSP_FRAME_LEN_1, 72 MSP_FRAME_LEN_1, 73 MSP_FRAME_LEN_1, 74 MSP_ELEM_LEN_16, 75 MSP_ELEM_LEN_16, 76 MSP_ELEM_LEN_16, 77 MSP_ELEM_LEN_16, 78 MSP_DELAY_0, 79 MSP_DELAY_0, 80 MSP_RISING_EDGE, 81 MSP_FALLING_EDGE, 82 MSP_FSYNC_POL_ACT_HI, 83 MSP_FSYNC_POL_ACT_HI, 84 MSP_SWAP_NONE, 85 MSP_SWAP_NONE, 86 MSP_COMPRESS_MODE_LINEAR, 87 MSP_EXPAND_MODE_LINEAR, 88 MSP_FSYNC_IGNORE, 89 255, 90 0, 91 256, 92 }, { /* Companded PCM */ 93 MSP_SINGLE_PHASE, 94 MSP_SINGLE_PHASE, 95 MSP_PHASE2_START_MODE_FSYNC, 96 MSP_PHASE2_START_MODE_FSYNC, 97 MSP_BTF_MS_BIT_FIRST, 98 MSP_BTF_MS_BIT_FIRST, 99 MSP_FRAME_LEN_1, 100 MSP_FRAME_LEN_1, 101 MSP_FRAME_LEN_1, 102 MSP_FRAME_LEN_1, 103 MSP_ELEM_LEN_8, 104 MSP_ELEM_LEN_8, 105 MSP_ELEM_LEN_8, 106 MSP_ELEM_LEN_8, 107 MSP_DELAY_0, 108 MSP_DELAY_0, 109 MSP_RISING_EDGE, 110 MSP_RISING_EDGE, 111 MSP_FSYNC_POL_ACT_HI, 112 MSP_FSYNC_POL_ACT_HI, 113 MSP_SWAP_NONE, 114 MSP_SWAP_NONE, 115 MSP_COMPRESS_MODE_LINEAR, 116 MSP_EXPAND_MODE_LINEAR, 117 MSP_FSYNC_IGNORE, 118 255, 119 0, 120 256, 121 }, 122 }; 123 124 static void set_prot_desc_tx(struct ux500_msp *msp, 125 struct msp_protdesc *protdesc, 126 enum msp_data_size data_size) 127 { 128 u32 temp_reg = 0; 129 130 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode); 131 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode); 132 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1); 133 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2); 134 if (msp->def_elem_len) { 135 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1); 136 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2); 137 } else { 138 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); 139 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); 140 } 141 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay); 142 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order); 143 temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol); 144 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap); 145 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode); 146 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); 147 148 writel(temp_reg, msp->registers + MSP_TCF); 149 } 150 151 static void set_prot_desc_rx(struct ux500_msp *msp, 152 struct msp_protdesc *protdesc, 153 enum msp_data_size data_size) 154 { 155 u32 temp_reg = 0; 156 157 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode); 158 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode); 159 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1); 160 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2); 161 if (msp->def_elem_len) { 162 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1); 163 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2); 164 } else { 165 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); 166 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); 167 } 168 169 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay); 170 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order); 171 temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol); 172 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap); 173 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode); 174 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); 175 176 writel(temp_reg, msp->registers + MSP_RCF); 177 } 178 179 static int configure_protocol(struct ux500_msp *msp, 180 struct ux500_msp_config *config) 181 { 182 struct msp_protdesc *protdesc; 183 enum msp_data_size data_size; 184 u32 temp_reg = 0; 185 186 data_size = config->data_size; 187 msp->def_elem_len = config->def_elem_len; 188 if (config->default_protdesc == 1) { 189 if (config->protocol >= MSP_INVALID_PROTOCOL) { 190 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n", 191 __func__); 192 return -EINVAL; 193 } 194 protdesc = 195 (struct msp_protdesc *)&prot_descs[config->protocol]; 196 } else { 197 protdesc = (struct msp_protdesc *)&config->protdesc; 198 } 199 200 if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) { 201 dev_err(msp->dev, 202 "%s: ERROR: Invalid data-size requested (data_size = %d)!\n", 203 __func__, data_size); 204 return -EINVAL; 205 } 206 207 if (config->direction & MSP_DIR_TX) 208 set_prot_desc_tx(msp, protdesc, data_size); 209 if (config->direction & MSP_DIR_RX) 210 set_prot_desc_rx(msp, protdesc, data_size); 211 212 /* The code below should not be separated. */ 213 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; 214 temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol); 215 writel(temp_reg, msp->registers + MSP_GCR); 216 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; 217 temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol); 218 writel(temp_reg, msp->registers + MSP_GCR); 219 220 return 0; 221 } 222 223 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config) 224 { 225 u32 reg_val_GCR; 226 u32 frame_per = 0; 227 u32 sck_div = 0; 228 u32 frame_width = 0; 229 u32 temp_reg = 0; 230 struct msp_protdesc *protdesc = NULL; 231 232 reg_val_GCR = readl(msp->registers + MSP_GCR); 233 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); 234 235 if (config->default_protdesc) 236 protdesc = 237 (struct msp_protdesc *)&prot_descs[config->protocol]; 238 else 239 protdesc = (struct msp_protdesc *)&config->protdesc; 240 241 switch (config->protocol) { 242 case MSP_PCM_PROTOCOL: 243 case MSP_PCM_COMPAND_PROTOCOL: 244 frame_width = protdesc->frame_width; 245 sck_div = config->f_inputclk / (config->frame_freq * 246 (protdesc->clocks_per_frame)); 247 frame_per = protdesc->frame_period; 248 break; 249 case MSP_I2S_PROTOCOL: 250 frame_width = protdesc->frame_width; 251 sck_div = config->f_inputclk / (config->frame_freq * 252 (protdesc->clocks_per_frame)); 253 frame_per = protdesc->frame_period; 254 break; 255 default: 256 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n", 257 __func__, 258 config->protocol); 259 return -EINVAL; 260 } 261 262 temp_reg = (sck_div - 1) & SCK_DIV_MASK; 263 temp_reg |= FRAME_WIDTH_BITS(frame_width); 264 temp_reg |= FRAME_PERIOD_BITS(frame_per); 265 writel(temp_reg, msp->registers + MSP_SRG); 266 267 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1); 268 269 /* Enable bit-clock */ 270 udelay(100); 271 reg_val_GCR = readl(msp->registers + MSP_GCR); 272 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); 273 udelay(100); 274 275 return 0; 276 } 277 278 static int configure_multichannel(struct ux500_msp *msp, 279 struct ux500_msp_config *config) 280 { 281 struct msp_protdesc *protdesc; 282 struct msp_multichannel_config *mcfg; 283 u32 reg_val_MCR; 284 285 if (config->default_protdesc == 1) { 286 if (config->protocol >= MSP_INVALID_PROTOCOL) { 287 dev_err(msp->dev, 288 "%s: ERROR: Invalid protocol (%d)!\n", 289 __func__, config->protocol); 290 return -EINVAL; 291 } 292 protdesc = (struct msp_protdesc *) 293 &prot_descs[config->protocol]; 294 } else { 295 protdesc = (struct msp_protdesc *)&config->protdesc; 296 } 297 298 mcfg = &config->multichannel_config; 299 if (mcfg->tx_multichannel_enable) { 300 if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) { 301 reg_val_MCR = readl(msp->registers + MSP_MCR); 302 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? 303 1 << TMCEN_BIT : 0), 304 msp->registers + MSP_MCR); 305 writel(mcfg->tx_channel_0_enable, 306 msp->registers + MSP_TCE0); 307 writel(mcfg->tx_channel_1_enable, 308 msp->registers + MSP_TCE1); 309 writel(mcfg->tx_channel_2_enable, 310 msp->registers + MSP_TCE2); 311 writel(mcfg->tx_channel_3_enable, 312 msp->registers + MSP_TCE3); 313 } else { 314 dev_err(msp->dev, 315 "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n", 316 __func__, protdesc->tx_phase_mode); 317 return -EINVAL; 318 } 319 } 320 if (mcfg->rx_multichannel_enable) { 321 if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) { 322 reg_val_MCR = readl(msp->registers + MSP_MCR); 323 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? 324 1 << RMCEN_BIT : 0), 325 msp->registers + MSP_MCR); 326 writel(mcfg->rx_channel_0_enable, 327 msp->registers + MSP_RCE0); 328 writel(mcfg->rx_channel_1_enable, 329 msp->registers + MSP_RCE1); 330 writel(mcfg->rx_channel_2_enable, 331 msp->registers + MSP_RCE2); 332 writel(mcfg->rx_channel_3_enable, 333 msp->registers + MSP_RCE3); 334 } else { 335 dev_err(msp->dev, 336 "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n", 337 __func__, protdesc->rx_phase_mode); 338 return -EINVAL; 339 } 340 if (mcfg->rx_comparison_enable_mode) { 341 reg_val_MCR = readl(msp->registers + MSP_MCR); 342 writel(reg_val_MCR | 343 (mcfg->rx_comparison_enable_mode << RCMPM_BIT), 344 msp->registers + MSP_MCR); 345 346 writel(mcfg->comparison_mask, 347 msp->registers + MSP_RCM); 348 writel(mcfg->comparison_value, 349 msp->registers + MSP_RCV); 350 351 } 352 } 353 354 return 0; 355 } 356 357 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) 358 { 359 int status = 0, retval = 0; 360 u32 reg_val_DMACR, reg_val_GCR; 361 unsigned long flags; 362 363 /* Check msp state whether in RUN or CONFIGURED Mode */ 364 if (msp->msp_state == MSP_STATE_IDLE) { 365 spin_lock_irqsave(&msp_rxtx_lock, flags); 366 if (msp->pinctrl_rxtx_ref == 0 && 367 !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_def))) { 368 retval = pinctrl_select_state(msp->pinctrl_p, 369 msp->pinctrl_def); 370 if (retval) 371 pr_err("could not set MSP defstate\n"); 372 } 373 if (!retval) 374 msp->pinctrl_rxtx_ref++; 375 spin_unlock_irqrestore(&msp_rxtx_lock, flags); 376 } 377 378 /* Configure msp with protocol dependent settings */ 379 configure_protocol(msp, config); 380 setup_bitclk(msp, config); 381 if (config->multichannel_configured == 1) { 382 status = configure_multichannel(msp, config); 383 if (status) 384 dev_warn(msp->dev, 385 "%s: WARN: configure_multichannel failed (%d)!\n", 386 __func__, status); 387 } 388 389 /* Make sure the correct DMA-directions are configured */ 390 if ((config->direction & MSP_DIR_RX) && (!msp->dma_cfg_rx)) { 391 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!", 392 __func__); 393 return -EINVAL; 394 } 395 if ((config->direction == MSP_DIR_TX) && (!msp->dma_cfg_tx)) { 396 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!", 397 __func__); 398 return -EINVAL; 399 } 400 401 reg_val_DMACR = readl(msp->registers + MSP_DMACR); 402 if (config->direction & MSP_DIR_RX) 403 reg_val_DMACR |= RX_DMA_ENABLE; 404 if (config->direction & MSP_DIR_TX) 405 reg_val_DMACR |= TX_DMA_ENABLE; 406 writel(reg_val_DMACR, msp->registers + MSP_DMACR); 407 408 writel(config->iodelay, msp->registers + MSP_IODLY); 409 410 /* Enable frame generation logic */ 411 reg_val_GCR = readl(msp->registers + MSP_GCR); 412 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); 413 414 return status; 415 } 416 417 static void flush_fifo_rx(struct ux500_msp *msp) 418 { 419 u32 reg_val_DR, reg_val_GCR, reg_val_FLR; 420 u32 limit = 32; 421 422 reg_val_GCR = readl(msp->registers + MSP_GCR); 423 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); 424 425 reg_val_FLR = readl(msp->registers + MSP_FLR); 426 while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) { 427 reg_val_DR = readl(msp->registers + MSP_DR); 428 reg_val_FLR = readl(msp->registers + MSP_FLR); 429 } 430 431 writel(reg_val_GCR, msp->registers + MSP_GCR); 432 } 433 434 static void flush_fifo_tx(struct ux500_msp *msp) 435 { 436 u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR; 437 u32 limit = 32; 438 439 reg_val_GCR = readl(msp->registers + MSP_GCR); 440 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); 441 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); 442 443 reg_val_FLR = readl(msp->registers + MSP_FLR); 444 while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) { 445 reg_val_TSTDR = readl(msp->registers + MSP_TSTDR); 446 reg_val_FLR = readl(msp->registers + MSP_FLR); 447 } 448 writel(0x0, msp->registers + MSP_ITCR); 449 writel(reg_val_GCR, msp->registers + MSP_GCR); 450 } 451 452 int ux500_msp_i2s_open(struct ux500_msp *msp, 453 struct ux500_msp_config *config) 454 { 455 u32 old_reg, new_reg, mask; 456 int res; 457 unsigned int tx_sel, rx_sel, tx_busy, rx_busy; 458 459 if (in_interrupt()) { 460 dev_err(msp->dev, 461 "%s: ERROR: Open called in interrupt context!\n", 462 __func__); 463 return -1; 464 } 465 466 tx_sel = (config->direction & MSP_DIR_TX) > 0; 467 rx_sel = (config->direction & MSP_DIR_RX) > 0; 468 if (!tx_sel && !rx_sel) { 469 dev_err(msp->dev, "%s: Error: No direction selected!\n", 470 __func__); 471 return -EINVAL; 472 } 473 474 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0; 475 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0; 476 if (tx_busy && tx_sel) { 477 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__); 478 return -EBUSY; 479 } 480 if (rx_busy && rx_sel) { 481 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__); 482 return -EBUSY; 483 } 484 485 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0); 486 487 /* First do the global config register */ 488 mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK | 489 TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK | 490 RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK | 491 LOOPBACK_MASK | TX_EXTRA_DELAY_MASK; 492 493 new_reg = (config->tx_clk_sel | config->rx_clk_sel | 494 config->rx_fsync_pol | config->tx_fsync_pol | 495 config->rx_fsync_sel | config->tx_fsync_sel | 496 config->rx_fifo_config | config->tx_fifo_config | 497 config->srg_clk_sel | config->loopback_enable | 498 config->tx_data_enable); 499 500 old_reg = readl(msp->registers + MSP_GCR); 501 old_reg &= ~mask; 502 new_reg |= old_reg; 503 writel(new_reg, msp->registers + MSP_GCR); 504 505 res = enable_msp(msp, config); 506 if (res < 0) { 507 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n", 508 __func__, res); 509 return -EBUSY; 510 } 511 if (config->loopback_enable & 0x80) 512 msp->loopback_enable = 1; 513 514 /* Flush FIFOs */ 515 flush_fifo_tx(msp); 516 flush_fifo_rx(msp); 517 518 msp->msp_state = MSP_STATE_CONFIGURED; 519 return 0; 520 } 521 522 static void disable_msp_rx(struct ux500_msp *msp) 523 { 524 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; 525 526 reg_val_GCR = readl(msp->registers + MSP_GCR); 527 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); 528 reg_val_DMACR = readl(msp->registers + MSP_DMACR); 529 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); 530 reg_val_IMSC = readl(msp->registers + MSP_IMSC); 531 writel(reg_val_IMSC & 532 ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT), 533 msp->registers + MSP_IMSC); 534 535 msp->dir_busy &= ~MSP_DIR_RX; 536 } 537 538 static void disable_msp_tx(struct ux500_msp *msp) 539 { 540 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; 541 542 reg_val_GCR = readl(msp->registers + MSP_GCR); 543 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); 544 reg_val_DMACR = readl(msp->registers + MSP_DMACR); 545 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); 546 reg_val_IMSC = readl(msp->registers + MSP_IMSC); 547 writel(reg_val_IMSC & 548 ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT), 549 msp->registers + MSP_IMSC); 550 551 msp->dir_busy &= ~MSP_DIR_TX; 552 } 553 554 static int disable_msp(struct ux500_msp *msp, unsigned int dir) 555 { 556 u32 reg_val_GCR; 557 int status = 0; 558 unsigned int disable_tx, disable_rx; 559 560 reg_val_GCR = readl(msp->registers + MSP_GCR); 561 disable_tx = dir & MSP_DIR_TX; 562 disable_rx = dir & MSP_DIR_TX; 563 if (disable_tx && disable_rx) { 564 reg_val_GCR = readl(msp->registers + MSP_GCR); 565 writel(reg_val_GCR | LOOPBACK_MASK, 566 msp->registers + MSP_GCR); 567 568 /* Flush TX-FIFO */ 569 flush_fifo_tx(msp); 570 571 /* Disable TX-channel */ 572 writel((readl(msp->registers + MSP_GCR) & 573 (~TX_ENABLE)), msp->registers + MSP_GCR); 574 575 /* Flush RX-FIFO */ 576 flush_fifo_rx(msp); 577 578 /* Disable Loopback and Receive channel */ 579 writel((readl(msp->registers + MSP_GCR) & 580 (~(RX_ENABLE | LOOPBACK_MASK))), 581 msp->registers + MSP_GCR); 582 583 disable_msp_tx(msp); 584 disable_msp_rx(msp); 585 } else if (disable_tx) 586 disable_msp_tx(msp); 587 else if (disable_rx) 588 disable_msp_rx(msp); 589 590 return status; 591 } 592 593 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction) 594 { 595 u32 reg_val_GCR, enable_bit; 596 597 if (msp->msp_state == MSP_STATE_IDLE) { 598 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n", 599 __func__); 600 return -EINVAL; 601 } 602 603 switch (cmd) { 604 case SNDRV_PCM_TRIGGER_START: 605 case SNDRV_PCM_TRIGGER_RESUME: 606 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 607 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 608 enable_bit = TX_ENABLE; 609 else 610 enable_bit = RX_ENABLE; 611 reg_val_GCR = readl(msp->registers + MSP_GCR); 612 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); 613 break; 614 615 case SNDRV_PCM_TRIGGER_STOP: 616 case SNDRV_PCM_TRIGGER_SUSPEND: 617 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 618 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 619 disable_msp_tx(msp); 620 else 621 disable_msp_rx(msp); 622 break; 623 default: 624 return -EINVAL; 625 break; 626 } 627 628 return 0; 629 } 630 631 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir) 632 { 633 int status = 0, retval = 0; 634 unsigned long flags; 635 636 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir); 637 638 status = disable_msp(msp, dir); 639 if (msp->dir_busy == 0) { 640 /* disable sample rate and frame generators */ 641 msp->msp_state = MSP_STATE_IDLE; 642 writel((readl(msp->registers + MSP_GCR) & 643 (~(FRAME_GEN_ENABLE | SRG_ENABLE))), 644 msp->registers + MSP_GCR); 645 646 spin_lock_irqsave(&msp_rxtx_lock, flags); 647 WARN_ON(!msp->pinctrl_rxtx_ref); 648 msp->pinctrl_rxtx_ref--; 649 if (msp->pinctrl_rxtx_ref == 0 && 650 !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_sleep))) { 651 retval = pinctrl_select_state(msp->pinctrl_p, 652 msp->pinctrl_sleep); 653 if (retval) 654 pr_err("could not set MSP sleepstate\n"); 655 } 656 spin_unlock_irqrestore(&msp_rxtx_lock, flags); 657 658 writel(0, msp->registers + MSP_GCR); 659 writel(0, msp->registers + MSP_TCF); 660 writel(0, msp->registers + MSP_RCF); 661 writel(0, msp->registers + MSP_DMACR); 662 writel(0, msp->registers + MSP_SRG); 663 writel(0, msp->registers + MSP_MCR); 664 writel(0, msp->registers + MSP_RCM); 665 writel(0, msp->registers + MSP_RCV); 666 writel(0, msp->registers + MSP_TCE0); 667 writel(0, msp->registers + MSP_TCE1); 668 writel(0, msp->registers + MSP_TCE2); 669 writel(0, msp->registers + MSP_TCE3); 670 writel(0, msp->registers + MSP_RCE0); 671 writel(0, msp->registers + MSP_RCE1); 672 writel(0, msp->registers + MSP_RCE2); 673 writel(0, msp->registers + MSP_RCE3); 674 } 675 676 return status; 677 678 } 679 680 int ux500_msp_i2s_init_msp(struct platform_device *pdev, 681 struct ux500_msp **msp_p, 682 struct msp_i2s_platform_data *platform_data) 683 { 684 struct resource *res = NULL; 685 struct i2s_controller *i2s_cont; 686 struct device_node *np = pdev->dev.of_node; 687 struct ux500_msp *msp; 688 689 *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL); 690 msp = *msp_p; 691 if (!msp) 692 return -ENOMEM; 693 694 if (np) { 695 if (!platform_data) { 696 platform_data = devm_kzalloc(&pdev->dev, 697 sizeof(struct msp_i2s_platform_data), GFP_KERNEL); 698 if (!platform_data) 699 return -ENOMEM; 700 } 701 } else 702 if (!platform_data) 703 return -EINVAL; 704 705 dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__, 706 pdev->name, platform_data->id); 707 708 msp->id = platform_data->id; 709 msp->dev = &pdev->dev; 710 msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx; 711 msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx; 712 713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 714 if (res == NULL) { 715 dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n", 716 __func__); 717 return -ENOMEM; 718 } 719 720 msp->registers = devm_ioremap(&pdev->dev, res->start, 721 resource_size(res)); 722 if (msp->registers == NULL) { 723 dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__); 724 return -ENOMEM; 725 } 726 727 msp->msp_state = MSP_STATE_IDLE; 728 msp->loopback_enable = 0; 729 730 /* I2S-controller is allocated and added in I2S controller class. */ 731 i2s_cont = devm_kzalloc(&pdev->dev, sizeof(*i2s_cont), GFP_KERNEL); 732 if (!i2s_cont) { 733 dev_err(&pdev->dev, 734 "%s: ERROR: Failed to allocate I2S-controller!\n", 735 __func__); 736 return -ENOMEM; 737 } 738 i2s_cont->dev.parent = &pdev->dev; 739 i2s_cont->data = (void *)msp; 740 i2s_cont->id = (s16)msp->id; 741 snprintf(i2s_cont->name, sizeof(i2s_cont->name), "ux500-msp-i2s.%04x", 742 msp->id); 743 dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name); 744 msp->i2s_cont = i2s_cont; 745 746 msp->pinctrl_p = pinctrl_get(msp->dev); 747 if (IS_ERR(msp->pinctrl_p)) 748 dev_err(&pdev->dev, "could not get MSP pinctrl\n"); 749 else { 750 msp->pinctrl_def = pinctrl_lookup_state(msp->pinctrl_p, 751 PINCTRL_STATE_DEFAULT); 752 if (IS_ERR(msp->pinctrl_def)) { 753 dev_err(&pdev->dev, 754 "could not get MSP defstate (%li)\n", 755 PTR_ERR(msp->pinctrl_def)); 756 } 757 msp->pinctrl_sleep = pinctrl_lookup_state(msp->pinctrl_p, 758 PINCTRL_STATE_SLEEP); 759 if (IS_ERR(msp->pinctrl_sleep)) 760 dev_err(&pdev->dev, 761 "could not get MSP idlestate (%li)\n", 762 PTR_ERR(msp->pinctrl_def)); 763 } 764 765 return 0; 766 } 767 768 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, 769 struct ux500_msp *msp) 770 { 771 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id); 772 773 device_unregister(&msp->i2s_cont->dev); 774 } 775 776 MODULE_LICENSE("GPL v2"); 777