1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2012 4 * 5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6 * Roger Nilsson <roger.xr.nilsson@stericsson.com>, 7 * Sandeep Kaushik <sandeep.kaushik@st.com> 8 * for ST-Ericsson. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/delay.h> 14 #include <linux/slab.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/platform_data/asoc-ux500-msp.h> 18 19 #include <sound/soc.h> 20 21 #include "ux500_msp_i2s.h" 22 23 /* Protocol desciptors */ 24 static const struct msp_protdesc prot_descs[] = { 25 { /* I2S */ 26 MSP_SINGLE_PHASE, 27 MSP_SINGLE_PHASE, 28 MSP_PHASE2_START_MODE_IMEDIATE, 29 MSP_PHASE2_START_MODE_IMEDIATE, 30 MSP_BTF_MS_BIT_FIRST, 31 MSP_BTF_MS_BIT_FIRST, 32 MSP_FRAME_LEN_1, 33 MSP_FRAME_LEN_1, 34 MSP_FRAME_LEN_1, 35 MSP_FRAME_LEN_1, 36 MSP_ELEM_LEN_32, 37 MSP_ELEM_LEN_32, 38 MSP_ELEM_LEN_32, 39 MSP_ELEM_LEN_32, 40 MSP_DELAY_1, 41 MSP_DELAY_1, 42 MSP_RISING_EDGE, 43 MSP_FALLING_EDGE, 44 MSP_FSYNC_POL_ACT_LO, 45 MSP_FSYNC_POL_ACT_LO, 46 MSP_SWAP_NONE, 47 MSP_SWAP_NONE, 48 MSP_COMPRESS_MODE_LINEAR, 49 MSP_EXPAND_MODE_LINEAR, 50 MSP_FSYNC_IGNORE, 51 31, 52 15, 53 32, 54 }, { /* PCM */ 55 MSP_DUAL_PHASE, 56 MSP_DUAL_PHASE, 57 MSP_PHASE2_START_MODE_FSYNC, 58 MSP_PHASE2_START_MODE_FSYNC, 59 MSP_BTF_MS_BIT_FIRST, 60 MSP_BTF_MS_BIT_FIRST, 61 MSP_FRAME_LEN_1, 62 MSP_FRAME_LEN_1, 63 MSP_FRAME_LEN_1, 64 MSP_FRAME_LEN_1, 65 MSP_ELEM_LEN_16, 66 MSP_ELEM_LEN_16, 67 MSP_ELEM_LEN_16, 68 MSP_ELEM_LEN_16, 69 MSP_DELAY_0, 70 MSP_DELAY_0, 71 MSP_RISING_EDGE, 72 MSP_FALLING_EDGE, 73 MSP_FSYNC_POL_ACT_HI, 74 MSP_FSYNC_POL_ACT_HI, 75 MSP_SWAP_NONE, 76 MSP_SWAP_NONE, 77 MSP_COMPRESS_MODE_LINEAR, 78 MSP_EXPAND_MODE_LINEAR, 79 MSP_FSYNC_IGNORE, 80 255, 81 0, 82 256, 83 }, { /* Companded PCM */ 84 MSP_SINGLE_PHASE, 85 MSP_SINGLE_PHASE, 86 MSP_PHASE2_START_MODE_FSYNC, 87 MSP_PHASE2_START_MODE_FSYNC, 88 MSP_BTF_MS_BIT_FIRST, 89 MSP_BTF_MS_BIT_FIRST, 90 MSP_FRAME_LEN_1, 91 MSP_FRAME_LEN_1, 92 MSP_FRAME_LEN_1, 93 MSP_FRAME_LEN_1, 94 MSP_ELEM_LEN_8, 95 MSP_ELEM_LEN_8, 96 MSP_ELEM_LEN_8, 97 MSP_ELEM_LEN_8, 98 MSP_DELAY_0, 99 MSP_DELAY_0, 100 MSP_RISING_EDGE, 101 MSP_RISING_EDGE, 102 MSP_FSYNC_POL_ACT_HI, 103 MSP_FSYNC_POL_ACT_HI, 104 MSP_SWAP_NONE, 105 MSP_SWAP_NONE, 106 MSP_COMPRESS_MODE_LINEAR, 107 MSP_EXPAND_MODE_LINEAR, 108 MSP_FSYNC_IGNORE, 109 255, 110 0, 111 256, 112 }, 113 }; 114 115 static void set_prot_desc_tx(struct ux500_msp *msp, 116 struct msp_protdesc *protdesc, 117 enum msp_data_size data_size) 118 { 119 u32 temp_reg = 0; 120 121 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode); 122 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode); 123 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1); 124 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2); 125 if (msp->def_elem_len) { 126 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1); 127 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2); 128 } else { 129 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); 130 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); 131 } 132 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay); 133 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order); 134 temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol); 135 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap); 136 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode); 137 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); 138 139 writel(temp_reg, msp->registers + MSP_TCF); 140 } 141 142 static void set_prot_desc_rx(struct ux500_msp *msp, 143 struct msp_protdesc *protdesc, 144 enum msp_data_size data_size) 145 { 146 u32 temp_reg = 0; 147 148 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode); 149 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode); 150 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1); 151 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2); 152 if (msp->def_elem_len) { 153 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1); 154 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2); 155 } else { 156 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); 157 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); 158 } 159 160 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay); 161 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order); 162 temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol); 163 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap); 164 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode); 165 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); 166 167 writel(temp_reg, msp->registers + MSP_RCF); 168 } 169 170 static int configure_protocol(struct ux500_msp *msp, 171 struct ux500_msp_config *config) 172 { 173 struct msp_protdesc *protdesc; 174 enum msp_data_size data_size; 175 u32 temp_reg = 0; 176 177 data_size = config->data_size; 178 msp->def_elem_len = config->def_elem_len; 179 if (config->default_protdesc == 1) { 180 if (config->protocol >= MSP_INVALID_PROTOCOL) { 181 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n", 182 __func__); 183 return -EINVAL; 184 } 185 protdesc = 186 (struct msp_protdesc *)&prot_descs[config->protocol]; 187 } else { 188 protdesc = (struct msp_protdesc *)&config->protdesc; 189 } 190 191 if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) { 192 dev_err(msp->dev, 193 "%s: ERROR: Invalid data-size requested (data_size = %d)!\n", 194 __func__, data_size); 195 return -EINVAL; 196 } 197 198 if (config->direction & MSP_DIR_TX) 199 set_prot_desc_tx(msp, protdesc, data_size); 200 if (config->direction & MSP_DIR_RX) 201 set_prot_desc_rx(msp, protdesc, data_size); 202 203 /* The code below should not be separated. */ 204 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; 205 temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol); 206 writel(temp_reg, msp->registers + MSP_GCR); 207 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; 208 temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol); 209 writel(temp_reg, msp->registers + MSP_GCR); 210 211 return 0; 212 } 213 214 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config) 215 { 216 u32 reg_val_GCR; 217 u32 frame_per = 0; 218 u32 sck_div = 0; 219 u32 frame_width = 0; 220 u32 temp_reg = 0; 221 struct msp_protdesc *protdesc = NULL; 222 223 reg_val_GCR = readl(msp->registers + MSP_GCR); 224 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); 225 226 if (config->default_protdesc) 227 protdesc = 228 (struct msp_protdesc *)&prot_descs[config->protocol]; 229 else 230 protdesc = (struct msp_protdesc *)&config->protdesc; 231 232 switch (config->protocol) { 233 case MSP_PCM_PROTOCOL: 234 case MSP_PCM_COMPAND_PROTOCOL: 235 frame_width = protdesc->frame_width; 236 sck_div = config->f_inputclk / (config->frame_freq * 237 (protdesc->clocks_per_frame)); 238 frame_per = protdesc->frame_period; 239 break; 240 case MSP_I2S_PROTOCOL: 241 frame_width = protdesc->frame_width; 242 sck_div = config->f_inputclk / (config->frame_freq * 243 (protdesc->clocks_per_frame)); 244 frame_per = protdesc->frame_period; 245 break; 246 default: 247 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n", 248 __func__, 249 config->protocol); 250 return -EINVAL; 251 } 252 253 temp_reg = (sck_div - 1) & SCK_DIV_MASK; 254 temp_reg |= FRAME_WIDTH_BITS(frame_width); 255 temp_reg |= FRAME_PERIOD_BITS(frame_per); 256 writel(temp_reg, msp->registers + MSP_SRG); 257 258 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1); 259 260 /* Enable bit-clock */ 261 udelay(100); 262 reg_val_GCR = readl(msp->registers + MSP_GCR); 263 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); 264 udelay(100); 265 266 return 0; 267 } 268 269 static int configure_multichannel(struct ux500_msp *msp, 270 struct ux500_msp_config *config) 271 { 272 struct msp_protdesc *protdesc; 273 struct msp_multichannel_config *mcfg; 274 u32 reg_val_MCR; 275 276 if (config->default_protdesc == 1) { 277 if (config->protocol >= MSP_INVALID_PROTOCOL) { 278 dev_err(msp->dev, 279 "%s: ERROR: Invalid protocol (%d)!\n", 280 __func__, config->protocol); 281 return -EINVAL; 282 } 283 protdesc = (struct msp_protdesc *) 284 &prot_descs[config->protocol]; 285 } else { 286 protdesc = (struct msp_protdesc *)&config->protdesc; 287 } 288 289 mcfg = &config->multichannel_config; 290 if (mcfg->tx_multichannel_enable) { 291 if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) { 292 reg_val_MCR = readl(msp->registers + MSP_MCR); 293 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? 294 1 << TMCEN_BIT : 0), 295 msp->registers + MSP_MCR); 296 writel(mcfg->tx_channel_0_enable, 297 msp->registers + MSP_TCE0); 298 writel(mcfg->tx_channel_1_enable, 299 msp->registers + MSP_TCE1); 300 writel(mcfg->tx_channel_2_enable, 301 msp->registers + MSP_TCE2); 302 writel(mcfg->tx_channel_3_enable, 303 msp->registers + MSP_TCE3); 304 } else { 305 dev_err(msp->dev, 306 "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n", 307 __func__, protdesc->tx_phase_mode); 308 return -EINVAL; 309 } 310 } 311 if (mcfg->rx_multichannel_enable) { 312 if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) { 313 reg_val_MCR = readl(msp->registers + MSP_MCR); 314 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? 315 1 << RMCEN_BIT : 0), 316 msp->registers + MSP_MCR); 317 writel(mcfg->rx_channel_0_enable, 318 msp->registers + MSP_RCE0); 319 writel(mcfg->rx_channel_1_enable, 320 msp->registers + MSP_RCE1); 321 writel(mcfg->rx_channel_2_enable, 322 msp->registers + MSP_RCE2); 323 writel(mcfg->rx_channel_3_enable, 324 msp->registers + MSP_RCE3); 325 } else { 326 dev_err(msp->dev, 327 "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n", 328 __func__, protdesc->rx_phase_mode); 329 return -EINVAL; 330 } 331 if (mcfg->rx_comparison_enable_mode) { 332 reg_val_MCR = readl(msp->registers + MSP_MCR); 333 writel(reg_val_MCR | 334 (mcfg->rx_comparison_enable_mode << RCMPM_BIT), 335 msp->registers + MSP_MCR); 336 337 writel(mcfg->comparison_mask, 338 msp->registers + MSP_RCM); 339 writel(mcfg->comparison_value, 340 msp->registers + MSP_RCV); 341 342 } 343 } 344 345 return 0; 346 } 347 348 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) 349 { 350 int status = 0; 351 u32 reg_val_DMACR, reg_val_GCR; 352 353 /* Configure msp with protocol dependent settings */ 354 configure_protocol(msp, config); 355 setup_bitclk(msp, config); 356 if (config->multichannel_configured == 1) { 357 status = configure_multichannel(msp, config); 358 if (status) 359 dev_warn(msp->dev, 360 "%s: WARN: configure_multichannel failed (%d)!\n", 361 __func__, status); 362 } 363 364 /* Make sure the correct DMA-directions are configured */ 365 if ((config->direction & MSP_DIR_RX) && 366 !msp->capture_dma_data.dma_cfg) { 367 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!", 368 __func__); 369 return -EINVAL; 370 } 371 if ((config->direction == MSP_DIR_TX) && 372 !msp->playback_dma_data.dma_cfg) { 373 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!", 374 __func__); 375 return -EINVAL; 376 } 377 378 reg_val_DMACR = readl(msp->registers + MSP_DMACR); 379 if (config->direction & MSP_DIR_RX) 380 reg_val_DMACR |= RX_DMA_ENABLE; 381 if (config->direction & MSP_DIR_TX) 382 reg_val_DMACR |= TX_DMA_ENABLE; 383 writel(reg_val_DMACR, msp->registers + MSP_DMACR); 384 385 writel(config->iodelay, msp->registers + MSP_IODLY); 386 387 /* Enable frame generation logic */ 388 reg_val_GCR = readl(msp->registers + MSP_GCR); 389 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); 390 391 return status; 392 } 393 394 static void flush_fifo_rx(struct ux500_msp *msp) 395 { 396 u32 reg_val_GCR, reg_val_FLR; 397 u32 limit = 32; 398 399 reg_val_GCR = readl(msp->registers + MSP_GCR); 400 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); 401 402 reg_val_FLR = readl(msp->registers + MSP_FLR); 403 while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) { 404 readl(msp->registers + MSP_DR); 405 reg_val_FLR = readl(msp->registers + MSP_FLR); 406 } 407 408 writel(reg_val_GCR, msp->registers + MSP_GCR); 409 } 410 411 static void flush_fifo_tx(struct ux500_msp *msp) 412 { 413 u32 reg_val_GCR, reg_val_FLR; 414 u32 limit = 32; 415 416 reg_val_GCR = readl(msp->registers + MSP_GCR); 417 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); 418 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); 419 420 reg_val_FLR = readl(msp->registers + MSP_FLR); 421 while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) { 422 readl(msp->registers + MSP_TSTDR); 423 reg_val_FLR = readl(msp->registers + MSP_FLR); 424 } 425 writel(0x0, msp->registers + MSP_ITCR); 426 writel(reg_val_GCR, msp->registers + MSP_GCR); 427 } 428 429 int ux500_msp_i2s_open(struct ux500_msp *msp, 430 struct ux500_msp_config *config) 431 { 432 u32 old_reg, new_reg, mask; 433 int res; 434 unsigned int tx_sel, rx_sel, tx_busy, rx_busy; 435 436 if (in_interrupt()) { 437 dev_err(msp->dev, 438 "%s: ERROR: Open called in interrupt context!\n", 439 __func__); 440 return -1; 441 } 442 443 tx_sel = (config->direction & MSP_DIR_TX) > 0; 444 rx_sel = (config->direction & MSP_DIR_RX) > 0; 445 if (!tx_sel && !rx_sel) { 446 dev_err(msp->dev, "%s: Error: No direction selected!\n", 447 __func__); 448 return -EINVAL; 449 } 450 451 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0; 452 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0; 453 if (tx_busy && tx_sel) { 454 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__); 455 return -EBUSY; 456 } 457 if (rx_busy && rx_sel) { 458 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__); 459 return -EBUSY; 460 } 461 462 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0); 463 464 /* First do the global config register */ 465 mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK | 466 TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK | 467 RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK | 468 LOOPBACK_MASK | TX_EXTRA_DELAY_MASK; 469 470 new_reg = (config->tx_clk_sel | config->rx_clk_sel | 471 config->rx_fsync_pol | config->tx_fsync_pol | 472 config->rx_fsync_sel | config->tx_fsync_sel | 473 config->rx_fifo_config | config->tx_fifo_config | 474 config->srg_clk_sel | config->loopback_enable | 475 config->tx_data_enable); 476 477 old_reg = readl(msp->registers + MSP_GCR); 478 old_reg &= ~mask; 479 new_reg |= old_reg; 480 writel(new_reg, msp->registers + MSP_GCR); 481 482 res = enable_msp(msp, config); 483 if (res < 0) { 484 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n", 485 __func__, res); 486 return -EBUSY; 487 } 488 if (config->loopback_enable & 0x80) 489 msp->loopback_enable = 1; 490 491 /* Flush FIFOs */ 492 flush_fifo_tx(msp); 493 flush_fifo_rx(msp); 494 495 msp->msp_state = MSP_STATE_CONFIGURED; 496 return 0; 497 } 498 499 static void disable_msp_rx(struct ux500_msp *msp) 500 { 501 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; 502 503 reg_val_GCR = readl(msp->registers + MSP_GCR); 504 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); 505 reg_val_DMACR = readl(msp->registers + MSP_DMACR); 506 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); 507 reg_val_IMSC = readl(msp->registers + MSP_IMSC); 508 writel(reg_val_IMSC & 509 ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT), 510 msp->registers + MSP_IMSC); 511 512 msp->dir_busy &= ~MSP_DIR_RX; 513 } 514 515 static void disable_msp_tx(struct ux500_msp *msp) 516 { 517 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; 518 519 reg_val_GCR = readl(msp->registers + MSP_GCR); 520 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); 521 reg_val_DMACR = readl(msp->registers + MSP_DMACR); 522 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); 523 reg_val_IMSC = readl(msp->registers + MSP_IMSC); 524 writel(reg_val_IMSC & 525 ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT), 526 msp->registers + MSP_IMSC); 527 528 msp->dir_busy &= ~MSP_DIR_TX; 529 } 530 531 static int disable_msp(struct ux500_msp *msp, unsigned int dir) 532 { 533 u32 reg_val_GCR; 534 unsigned int disable_tx, disable_rx; 535 536 reg_val_GCR = readl(msp->registers + MSP_GCR); 537 disable_tx = dir & MSP_DIR_TX; 538 disable_rx = dir & MSP_DIR_TX; 539 if (disable_tx && disable_rx) { 540 reg_val_GCR = readl(msp->registers + MSP_GCR); 541 writel(reg_val_GCR | LOOPBACK_MASK, 542 msp->registers + MSP_GCR); 543 544 /* Flush TX-FIFO */ 545 flush_fifo_tx(msp); 546 547 /* Disable TX-channel */ 548 writel((readl(msp->registers + MSP_GCR) & 549 (~TX_ENABLE)), msp->registers + MSP_GCR); 550 551 /* Flush RX-FIFO */ 552 flush_fifo_rx(msp); 553 554 /* Disable Loopback and Receive channel */ 555 writel((readl(msp->registers + MSP_GCR) & 556 (~(RX_ENABLE | LOOPBACK_MASK))), 557 msp->registers + MSP_GCR); 558 559 disable_msp_tx(msp); 560 disable_msp_rx(msp); 561 } else if (disable_tx) 562 disable_msp_tx(msp); 563 else if (disable_rx) 564 disable_msp_rx(msp); 565 566 return 0; 567 } 568 569 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction) 570 { 571 u32 reg_val_GCR, enable_bit; 572 573 if (msp->msp_state == MSP_STATE_IDLE) { 574 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n", 575 __func__); 576 return -EINVAL; 577 } 578 579 switch (cmd) { 580 case SNDRV_PCM_TRIGGER_START: 581 case SNDRV_PCM_TRIGGER_RESUME: 582 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 583 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 584 enable_bit = TX_ENABLE; 585 else 586 enable_bit = RX_ENABLE; 587 reg_val_GCR = readl(msp->registers + MSP_GCR); 588 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); 589 break; 590 591 case SNDRV_PCM_TRIGGER_STOP: 592 case SNDRV_PCM_TRIGGER_SUSPEND: 593 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 594 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 595 disable_msp_tx(msp); 596 else 597 disable_msp_rx(msp); 598 break; 599 default: 600 return -EINVAL; 601 } 602 603 return 0; 604 } 605 606 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir) 607 { 608 int status = 0; 609 610 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir); 611 612 status = disable_msp(msp, dir); 613 if (msp->dir_busy == 0) { 614 /* disable sample rate and frame generators */ 615 msp->msp_state = MSP_STATE_IDLE; 616 writel((readl(msp->registers + MSP_GCR) & 617 (~(FRAME_GEN_ENABLE | SRG_ENABLE))), 618 msp->registers + MSP_GCR); 619 620 writel(0, msp->registers + MSP_GCR); 621 writel(0, msp->registers + MSP_TCF); 622 writel(0, msp->registers + MSP_RCF); 623 writel(0, msp->registers + MSP_DMACR); 624 writel(0, msp->registers + MSP_SRG); 625 writel(0, msp->registers + MSP_MCR); 626 writel(0, msp->registers + MSP_RCM); 627 writel(0, msp->registers + MSP_RCV); 628 writel(0, msp->registers + MSP_TCE0); 629 writel(0, msp->registers + MSP_TCE1); 630 writel(0, msp->registers + MSP_TCE2); 631 writel(0, msp->registers + MSP_TCE3); 632 writel(0, msp->registers + MSP_RCE0); 633 writel(0, msp->registers + MSP_RCE1); 634 writel(0, msp->registers + MSP_RCE2); 635 writel(0, msp->registers + MSP_RCE3); 636 } 637 638 return status; 639 640 } 641 642 static int ux500_msp_i2s_of_init_msp(struct platform_device *pdev, 643 struct ux500_msp *msp, 644 struct msp_i2s_platform_data **platform_data) 645 { 646 struct msp_i2s_platform_data *pdata; 647 648 *platform_data = devm_kzalloc(&pdev->dev, 649 sizeof(struct msp_i2s_platform_data), 650 GFP_KERNEL); 651 pdata = *platform_data; 652 if (!pdata) 653 return -ENOMEM; 654 655 msp->playback_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, 656 sizeof(struct stedma40_chan_cfg), 657 GFP_KERNEL); 658 if (!msp->playback_dma_data.dma_cfg) 659 return -ENOMEM; 660 661 msp->capture_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, 662 sizeof(struct stedma40_chan_cfg), 663 GFP_KERNEL); 664 if (!msp->capture_dma_data.dma_cfg) 665 return -ENOMEM; 666 667 return 0; 668 } 669 670 int ux500_msp_i2s_init_msp(struct platform_device *pdev, 671 struct ux500_msp **msp_p, 672 struct msp_i2s_platform_data *platform_data) 673 { 674 struct resource *res = NULL; 675 struct device_node *np = pdev->dev.of_node; 676 struct ux500_msp *msp; 677 int ret; 678 679 *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL); 680 msp = *msp_p; 681 if (!msp) 682 return -ENOMEM; 683 684 if (!platform_data) { 685 if (np) { 686 ret = ux500_msp_i2s_of_init_msp(pdev, msp, 687 &platform_data); 688 if (ret) 689 return ret; 690 } else 691 return -EINVAL; 692 } else { 693 msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx; 694 msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx; 695 msp->id = platform_data->id; 696 } 697 698 msp->dev = &pdev->dev; 699 700 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 701 if (res == NULL) { 702 dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n", 703 __func__); 704 return -ENOMEM; 705 } 706 707 msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR; 708 msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR; 709 710 msp->registers = devm_ioremap(&pdev->dev, res->start, 711 resource_size(res)); 712 if (msp->registers == NULL) { 713 dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__); 714 return -ENOMEM; 715 } 716 717 msp->msp_state = MSP_STATE_IDLE; 718 msp->loopback_enable = 0; 719 720 return 0; 721 } 722 723 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, 724 struct ux500_msp *msp) 725 { 726 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id); 727 } 728 729 MODULE_LICENSE("GPL v2"); 730