xref: /openbmc/linux/sound/soc/ux500/ux500_msp_dai.h (revision 8466579b)
1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
23592b7f6SOla Lilja /*
33592b7f6SOla Lilja  * Copyright (C) ST-Ericsson SA 2012
43592b7f6SOla Lilja  *
53592b7f6SOla Lilja  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
63592b7f6SOla Lilja  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
73592b7f6SOla Lilja  *         for ST-Ericsson.
83592b7f6SOla Lilja  */
93592b7f6SOla Lilja 
103592b7f6SOla Lilja #ifndef UX500_msp_dai_H
113592b7f6SOla Lilja #define UX500_msp_dai_H
123592b7f6SOla Lilja 
133592b7f6SOla Lilja #include <linux/types.h>
143592b7f6SOla Lilja #include <linux/spinlock.h>
153592b7f6SOla Lilja 
163592b7f6SOla Lilja #include "ux500_msp_i2s.h"
173592b7f6SOla Lilja 
183592b7f6SOla Lilja #define UX500_NBR_OF_DAI	4
193592b7f6SOla Lilja 
203592b7f6SOla Lilja #define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |	\
213592b7f6SOla Lilja 			SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
223592b7f6SOla Lilja 
233592b7f6SOla Lilja #define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
243592b7f6SOla Lilja 
253592b7f6SOla Lilja #define FRAME_PER_SINGLE_SLOT_8_KHZ		31
263592b7f6SOla Lilja #define FRAME_PER_SINGLE_SLOT_16_KHZ	124
273592b7f6SOla Lilja #define FRAME_PER_SINGLE_SLOT_44_1_KHZ	63
283592b7f6SOla Lilja #define FRAME_PER_SINGLE_SLOT_48_KHZ	49
293592b7f6SOla Lilja #define FRAME_PER_2_SLOTS				31
303592b7f6SOla Lilja #define FRAME_PER_8_SLOTS				138
313592b7f6SOla Lilja #define FRAME_PER_16_SLOTS				277
323592b7f6SOla Lilja 
333592b7f6SOla Lilja #define UX500_MSP_INTERNAL_CLOCK_FREQ  40000000
343592b7f6SOla Lilja #define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
353592b7f6SOla Lilja 
363592b7f6SOla Lilja #define UX500_MSP_MIN_CHANNELS		1
373592b7f6SOla Lilja #define UX500_MSP_MAX_CHANNELS		8
383592b7f6SOla Lilja 
393592b7f6SOla Lilja #define PLAYBACK_CONFIGURED		1
403592b7f6SOla Lilja #define CAPTURE_CONFIGURED		2
413592b7f6SOla Lilja 
423592b7f6SOla Lilja enum ux500_msp_clock_id {
433592b7f6SOla Lilja 	UX500_MSP_MASTER_CLOCK,
443592b7f6SOla Lilja };
453592b7f6SOla Lilja 
463592b7f6SOla Lilja struct ux500_msp_i2s_drvdata {
473592b7f6SOla Lilja 	struct ux500_msp *msp;
483592b7f6SOla Lilja 	struct regulator *reg_vape;
493592b7f6SOla Lilja 	unsigned int fmt;
503592b7f6SOla Lilja 	unsigned int tx_mask;
513592b7f6SOla Lilja 	unsigned int rx_mask;
523592b7f6SOla Lilja 	int slots;
533592b7f6SOla Lilja 	int slot_width;
543592b7f6SOla Lilja 
553592b7f6SOla Lilja 	/* Clocks */
563592b7f6SOla Lilja 	unsigned int master_clk;
573592b7f6SOla Lilja 	struct clk *clk;
58f61ab093SUlf Hansson 	struct clk *pclk;
593592b7f6SOla Lilja 
603592b7f6SOla Lilja 	/* Regulators */
613592b7f6SOla Lilja 	int vape_opp_constraint;
623592b7f6SOla Lilja };
633592b7f6SOla Lilja 
643592b7f6SOla Lilja int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
653592b7f6SOla Lilja 
663592b7f6SOla Lilja #endif
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