1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> 8 * Peter Ujfalusi <peter.ujfalusi@ti.com> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/initval.h> 21 #include <sound/soc.h> 22 #include <sound/dmaengine_pcm.h> 23 24 #include "omap-mcbsp-priv.h" 25 #include "omap-mcbsp.h" 26 #include "sdma-pcm.h" 27 28 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) 29 30 enum { 31 OMAP_MCBSP_WORD_8 = 0, 32 OMAP_MCBSP_WORD_12, 33 OMAP_MCBSP_WORD_16, 34 OMAP_MCBSP_WORD_20, 35 OMAP_MCBSP_WORD_24, 36 OMAP_MCBSP_WORD_32, 37 }; 38 39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp) 40 { 41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); 42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); 43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); 44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); 45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); 46 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2)); 47 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1)); 48 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2)); 49 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1)); 50 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2)); 51 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1)); 52 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2)); 53 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1)); 54 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0)); 55 dev_dbg(mcbsp->dev, "***********************\n"); 56 } 57 58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id) 59 { 60 struct clk *fck_src; 61 const char *src; 62 int r; 63 64 if (fck_src_id == MCBSP_CLKS_PAD_SRC) 65 src = "pad_fck"; 66 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) 67 src = "prcm_fck"; 68 else 69 return -EINVAL; 70 71 fck_src = clk_get(mcbsp->dev, src); 72 if (IS_ERR(fck_src)) { 73 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src); 74 return -EINVAL; 75 } 76 77 pm_runtime_put_sync(mcbsp->dev); 78 79 r = clk_set_parent(mcbsp->fclk, fck_src); 80 if (r) { 81 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n", 82 src); 83 clk_put(fck_src); 84 return r; 85 } 86 87 pm_runtime_get_sync(mcbsp->dev); 88 89 clk_put(fck_src); 90 91 return 0; 92 } 93 94 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data) 95 { 96 struct omap_mcbsp *mcbsp = data; 97 u16 irqst; 98 99 irqst = MCBSP_READ(mcbsp, IRQST); 100 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst); 101 102 if (irqst & RSYNCERREN) 103 dev_err(mcbsp->dev, "RX Frame Sync Error!\n"); 104 if (irqst & RFSREN) 105 dev_dbg(mcbsp->dev, "RX Frame Sync\n"); 106 if (irqst & REOFEN) 107 dev_dbg(mcbsp->dev, "RX End Of Frame\n"); 108 if (irqst & RRDYEN) 109 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n"); 110 if (irqst & RUNDFLEN) 111 dev_err(mcbsp->dev, "RX Buffer Underflow!\n"); 112 if (irqst & ROVFLEN) 113 dev_err(mcbsp->dev, "RX Buffer Overflow!\n"); 114 115 if (irqst & XSYNCERREN) 116 dev_err(mcbsp->dev, "TX Frame Sync Error!\n"); 117 if (irqst & XFSXEN) 118 dev_dbg(mcbsp->dev, "TX Frame Sync\n"); 119 if (irqst & XEOFEN) 120 dev_dbg(mcbsp->dev, "TX End Of Frame\n"); 121 if (irqst & XRDYEN) 122 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n"); 123 if (irqst & XUNDFLEN) 124 dev_err(mcbsp->dev, "TX Buffer Underflow!\n"); 125 if (irqst & XOVFLEN) 126 dev_err(mcbsp->dev, "TX Buffer Overflow!\n"); 127 if (irqst & XEMPTYEOFEN) 128 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n"); 129 130 MCBSP_WRITE(mcbsp, IRQST, irqst); 131 132 return IRQ_HANDLED; 133 } 134 135 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data) 136 { 137 struct omap_mcbsp *mcbsp = data; 138 u16 irqst_spcr2; 139 140 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2); 141 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); 142 143 if (irqst_spcr2 & XSYNC_ERR) { 144 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n", 145 irqst_spcr2); 146 /* Writing zero to XSYNC_ERR clears the IRQ */ 147 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2)); 148 } 149 150 return IRQ_HANDLED; 151 } 152 153 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data) 154 { 155 struct omap_mcbsp *mcbsp = data; 156 u16 irqst_spcr1; 157 158 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1); 159 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); 160 161 if (irqst_spcr1 & RSYNC_ERR) { 162 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n", 163 irqst_spcr1); 164 /* Writing zero to RSYNC_ERR clears the IRQ */ 165 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1)); 166 } 167 168 return IRQ_HANDLED; 169 } 170 171 /* 172 * omap_mcbsp_config simply write a config to the 173 * appropriate McBSP. 174 * You either call this function or set the McBSP registers 175 * by yourself before calling omap_mcbsp_start(). 176 */ 177 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp, 178 const struct omap_mcbsp_reg_cfg *config) 179 { 180 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", 181 mcbsp->id, mcbsp->phys_base); 182 183 /* We write the given config */ 184 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); 185 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); 186 MCBSP_WRITE(mcbsp, RCR2, config->rcr2); 187 MCBSP_WRITE(mcbsp, RCR1, config->rcr1); 188 MCBSP_WRITE(mcbsp, XCR2, config->xcr2); 189 MCBSP_WRITE(mcbsp, XCR1, config->xcr1); 190 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); 191 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); 192 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 193 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 194 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 195 if (mcbsp->pdata->has_ccr) { 196 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 197 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 198 } 199 /* Enable wakeup behavior */ 200 if (mcbsp->pdata->has_wakeup) 201 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); 202 203 /* Enable TX/RX sync error interrupts by default */ 204 if (mcbsp->irq) 205 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN | 206 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN); 207 } 208 209 /** 210 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register 211 * @mcbsp: omap_mcbsp struct for the McBSP instance 212 * @stream: Stream direction (playback/capture) 213 * 214 * Returns the address of mcbsp data transmit register or data receive register 215 * to be used by DMA for transferring/receiving data 216 */ 217 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp, 218 unsigned int stream) 219 { 220 int data_reg; 221 222 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 223 if (mcbsp->pdata->reg_size == 2) 224 data_reg = OMAP_MCBSP_REG_DXR1; 225 else 226 data_reg = OMAP_MCBSP_REG_DXR; 227 } else { 228 if (mcbsp->pdata->reg_size == 2) 229 data_reg = OMAP_MCBSP_REG_DRR1; 230 else 231 data_reg = OMAP_MCBSP_REG_DRR; 232 } 233 234 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step; 235 } 236 237 /* 238 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. 239 * The threshold parameter is 1 based, and it is converted (threshold - 1) 240 * for the THRSH2 register. 241 */ 242 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 243 { 244 if (threshold && threshold <= mcbsp->max_tx_thres) 245 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); 246 } 247 248 /* 249 * omap_mcbsp_set_rx_threshold configures the receive threshold in words. 250 * The threshold parameter is 1 based, and it is converted (threshold - 1) 251 * for the THRSH1 register. 252 */ 253 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 254 { 255 if (threshold && threshold <= mcbsp->max_rx_thres) 256 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); 257 } 258 259 /* 260 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO 261 */ 262 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp) 263 { 264 u16 buffstat; 265 266 /* Returns the number of free locations in the buffer */ 267 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); 268 269 /* Number of slots are different in McBSP ports */ 270 return mcbsp->pdata->buffer_size - buffstat; 271 } 272 273 /* 274 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO 275 * to reach the threshold value (when the DMA will be triggered to read it) 276 */ 277 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp) 278 { 279 u16 buffstat, threshold; 280 281 /* Returns the number of used locations in the buffer */ 282 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); 283 /* RX threshold */ 284 threshold = MCBSP_READ(mcbsp, THRSH1); 285 286 /* Return the number of location till we reach the threshold limit */ 287 if (threshold <= buffstat) 288 return 0; 289 else 290 return threshold - buffstat; 291 } 292 293 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp) 294 { 295 void *reg_cache; 296 int err; 297 298 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL); 299 if (!reg_cache) 300 return -ENOMEM; 301 302 spin_lock(&mcbsp->lock); 303 if (!mcbsp->free) { 304 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id); 305 err = -EBUSY; 306 goto err_kfree; 307 } 308 309 mcbsp->free = false; 310 mcbsp->reg_cache = reg_cache; 311 spin_unlock(&mcbsp->lock); 312 313 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request) 314 mcbsp->pdata->ops->request(mcbsp->id - 1); 315 316 /* 317 * Make sure that transmitter, receiver and sample-rate generator are 318 * not running before activating IRQs. 319 */ 320 MCBSP_WRITE(mcbsp, SPCR1, 0); 321 MCBSP_WRITE(mcbsp, SPCR2, 0); 322 323 if (mcbsp->irq) { 324 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0, 325 "McBSP", (void *)mcbsp); 326 if (err != 0) { 327 dev_err(mcbsp->dev, "Unable to request IRQ\n"); 328 goto err_clk_disable; 329 } 330 } else { 331 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0, 332 "McBSP TX", (void *)mcbsp); 333 if (err != 0) { 334 dev_err(mcbsp->dev, "Unable to request TX IRQ\n"); 335 goto err_clk_disable; 336 } 337 338 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0, 339 "McBSP RX", (void *)mcbsp); 340 if (err != 0) { 341 dev_err(mcbsp->dev, "Unable to request RX IRQ\n"); 342 goto err_free_irq; 343 } 344 } 345 346 return 0; 347 err_free_irq: 348 free_irq(mcbsp->tx_irq, (void *)mcbsp); 349 err_clk_disable: 350 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 351 mcbsp->pdata->ops->free(mcbsp->id - 1); 352 353 /* Disable wakeup behavior */ 354 if (mcbsp->pdata->has_wakeup) 355 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 356 357 spin_lock(&mcbsp->lock); 358 mcbsp->free = true; 359 mcbsp->reg_cache = NULL; 360 err_kfree: 361 spin_unlock(&mcbsp->lock); 362 kfree(reg_cache); 363 364 return err; 365 } 366 367 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp) 368 { 369 void *reg_cache; 370 371 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 372 mcbsp->pdata->ops->free(mcbsp->id - 1); 373 374 /* Disable wakeup behavior */ 375 if (mcbsp->pdata->has_wakeup) 376 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 377 378 /* Disable interrupt requests */ 379 if (mcbsp->irq) 380 MCBSP_WRITE(mcbsp, IRQEN, 0); 381 382 if (mcbsp->irq) { 383 free_irq(mcbsp->irq, (void *)mcbsp); 384 } else { 385 free_irq(mcbsp->rx_irq, (void *)mcbsp); 386 free_irq(mcbsp->tx_irq, (void *)mcbsp); 387 } 388 389 reg_cache = mcbsp->reg_cache; 390 391 /* 392 * Select CLKS source from internal source unconditionally before 393 * marking the McBSP port as free. 394 * If the external clock source via MCBSP_CLKS pin has been selected the 395 * system will refuse to enter idle if the CLKS pin source is not reset 396 * back to internal source. 397 */ 398 if (!mcbsp_omap1()) 399 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC); 400 401 spin_lock(&mcbsp->lock); 402 if (mcbsp->free) 403 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); 404 else 405 mcbsp->free = true; 406 mcbsp->reg_cache = NULL; 407 spin_unlock(&mcbsp->lock); 408 409 kfree(reg_cache); 410 } 411 412 /* 413 * Here we start the McBSP, by enabling transmitter, receiver or both. 414 * If no transmitter or receiver is active prior calling, then sample-rate 415 * generator and frame sync are started. 416 */ 417 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream) 418 { 419 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 420 int rx = !tx; 421 int enable_srg = 0; 422 u16 w; 423 424 if (mcbsp->st_data) 425 omap_mcbsp_st_start(mcbsp); 426 427 /* Only enable SRG, if McBSP is master */ 428 w = MCBSP_READ_CACHE(mcbsp, PCR0); 429 if (w & (FSXM | FSRM | CLKXM | CLKRM)) 430 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 431 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 432 433 if (enable_srg) { 434 /* Start the sample generator */ 435 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 436 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); 437 } 438 439 /* Enable transmitter and receiver */ 440 tx &= 1; 441 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 442 MCBSP_WRITE(mcbsp, SPCR2, w | tx); 443 444 rx &= 1; 445 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 446 MCBSP_WRITE(mcbsp, SPCR1, w | rx); 447 448 /* 449 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec 450 * REVISIT: 100us may give enough time for two CLKSRG, however 451 * due to some unknown PM related, clock gating etc. reason it 452 * is now at 500us. 453 */ 454 udelay(500); 455 456 if (enable_srg) { 457 /* Start frame sync */ 458 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 459 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 460 } 461 462 if (mcbsp->pdata->has_ccr) { 463 /* Release the transmitter and receiver */ 464 w = MCBSP_READ_CACHE(mcbsp, XCCR); 465 w &= ~(tx ? XDISABLE : 0); 466 MCBSP_WRITE(mcbsp, XCCR, w); 467 w = MCBSP_READ_CACHE(mcbsp, RCCR); 468 w &= ~(rx ? RDISABLE : 0); 469 MCBSP_WRITE(mcbsp, RCCR, w); 470 } 471 472 /* Dump McBSP Regs */ 473 omap_mcbsp_dump_reg(mcbsp); 474 } 475 476 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream) 477 { 478 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 479 int rx = !tx; 480 int idle; 481 u16 w; 482 483 /* Reset transmitter */ 484 tx &= 1; 485 if (mcbsp->pdata->has_ccr) { 486 w = MCBSP_READ_CACHE(mcbsp, XCCR); 487 w |= (tx ? XDISABLE : 0); 488 MCBSP_WRITE(mcbsp, XCCR, w); 489 } 490 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 491 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); 492 493 /* Reset receiver */ 494 rx &= 1; 495 if (mcbsp->pdata->has_ccr) { 496 w = MCBSP_READ_CACHE(mcbsp, RCCR); 497 w |= (rx ? RDISABLE : 0); 498 MCBSP_WRITE(mcbsp, RCCR, w); 499 } 500 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 501 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); 502 503 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 504 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 505 506 if (idle) { 507 /* Reset the sample rate generator */ 508 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 509 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); 510 } 511 512 if (mcbsp->st_data) 513 omap_mcbsp_st_stop(mcbsp); 514 } 515 516 #define max_thres(m) (mcbsp->pdata->buffer_size) 517 #define valid_threshold(m, val) ((val) <= max_thres(m)) 518 #define THRESHOLD_PROP_BUILDER(prop) \ 519 static ssize_t prop##_show(struct device *dev, \ 520 struct device_attribute *attr, char *buf) \ 521 { \ 522 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 523 \ 524 return sprintf(buf, "%u\n", mcbsp->prop); \ 525 } \ 526 \ 527 static ssize_t prop##_store(struct device *dev, \ 528 struct device_attribute *attr, \ 529 const char *buf, size_t size) \ 530 { \ 531 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 532 unsigned long val; \ 533 int status; \ 534 \ 535 status = kstrtoul(buf, 0, &val); \ 536 if (status) \ 537 return status; \ 538 \ 539 if (!valid_threshold(mcbsp, val)) \ 540 return -EDOM; \ 541 \ 542 mcbsp->prop = val; \ 543 return size; \ 544 } \ 545 \ 546 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store) 547 548 THRESHOLD_PROP_BUILDER(max_tx_thres); 549 THRESHOLD_PROP_BUILDER(max_rx_thres); 550 551 static const char * const dma_op_modes[] = { 552 "element", "threshold", 553 }; 554 555 static ssize_t dma_op_mode_show(struct device *dev, 556 struct device_attribute *attr, char *buf) 557 { 558 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 559 int dma_op_mode, i = 0; 560 ssize_t len = 0; 561 const char * const *s; 562 563 dma_op_mode = mcbsp->dma_op_mode; 564 565 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) { 566 if (dma_op_mode == i) 567 len += sprintf(buf + len, "[%s] ", *s); 568 else 569 len += sprintf(buf + len, "%s ", *s); 570 } 571 len += sprintf(buf + len, "\n"); 572 573 return len; 574 } 575 576 static ssize_t dma_op_mode_store(struct device *dev, 577 struct device_attribute *attr, const char *buf, 578 size_t size) 579 { 580 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 581 int i; 582 583 i = sysfs_match_string(dma_op_modes, buf); 584 if (i < 0) 585 return i; 586 587 spin_lock_irq(&mcbsp->lock); 588 if (!mcbsp->free) { 589 size = -EBUSY; 590 goto unlock; 591 } 592 mcbsp->dma_op_mode = i; 593 594 unlock: 595 spin_unlock_irq(&mcbsp->lock); 596 597 return size; 598 } 599 600 static DEVICE_ATTR_RW(dma_op_mode); 601 602 static const struct attribute *additional_attrs[] = { 603 &dev_attr_max_tx_thres.attr, 604 &dev_attr_max_rx_thres.attr, 605 &dev_attr_dma_op_mode.attr, 606 NULL, 607 }; 608 609 static const struct attribute_group additional_attr_group = { 610 .attrs = (struct attribute **)additional_attrs, 611 }; 612 613 /* 614 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 615 * 730 has only 2 McBSP, and both of them are MPU peripherals. 616 */ 617 static int omap_mcbsp_init(struct platform_device *pdev) 618 { 619 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 620 struct resource *res; 621 int ret = 0; 622 623 spin_lock_init(&mcbsp->lock); 624 mcbsp->free = true; 625 626 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 627 if (!res) 628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 629 630 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res); 631 if (IS_ERR(mcbsp->io_base)) 632 return PTR_ERR(mcbsp->io_base); 633 634 mcbsp->phys_base = res->start; 635 mcbsp->reg_cache_size = resource_size(res); 636 637 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 638 if (!res) 639 mcbsp->phys_dma_base = mcbsp->phys_base; 640 else 641 mcbsp->phys_dma_base = res->start; 642 643 /* 644 * OMAP1, 2 uses two interrupt lines: TX, RX 645 * OMAP2430, OMAP3 SoC have combined IRQ line as well. 646 * OMAP4 and newer SoC only have the combined IRQ line. 647 * Use the combined IRQ if available since it gives better debugging 648 * possibilities. 649 */ 650 mcbsp->irq = platform_get_irq_byname(pdev, "common"); 651 if (mcbsp->irq == -ENXIO) { 652 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); 653 654 if (mcbsp->tx_irq == -ENXIO) { 655 mcbsp->irq = platform_get_irq(pdev, 0); 656 mcbsp->tx_irq = 0; 657 } else { 658 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); 659 mcbsp->irq = 0; 660 } 661 } 662 663 if (!pdev->dev.of_node) { 664 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 665 if (!res) { 666 dev_err(&pdev->dev, "invalid tx DMA channel\n"); 667 return -ENODEV; 668 } 669 mcbsp->dma_req[0] = res->start; 670 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0]; 671 672 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 673 if (!res) { 674 dev_err(&pdev->dev, "invalid rx DMA channel\n"); 675 return -ENODEV; 676 } 677 mcbsp->dma_req[1] = res->start; 678 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1]; 679 } else { 680 mcbsp->dma_data[0].filter_data = "tx"; 681 mcbsp->dma_data[1].filter_data = "rx"; 682 } 683 684 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 685 SNDRV_PCM_STREAM_PLAYBACK); 686 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 687 SNDRV_PCM_STREAM_CAPTURE); 688 689 mcbsp->fclk = clk_get(&pdev->dev, "fck"); 690 if (IS_ERR(mcbsp->fclk)) { 691 ret = PTR_ERR(mcbsp->fclk); 692 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret); 693 return ret; 694 } 695 696 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; 697 if (mcbsp->pdata->buffer_size) { 698 /* 699 * Initially configure the maximum thresholds to a safe value. 700 * The McBSP FIFO usage with these values should not go under 701 * 16 locations. 702 * If the whole FIFO without safety buffer is used, than there 703 * is a possibility that the DMA will be not able to push the 704 * new data on time, causing channel shifts in runtime. 705 */ 706 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; 707 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; 708 709 ret = sysfs_create_group(&mcbsp->dev->kobj, 710 &additional_attr_group); 711 if (ret) { 712 dev_err(mcbsp->dev, 713 "Unable to create additional controls\n"); 714 goto err_thres; 715 } 716 } 717 718 ret = omap_mcbsp_st_init(pdev); 719 if (ret) 720 goto err_st; 721 722 return 0; 723 724 err_st: 725 if (mcbsp->pdata->buffer_size) 726 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group); 727 err_thres: 728 clk_put(mcbsp->fclk); 729 return ret; 730 } 731 732 /* 733 * Stream DMA parameters. DMA request line and port address are set runtime 734 * since they are different between OMAP1 and later OMAPs 735 */ 736 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream, 737 unsigned int packet_size) 738 { 739 struct snd_soc_pcm_runtime *rtd = substream->private_data; 740 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 741 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 742 int words; 743 744 /* No need to proceed further if McBSP does not have FIFO */ 745 if (mcbsp->pdata->buffer_size == 0) 746 return; 747 748 /* 749 * Configure McBSP threshold based on either: 750 * packet_size, when the sDMA is in packet mode, or based on the 751 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1 752 * for mono streams. 753 */ 754 if (packet_size) 755 words = packet_size; 756 else 757 words = 1; 758 759 /* Configure McBSP internal buffer usage */ 760 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 761 omap_mcbsp_set_tx_threshold(mcbsp, words); 762 else 763 omap_mcbsp_set_rx_threshold(mcbsp, words); 764 } 765 766 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, 767 struct snd_pcm_hw_rule *rule) 768 { 769 struct snd_interval *buffer_size = hw_param_interval(params, 770 SNDRV_PCM_HW_PARAM_BUFFER_SIZE); 771 struct snd_interval *channels = hw_param_interval(params, 772 SNDRV_PCM_HW_PARAM_CHANNELS); 773 struct omap_mcbsp *mcbsp = rule->private; 774 struct snd_interval frames; 775 int size; 776 777 snd_interval_any(&frames); 778 size = mcbsp->pdata->buffer_size; 779 780 frames.min = size / channels->min; 781 frames.integer = 1; 782 return snd_interval_refine(buffer_size, &frames); 783 } 784 785 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, 786 struct snd_soc_dai *cpu_dai) 787 { 788 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 789 int err = 0; 790 791 if (!cpu_dai->active) 792 err = omap_mcbsp_request(mcbsp); 793 794 /* 795 * OMAP3 McBSP FIFO is word structured. 796 * McBSP2 has 1024 + 256 = 1280 word long buffer, 797 * McBSP1,3,4,5 has 128 word long buffer 798 * This means that the size of the FIFO depends on the sample format. 799 * For example on McBSP3: 800 * 16bit samples: size is 128 * 2 = 256 bytes 801 * 32bit samples: size is 128 * 4 = 512 bytes 802 * It is simpler to place constraint for buffer and period based on 803 * channels. 804 * McBSP3 as example again (16 or 32 bit samples): 805 * 1 channel (mono): size is 128 frames (128 words) 806 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) 807 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) 808 */ 809 if (mcbsp->pdata->buffer_size) { 810 /* 811 * Rule for the buffer size. We should not allow 812 * smaller buffer than the FIFO size to avoid underruns. 813 * This applies only for the playback stream. 814 */ 815 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 816 snd_pcm_hw_rule_add(substream->runtime, 0, 817 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 818 omap_mcbsp_hwrule_min_buffersize, 819 mcbsp, 820 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 821 822 /* Make sure, that the period size is always even */ 823 snd_pcm_hw_constraint_step(substream->runtime, 0, 824 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 825 } 826 827 return err; 828 } 829 830 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, 831 struct snd_soc_dai *cpu_dai) 832 { 833 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 834 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 835 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 836 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 837 838 if (mcbsp->latency[stream2]) 839 pm_qos_update_request(&mcbsp->pm_qos_req, 840 mcbsp->latency[stream2]); 841 else if (mcbsp->latency[stream1]) 842 pm_qos_remove_request(&mcbsp->pm_qos_req); 843 844 mcbsp->latency[stream1] = 0; 845 846 if (!cpu_dai->active) { 847 omap_mcbsp_free(mcbsp); 848 mcbsp->configured = 0; 849 } 850 } 851 852 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream, 853 struct snd_soc_dai *cpu_dai) 854 { 855 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 856 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req; 857 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 858 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 859 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 860 int latency = mcbsp->latency[stream2]; 861 862 /* Prevent omap hardware from hitting off between FIFO fills */ 863 if (!latency || mcbsp->latency[stream1] < latency) 864 latency = mcbsp->latency[stream1]; 865 866 if (pm_qos_request_active(pm_qos_req)) 867 pm_qos_update_request(pm_qos_req, latency); 868 else if (latency) 869 pm_qos_add_request(pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency); 870 871 return 0; 872 } 873 874 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, 875 struct snd_soc_dai *cpu_dai) 876 { 877 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 878 879 switch (cmd) { 880 case SNDRV_PCM_TRIGGER_START: 881 case SNDRV_PCM_TRIGGER_RESUME: 882 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 883 mcbsp->active++; 884 omap_mcbsp_start(mcbsp, substream->stream); 885 break; 886 887 case SNDRV_PCM_TRIGGER_STOP: 888 case SNDRV_PCM_TRIGGER_SUSPEND: 889 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 890 omap_mcbsp_stop(mcbsp, substream->stream); 891 mcbsp->active--; 892 break; 893 default: 894 return -EINVAL; 895 } 896 897 return 0; 898 } 899 900 static snd_pcm_sframes_t omap_mcbsp_dai_delay( 901 struct snd_pcm_substream *substream, 902 struct snd_soc_dai *dai) 903 { 904 struct snd_soc_pcm_runtime *rtd = substream->private_data; 905 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 906 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 907 u16 fifo_use; 908 snd_pcm_sframes_t delay; 909 910 /* No need to proceed further if McBSP does not have FIFO */ 911 if (mcbsp->pdata->buffer_size == 0) 912 return 0; 913 914 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 915 fifo_use = omap_mcbsp_get_tx_delay(mcbsp); 916 else 917 fifo_use = omap_mcbsp_get_rx_delay(mcbsp); 918 919 /* 920 * Divide the used locations with the channel count to get the 921 * FIFO usage in samples (don't care about partial samples in the 922 * buffer). 923 */ 924 delay = fifo_use / substream->runtime->channels; 925 926 return delay; 927 } 928 929 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 930 struct snd_pcm_hw_params *params, 931 struct snd_soc_dai *cpu_dai) 932 { 933 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 934 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 935 struct snd_dmaengine_dai_dma_data *dma_data; 936 int wlen, channels, wpf; 937 int pkt_size = 0; 938 unsigned int format, div, framesize, master; 939 unsigned int buffer_size = mcbsp->pdata->buffer_size; 940 941 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); 942 channels = params_channels(params); 943 944 switch (params_format(params)) { 945 case SNDRV_PCM_FORMAT_S16_LE: 946 wlen = 16; 947 break; 948 case SNDRV_PCM_FORMAT_S32_LE: 949 wlen = 32; 950 break; 951 default: 952 return -EINVAL; 953 } 954 if (buffer_size) { 955 int latency; 956 957 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { 958 int period_words, max_thrsh; 959 int divider = 0; 960 961 period_words = params_period_bytes(params) / (wlen / 8); 962 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 963 max_thrsh = mcbsp->max_tx_thres; 964 else 965 max_thrsh = mcbsp->max_rx_thres; 966 /* 967 * Use sDMA packet mode if McBSP is in threshold mode: 968 * If period words less than the FIFO size the packet 969 * size is set to the number of period words, otherwise 970 * Look for the biggest threshold value which divides 971 * the period size evenly. 972 */ 973 divider = period_words / max_thrsh; 974 if (period_words % max_thrsh) 975 divider++; 976 while (period_words % divider && 977 divider < period_words) 978 divider++; 979 if (divider == period_words) 980 return -EINVAL; 981 982 pkt_size = period_words / divider; 983 } else if (channels > 1) { 984 /* Use packet mode for non mono streams */ 985 pkt_size = channels; 986 } 987 988 latency = (buffer_size - pkt_size) / channels; 989 latency = latency * USEC_PER_SEC / 990 (params->rate_num / params->rate_den); 991 mcbsp->latency[substream->stream] = latency; 992 993 omap_mcbsp_set_threshold(substream, pkt_size); 994 } 995 996 dma_data->maxburst = pkt_size; 997 998 if (mcbsp->configured) { 999 /* McBSP already configured by another stream */ 1000 return 0; 1001 } 1002 1003 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); 1004 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); 1005 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); 1006 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); 1007 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1008 wpf = channels; 1009 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || 1010 format == SND_SOC_DAIFMT_LEFT_J)) { 1011 /* Use dual-phase frames */ 1012 regs->rcr2 |= RPHASE; 1013 regs->xcr2 |= XPHASE; 1014 /* Set 1 word per (McBSP) frame for phase1 and phase2 */ 1015 wpf--; 1016 regs->rcr2 |= RFRLEN2(wpf - 1); 1017 regs->xcr2 |= XFRLEN2(wpf - 1); 1018 } 1019 1020 regs->rcr1 |= RFRLEN1(wpf - 1); 1021 regs->xcr1 |= XFRLEN1(wpf - 1); 1022 1023 switch (params_format(params)) { 1024 case SNDRV_PCM_FORMAT_S16_LE: 1025 /* Set word lengths */ 1026 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); 1027 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); 1028 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); 1029 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); 1030 break; 1031 case SNDRV_PCM_FORMAT_S32_LE: 1032 /* Set word lengths */ 1033 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); 1034 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); 1035 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); 1036 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); 1037 break; 1038 default: 1039 /* Unsupported PCM format */ 1040 return -EINVAL; 1041 } 1042 1043 /* In McBSP master modes, FRAME (i.e. sample rate) is generated 1044 * by _counting_ BCLKs. Calculate frame size in BCLKs */ 1045 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK; 1046 if (master == SND_SOC_DAIFMT_CBS_CFS) { 1047 div = mcbsp->clk_div ? mcbsp->clk_div : 1; 1048 framesize = (mcbsp->in_freq / div) / params_rate(params); 1049 1050 if (framesize < wlen * channels) { 1051 printk(KERN_ERR "%s: not enough bandwidth for desired rate and " 1052 "channels\n", __func__); 1053 return -EINVAL; 1054 } 1055 } else 1056 framesize = wlen * channels; 1057 1058 /* Set FS period and length in terms of bit clock periods */ 1059 regs->srgr2 &= ~FPER(0xfff); 1060 regs->srgr1 &= ~FWID(0xff); 1061 switch (format) { 1062 case SND_SOC_DAIFMT_I2S: 1063 case SND_SOC_DAIFMT_LEFT_J: 1064 regs->srgr2 |= FPER(framesize - 1); 1065 regs->srgr1 |= FWID((framesize >> 1) - 1); 1066 break; 1067 case SND_SOC_DAIFMT_DSP_A: 1068 case SND_SOC_DAIFMT_DSP_B: 1069 regs->srgr2 |= FPER(framesize - 1); 1070 regs->srgr1 |= FWID(0); 1071 break; 1072 } 1073 1074 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs); 1075 mcbsp->wlen = wlen; 1076 mcbsp->configured = 1; 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * This must be called before _set_clkdiv and _set_sysclk since McBSP register 1083 * cache is initialized here 1084 */ 1085 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 1086 unsigned int fmt) 1087 { 1088 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1089 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1090 bool inv_fs = false; 1091 1092 if (mcbsp->configured) 1093 return 0; 1094 1095 mcbsp->fmt = fmt; 1096 memset(regs, 0, sizeof(*regs)); 1097 /* Generic McBSP register settings */ 1098 regs->spcr2 |= XINTM(3) | FREE; 1099 regs->spcr1 |= RINTM(3); 1100 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */ 1101 if (!mcbsp->pdata->has_ccr) { 1102 regs->rcr2 |= RFIG; 1103 regs->xcr2 |= XFIG; 1104 } 1105 1106 /* Configure XCCR/RCCR only for revisions which have ccr registers */ 1107 if (mcbsp->pdata->has_ccr) { 1108 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; 1109 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; 1110 } 1111 1112 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1113 case SND_SOC_DAIFMT_I2S: 1114 /* 1-bit data delay */ 1115 regs->rcr2 |= RDATDLY(1); 1116 regs->xcr2 |= XDATDLY(1); 1117 break; 1118 case SND_SOC_DAIFMT_LEFT_J: 1119 /* 0-bit data delay */ 1120 regs->rcr2 |= RDATDLY(0); 1121 regs->xcr2 |= XDATDLY(0); 1122 regs->spcr1 |= RJUST(2); 1123 /* Invert FS polarity configuration */ 1124 inv_fs = true; 1125 break; 1126 case SND_SOC_DAIFMT_DSP_A: 1127 /* 1-bit data delay */ 1128 regs->rcr2 |= RDATDLY(1); 1129 regs->xcr2 |= XDATDLY(1); 1130 /* Invert FS polarity configuration */ 1131 inv_fs = true; 1132 break; 1133 case SND_SOC_DAIFMT_DSP_B: 1134 /* 0-bit data delay */ 1135 regs->rcr2 |= RDATDLY(0); 1136 regs->xcr2 |= XDATDLY(0); 1137 /* Invert FS polarity configuration */ 1138 inv_fs = true; 1139 break; 1140 default: 1141 /* Unsupported data format */ 1142 return -EINVAL; 1143 } 1144 1145 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1146 case SND_SOC_DAIFMT_CBS_CFS: 1147 /* McBSP master. Set FS and bit clocks as outputs */ 1148 regs->pcr0 |= FSXM | FSRM | 1149 CLKXM | CLKRM; 1150 /* Sample rate generator drives the FS */ 1151 regs->srgr2 |= FSGM; 1152 break; 1153 case SND_SOC_DAIFMT_CBM_CFS: 1154 /* McBSP slave. FS clock as output */ 1155 regs->srgr2 |= FSGM; 1156 regs->pcr0 |= FSXM | FSRM; 1157 break; 1158 case SND_SOC_DAIFMT_CBM_CFM: 1159 /* McBSP slave */ 1160 break; 1161 default: 1162 /* Unsupported master/slave configuration */ 1163 return -EINVAL; 1164 } 1165 1166 /* Set bit clock (CLKX/CLKR) and FS polarities */ 1167 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1168 case SND_SOC_DAIFMT_NB_NF: 1169 /* 1170 * Normal BCLK + FS. 1171 * FS active low. TX data driven on falling edge of bit clock 1172 * and RX data sampled on rising edge of bit clock. 1173 */ 1174 regs->pcr0 |= FSXP | FSRP | 1175 CLKXP | CLKRP; 1176 break; 1177 case SND_SOC_DAIFMT_NB_IF: 1178 regs->pcr0 |= CLKXP | CLKRP; 1179 break; 1180 case SND_SOC_DAIFMT_IB_NF: 1181 regs->pcr0 |= FSXP | FSRP; 1182 break; 1183 case SND_SOC_DAIFMT_IB_IF: 1184 break; 1185 default: 1186 return -EINVAL; 1187 } 1188 if (inv_fs == true) 1189 regs->pcr0 ^= FSXP | FSRP; 1190 1191 return 0; 1192 } 1193 1194 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, 1195 int div_id, int div) 1196 { 1197 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1198 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1199 1200 if (div_id != OMAP_MCBSP_CLKGDV) 1201 return -ENODEV; 1202 1203 mcbsp->clk_div = div; 1204 regs->srgr1 &= ~CLKGDV(0xff); 1205 regs->srgr1 |= CLKGDV(div - 1); 1206 1207 return 0; 1208 } 1209 1210 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 1211 int clk_id, unsigned int freq, 1212 int dir) 1213 { 1214 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1215 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1216 int err = 0; 1217 1218 if (mcbsp->active) { 1219 if (freq == mcbsp->in_freq) 1220 return 0; 1221 else 1222 return -EBUSY; 1223 } 1224 1225 mcbsp->in_freq = freq; 1226 regs->srgr2 &= ~CLKSM; 1227 regs->pcr0 &= ~SCLKME; 1228 1229 switch (clk_id) { 1230 case OMAP_MCBSP_SYSCLK_CLK: 1231 regs->srgr2 |= CLKSM; 1232 break; 1233 case OMAP_MCBSP_SYSCLK_CLKS_FCLK: 1234 if (mcbsp_omap1()) { 1235 err = -EINVAL; 1236 break; 1237 } 1238 err = omap2_mcbsp_set_clks_src(mcbsp, 1239 MCBSP_CLKS_PRCM_SRC); 1240 break; 1241 case OMAP_MCBSP_SYSCLK_CLKS_EXT: 1242 if (mcbsp_omap1()) { 1243 err = 0; 1244 break; 1245 } 1246 err = omap2_mcbsp_set_clks_src(mcbsp, 1247 MCBSP_CLKS_PAD_SRC); 1248 break; 1249 1250 case OMAP_MCBSP_SYSCLK_CLKX_EXT: 1251 regs->srgr2 |= CLKSM; 1252 regs->pcr0 |= SCLKME; 1253 /* 1254 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG, 1255 * disable output on those pins. This enables to inject the 1256 * reference clock through CLKX/CLKR. For this to work 1257 * set_dai_sysclk() _needs_ to be called after set_dai_fmt(). 1258 */ 1259 regs->pcr0 &= ~CLKXM; 1260 break; 1261 case OMAP_MCBSP_SYSCLK_CLKR_EXT: 1262 regs->pcr0 |= SCLKME; 1263 /* Disable ouput on CLKR pin in master mode */ 1264 regs->pcr0 &= ~CLKRM; 1265 break; 1266 default: 1267 err = -ENODEV; 1268 } 1269 1270 return err; 1271 } 1272 1273 static const struct snd_soc_dai_ops mcbsp_dai_ops = { 1274 .startup = omap_mcbsp_dai_startup, 1275 .shutdown = omap_mcbsp_dai_shutdown, 1276 .prepare = omap_mcbsp_dai_prepare, 1277 .trigger = omap_mcbsp_dai_trigger, 1278 .delay = omap_mcbsp_dai_delay, 1279 .hw_params = omap_mcbsp_dai_hw_params, 1280 .set_fmt = omap_mcbsp_dai_set_dai_fmt, 1281 .set_clkdiv = omap_mcbsp_dai_set_clkdiv, 1282 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, 1283 }; 1284 1285 static int omap_mcbsp_probe(struct snd_soc_dai *dai) 1286 { 1287 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1288 1289 pm_runtime_enable(mcbsp->dev); 1290 1291 snd_soc_dai_init_dma_data(dai, 1292 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK], 1293 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]); 1294 1295 return 0; 1296 } 1297 1298 static int omap_mcbsp_remove(struct snd_soc_dai *dai) 1299 { 1300 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1301 1302 pm_runtime_disable(mcbsp->dev); 1303 1304 return 0; 1305 } 1306 1307 static struct snd_soc_dai_driver omap_mcbsp_dai = { 1308 .probe = omap_mcbsp_probe, 1309 .remove = omap_mcbsp_remove, 1310 .playback = { 1311 .channels_min = 1, 1312 .channels_max = 16, 1313 .rates = OMAP_MCBSP_RATES, 1314 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1315 }, 1316 .capture = { 1317 .channels_min = 1, 1318 .channels_max = 16, 1319 .rates = OMAP_MCBSP_RATES, 1320 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1321 }, 1322 .ops = &mcbsp_dai_ops, 1323 }; 1324 1325 static const struct snd_soc_component_driver omap_mcbsp_component = { 1326 .name = "omap-mcbsp", 1327 }; 1328 1329 static struct omap_mcbsp_platform_data omap2420_pdata = { 1330 .reg_step = 4, 1331 .reg_size = 2, 1332 }; 1333 1334 static struct omap_mcbsp_platform_data omap2430_pdata = { 1335 .reg_step = 4, 1336 .reg_size = 4, 1337 .has_ccr = true, 1338 }; 1339 1340 static struct omap_mcbsp_platform_data omap3_pdata = { 1341 .reg_step = 4, 1342 .reg_size = 4, 1343 .has_ccr = true, 1344 .has_wakeup = true, 1345 }; 1346 1347 static struct omap_mcbsp_platform_data omap4_pdata = { 1348 .reg_step = 4, 1349 .reg_size = 4, 1350 .has_ccr = true, 1351 .has_wakeup = true, 1352 }; 1353 1354 static const struct of_device_id omap_mcbsp_of_match[] = { 1355 { 1356 .compatible = "ti,omap2420-mcbsp", 1357 .data = &omap2420_pdata, 1358 }, 1359 { 1360 .compatible = "ti,omap2430-mcbsp", 1361 .data = &omap2430_pdata, 1362 }, 1363 { 1364 .compatible = "ti,omap3-mcbsp", 1365 .data = &omap3_pdata, 1366 }, 1367 { 1368 .compatible = "ti,omap4-mcbsp", 1369 .data = &omap4_pdata, 1370 }, 1371 { }, 1372 }; 1373 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match); 1374 1375 static int asoc_mcbsp_probe(struct platform_device *pdev) 1376 { 1377 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev); 1378 struct omap_mcbsp *mcbsp; 1379 const struct of_device_id *match; 1380 int ret; 1381 1382 match = of_match_device(omap_mcbsp_of_match, &pdev->dev); 1383 if (match) { 1384 struct device_node *node = pdev->dev.of_node; 1385 struct omap_mcbsp_platform_data *pdata_quirk = pdata; 1386 int buffer_size; 1387 1388 pdata = devm_kzalloc(&pdev->dev, 1389 sizeof(struct omap_mcbsp_platform_data), 1390 GFP_KERNEL); 1391 if (!pdata) 1392 return -ENOMEM; 1393 1394 memcpy(pdata, match->data, sizeof(*pdata)); 1395 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size)) 1396 pdata->buffer_size = buffer_size; 1397 if (pdata_quirk) 1398 pdata->force_ick_on = pdata_quirk->force_ick_on; 1399 } else if (!pdata) { 1400 dev_err(&pdev->dev, "missing platform data.\n"); 1401 return -EINVAL; 1402 } 1403 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL); 1404 if (!mcbsp) 1405 return -ENOMEM; 1406 1407 mcbsp->id = pdev->id; 1408 mcbsp->pdata = pdata; 1409 mcbsp->dev = &pdev->dev; 1410 platform_set_drvdata(pdev, mcbsp); 1411 1412 ret = omap_mcbsp_init(pdev); 1413 if (ret) 1414 return ret; 1415 1416 if (mcbsp->pdata->reg_size == 2) { 1417 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1418 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1419 } 1420 1421 ret = devm_snd_soc_register_component(&pdev->dev, 1422 &omap_mcbsp_component, 1423 &omap_mcbsp_dai, 1); 1424 if (ret) 1425 return ret; 1426 1427 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 1428 } 1429 1430 static int asoc_mcbsp_remove(struct platform_device *pdev) 1431 { 1432 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 1433 1434 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free) 1435 mcbsp->pdata->ops->free(mcbsp->id); 1436 1437 if (pm_qos_request_active(&mcbsp->pm_qos_req)) 1438 pm_qos_remove_request(&mcbsp->pm_qos_req); 1439 1440 if (mcbsp->pdata->buffer_size) 1441 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group); 1442 1443 omap_mcbsp_st_cleanup(pdev); 1444 1445 clk_put(mcbsp->fclk); 1446 1447 return 0; 1448 } 1449 1450 static struct platform_driver asoc_mcbsp_driver = { 1451 .driver = { 1452 .name = "omap-mcbsp", 1453 .of_match_table = omap_mcbsp_of_match, 1454 }, 1455 1456 .probe = asoc_mcbsp_probe, 1457 .remove = asoc_mcbsp_remove, 1458 }; 1459 1460 module_platform_driver(asoc_mcbsp_driver); 1461 1462 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); 1463 MODULE_DESCRIPTION("OMAP I2S SoC Interface"); 1464 MODULE_LICENSE("GPL"); 1465 MODULE_ALIAS("platform:omap-mcbsp"); 1466