1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> 8 * Peter Ujfalusi <peter.ujfalusi@ti.com> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/initval.h> 21 #include <sound/soc.h> 22 #include <sound/dmaengine_pcm.h> 23 24 #include "omap-mcbsp-priv.h" 25 #include "omap-mcbsp.h" 26 #include "sdma-pcm.h" 27 28 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) 29 30 enum { 31 OMAP_MCBSP_WORD_8 = 0, 32 OMAP_MCBSP_WORD_12, 33 OMAP_MCBSP_WORD_16, 34 OMAP_MCBSP_WORD_20, 35 OMAP_MCBSP_WORD_24, 36 OMAP_MCBSP_WORD_32, 37 }; 38 39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp) 40 { 41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); 42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); 43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); 44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); 45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); 46 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2)); 47 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1)); 48 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2)); 49 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1)); 50 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2)); 51 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1)); 52 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2)); 53 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1)); 54 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0)); 55 dev_dbg(mcbsp->dev, "***********************\n"); 56 } 57 58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id) 59 { 60 struct clk *fck_src; 61 const char *src; 62 int r; 63 64 if (fck_src_id == MCBSP_CLKS_PAD_SRC) 65 src = "pad_fck"; 66 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) 67 src = "prcm_fck"; 68 else 69 return -EINVAL; 70 71 fck_src = clk_get(mcbsp->dev, src); 72 if (IS_ERR(fck_src)) { 73 dev_info(mcbsp->dev, "CLKS: could not clk_get() %s\n", src); 74 return 0; 75 } 76 77 if (mcbsp->active) 78 pm_runtime_put_sync(mcbsp->dev); 79 80 r = clk_set_parent(mcbsp->fclk, fck_src); 81 if (r) 82 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n", 83 src); 84 85 if (mcbsp->active) 86 pm_runtime_get_sync(mcbsp->dev); 87 88 clk_put(fck_src); 89 90 return r; 91 } 92 93 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data) 94 { 95 struct omap_mcbsp *mcbsp = data; 96 u16 irqst; 97 98 irqst = MCBSP_READ(mcbsp, IRQST); 99 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst); 100 101 if (irqst & RSYNCERREN) 102 dev_err(mcbsp->dev, "RX Frame Sync Error!\n"); 103 if (irqst & RFSREN) 104 dev_dbg(mcbsp->dev, "RX Frame Sync\n"); 105 if (irqst & REOFEN) 106 dev_dbg(mcbsp->dev, "RX End Of Frame\n"); 107 if (irqst & RRDYEN) 108 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n"); 109 if (irqst & RUNDFLEN) 110 dev_err(mcbsp->dev, "RX Buffer Underflow!\n"); 111 if (irqst & ROVFLEN) 112 dev_err(mcbsp->dev, "RX Buffer Overflow!\n"); 113 114 if (irqst & XSYNCERREN) 115 dev_err(mcbsp->dev, "TX Frame Sync Error!\n"); 116 if (irqst & XFSXEN) 117 dev_dbg(mcbsp->dev, "TX Frame Sync\n"); 118 if (irqst & XEOFEN) 119 dev_dbg(mcbsp->dev, "TX End Of Frame\n"); 120 if (irqst & XRDYEN) 121 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n"); 122 if (irqst & XUNDFLEN) 123 dev_err(mcbsp->dev, "TX Buffer Underflow!\n"); 124 if (irqst & XOVFLEN) 125 dev_err(mcbsp->dev, "TX Buffer Overflow!\n"); 126 if (irqst & XEMPTYEOFEN) 127 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n"); 128 129 MCBSP_WRITE(mcbsp, IRQST, irqst); 130 131 return IRQ_HANDLED; 132 } 133 134 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data) 135 { 136 struct omap_mcbsp *mcbsp = data; 137 u16 irqst_spcr2; 138 139 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2); 140 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); 141 142 if (irqst_spcr2 & XSYNC_ERR) { 143 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n", 144 irqst_spcr2); 145 /* Writing zero to XSYNC_ERR clears the IRQ */ 146 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2)); 147 } 148 149 return IRQ_HANDLED; 150 } 151 152 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data) 153 { 154 struct omap_mcbsp *mcbsp = data; 155 u16 irqst_spcr1; 156 157 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1); 158 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); 159 160 if (irqst_spcr1 & RSYNC_ERR) { 161 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n", 162 irqst_spcr1); 163 /* Writing zero to RSYNC_ERR clears the IRQ */ 164 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1)); 165 } 166 167 return IRQ_HANDLED; 168 } 169 170 /* 171 * omap_mcbsp_config simply write a config to the 172 * appropriate McBSP. 173 * You either call this function or set the McBSP registers 174 * by yourself before calling omap_mcbsp_start(). 175 */ 176 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp, 177 const struct omap_mcbsp_reg_cfg *config) 178 { 179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", 180 mcbsp->id, mcbsp->phys_base); 181 182 /* We write the given config */ 183 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); 184 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); 185 MCBSP_WRITE(mcbsp, RCR2, config->rcr2); 186 MCBSP_WRITE(mcbsp, RCR1, config->rcr1); 187 MCBSP_WRITE(mcbsp, XCR2, config->xcr2); 188 MCBSP_WRITE(mcbsp, XCR1, config->xcr1); 189 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); 190 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); 191 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 192 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 193 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 194 if (mcbsp->pdata->has_ccr) { 195 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 196 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 197 } 198 /* Enable wakeup behavior */ 199 if (mcbsp->pdata->has_wakeup) 200 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); 201 202 /* Enable TX/RX sync error interrupts by default */ 203 if (mcbsp->irq) 204 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN | 205 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN); 206 } 207 208 /** 209 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register 210 * @mcbsp: omap_mcbsp struct for the McBSP instance 211 * @stream: Stream direction (playback/capture) 212 * 213 * Returns the address of mcbsp data transmit register or data receive register 214 * to be used by DMA for transferring/receiving data 215 */ 216 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp, 217 unsigned int stream) 218 { 219 int data_reg; 220 221 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 222 if (mcbsp->pdata->reg_size == 2) 223 data_reg = OMAP_MCBSP_REG_DXR1; 224 else 225 data_reg = OMAP_MCBSP_REG_DXR; 226 } else { 227 if (mcbsp->pdata->reg_size == 2) 228 data_reg = OMAP_MCBSP_REG_DRR1; 229 else 230 data_reg = OMAP_MCBSP_REG_DRR; 231 } 232 233 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step; 234 } 235 236 /* 237 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. 238 * The threshold parameter is 1 based, and it is converted (threshold - 1) 239 * for the THRSH2 register. 240 */ 241 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 242 { 243 if (threshold && threshold <= mcbsp->max_tx_thres) 244 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); 245 } 246 247 /* 248 * omap_mcbsp_set_rx_threshold configures the receive threshold in words. 249 * The threshold parameter is 1 based, and it is converted (threshold - 1) 250 * for the THRSH1 register. 251 */ 252 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 253 { 254 if (threshold && threshold <= mcbsp->max_rx_thres) 255 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); 256 } 257 258 /* 259 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO 260 */ 261 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp) 262 { 263 u16 buffstat; 264 265 /* Returns the number of free locations in the buffer */ 266 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); 267 268 /* Number of slots are different in McBSP ports */ 269 return mcbsp->pdata->buffer_size - buffstat; 270 } 271 272 /* 273 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO 274 * to reach the threshold value (when the DMA will be triggered to read it) 275 */ 276 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp) 277 { 278 u16 buffstat, threshold; 279 280 /* Returns the number of used locations in the buffer */ 281 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); 282 /* RX threshold */ 283 threshold = MCBSP_READ(mcbsp, THRSH1); 284 285 /* Return the number of location till we reach the threshold limit */ 286 if (threshold <= buffstat) 287 return 0; 288 else 289 return threshold - buffstat; 290 } 291 292 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp) 293 { 294 void *reg_cache; 295 int err; 296 297 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL); 298 if (!reg_cache) 299 return -ENOMEM; 300 301 spin_lock(&mcbsp->lock); 302 if (!mcbsp->free) { 303 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id); 304 err = -EBUSY; 305 goto err_kfree; 306 } 307 308 mcbsp->free = false; 309 mcbsp->reg_cache = reg_cache; 310 spin_unlock(&mcbsp->lock); 311 312 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request) 313 mcbsp->pdata->ops->request(mcbsp->id - 1); 314 315 /* 316 * Make sure that transmitter, receiver and sample-rate generator are 317 * not running before activating IRQs. 318 */ 319 MCBSP_WRITE(mcbsp, SPCR1, 0); 320 MCBSP_WRITE(mcbsp, SPCR2, 0); 321 322 if (mcbsp->irq) { 323 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0, 324 "McBSP", (void *)mcbsp); 325 if (err != 0) { 326 dev_err(mcbsp->dev, "Unable to request IRQ\n"); 327 goto err_clk_disable; 328 } 329 } else { 330 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0, 331 "McBSP TX", (void *)mcbsp); 332 if (err != 0) { 333 dev_err(mcbsp->dev, "Unable to request TX IRQ\n"); 334 goto err_clk_disable; 335 } 336 337 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0, 338 "McBSP RX", (void *)mcbsp); 339 if (err != 0) { 340 dev_err(mcbsp->dev, "Unable to request RX IRQ\n"); 341 goto err_free_irq; 342 } 343 } 344 345 return 0; 346 err_free_irq: 347 free_irq(mcbsp->tx_irq, (void *)mcbsp); 348 err_clk_disable: 349 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 350 mcbsp->pdata->ops->free(mcbsp->id - 1); 351 352 /* Disable wakeup behavior */ 353 if (mcbsp->pdata->has_wakeup) 354 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 355 356 spin_lock(&mcbsp->lock); 357 mcbsp->free = true; 358 mcbsp->reg_cache = NULL; 359 err_kfree: 360 spin_unlock(&mcbsp->lock); 361 kfree(reg_cache); 362 363 return err; 364 } 365 366 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp) 367 { 368 void *reg_cache; 369 370 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 371 mcbsp->pdata->ops->free(mcbsp->id - 1); 372 373 /* Disable wakeup behavior */ 374 if (mcbsp->pdata->has_wakeup) 375 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 376 377 /* Disable interrupt requests */ 378 if (mcbsp->irq) { 379 MCBSP_WRITE(mcbsp, IRQEN, 0); 380 381 free_irq(mcbsp->irq, (void *)mcbsp); 382 } else { 383 free_irq(mcbsp->rx_irq, (void *)mcbsp); 384 free_irq(mcbsp->tx_irq, (void *)mcbsp); 385 } 386 387 reg_cache = mcbsp->reg_cache; 388 389 /* 390 * Select CLKS source from internal source unconditionally before 391 * marking the McBSP port as free. 392 * If the external clock source via MCBSP_CLKS pin has been selected the 393 * system will refuse to enter idle if the CLKS pin source is not reset 394 * back to internal source. 395 */ 396 if (!mcbsp_omap1()) 397 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC); 398 399 spin_lock(&mcbsp->lock); 400 if (mcbsp->free) 401 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); 402 else 403 mcbsp->free = true; 404 mcbsp->reg_cache = NULL; 405 spin_unlock(&mcbsp->lock); 406 407 kfree(reg_cache); 408 } 409 410 /* 411 * Here we start the McBSP, by enabling transmitter, receiver or both. 412 * If no transmitter or receiver is active prior calling, then sample-rate 413 * generator and frame sync are started. 414 */ 415 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream) 416 { 417 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 418 int rx = !tx; 419 int enable_srg = 0; 420 u16 w; 421 422 if (mcbsp->st_data) 423 omap_mcbsp_st_start(mcbsp); 424 425 /* Only enable SRG, if McBSP is master */ 426 w = MCBSP_READ_CACHE(mcbsp, PCR0); 427 if (w & (FSXM | FSRM | CLKXM | CLKRM)) 428 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 429 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 430 431 if (enable_srg) { 432 /* Start the sample generator */ 433 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 434 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); 435 } 436 437 /* Enable transmitter and receiver */ 438 tx &= 1; 439 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 440 MCBSP_WRITE(mcbsp, SPCR2, w | tx); 441 442 rx &= 1; 443 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 444 MCBSP_WRITE(mcbsp, SPCR1, w | rx); 445 446 /* 447 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec 448 * REVISIT: 100us may give enough time for two CLKSRG, however 449 * due to some unknown PM related, clock gating etc. reason it 450 * is now at 500us. 451 */ 452 udelay(500); 453 454 if (enable_srg) { 455 /* Start frame sync */ 456 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 457 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 458 } 459 460 if (mcbsp->pdata->has_ccr) { 461 /* Release the transmitter and receiver */ 462 w = MCBSP_READ_CACHE(mcbsp, XCCR); 463 w &= ~(tx ? XDISABLE : 0); 464 MCBSP_WRITE(mcbsp, XCCR, w); 465 w = MCBSP_READ_CACHE(mcbsp, RCCR); 466 w &= ~(rx ? RDISABLE : 0); 467 MCBSP_WRITE(mcbsp, RCCR, w); 468 } 469 470 /* Dump McBSP Regs */ 471 omap_mcbsp_dump_reg(mcbsp); 472 } 473 474 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream) 475 { 476 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 477 int rx = !tx; 478 int idle; 479 u16 w; 480 481 /* Reset transmitter */ 482 tx &= 1; 483 if (mcbsp->pdata->has_ccr) { 484 w = MCBSP_READ_CACHE(mcbsp, XCCR); 485 w |= (tx ? XDISABLE : 0); 486 MCBSP_WRITE(mcbsp, XCCR, w); 487 } 488 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 489 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); 490 491 /* Reset receiver */ 492 rx &= 1; 493 if (mcbsp->pdata->has_ccr) { 494 w = MCBSP_READ_CACHE(mcbsp, RCCR); 495 w |= (rx ? RDISABLE : 0); 496 MCBSP_WRITE(mcbsp, RCCR, w); 497 } 498 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 499 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); 500 501 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 502 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 503 504 if (idle) { 505 /* Reset the sample rate generator */ 506 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 507 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); 508 } 509 510 if (mcbsp->st_data) 511 omap_mcbsp_st_stop(mcbsp); 512 } 513 514 #define max_thres(m) (mcbsp->pdata->buffer_size) 515 #define valid_threshold(m, val) ((val) <= max_thres(m)) 516 #define THRESHOLD_PROP_BUILDER(prop) \ 517 static ssize_t prop##_show(struct device *dev, \ 518 struct device_attribute *attr, char *buf) \ 519 { \ 520 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 521 \ 522 return sysfs_emit(buf, "%u\n", mcbsp->prop); \ 523 } \ 524 \ 525 static ssize_t prop##_store(struct device *dev, \ 526 struct device_attribute *attr, \ 527 const char *buf, size_t size) \ 528 { \ 529 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 530 unsigned long val; \ 531 int status; \ 532 \ 533 status = kstrtoul(buf, 0, &val); \ 534 if (status) \ 535 return status; \ 536 \ 537 if (!valid_threshold(mcbsp, val)) \ 538 return -EDOM; \ 539 \ 540 mcbsp->prop = val; \ 541 return size; \ 542 } \ 543 \ 544 static DEVICE_ATTR_RW(prop) 545 546 THRESHOLD_PROP_BUILDER(max_tx_thres); 547 THRESHOLD_PROP_BUILDER(max_rx_thres); 548 549 static const char * const dma_op_modes[] = { 550 "element", "threshold", 551 }; 552 553 static ssize_t dma_op_mode_show(struct device *dev, 554 struct device_attribute *attr, char *buf) 555 { 556 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 557 int dma_op_mode, i = 0; 558 ssize_t len = 0; 559 const char * const *s; 560 561 dma_op_mode = mcbsp->dma_op_mode; 562 563 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) { 564 if (dma_op_mode == i) 565 len += sysfs_emit_at(buf, len, "[%s] ", *s); 566 else 567 len += sysfs_emit_at(buf, len, "%s ", *s); 568 } 569 len += sysfs_emit_at(buf, len, "\n"); 570 571 return len; 572 } 573 574 static ssize_t dma_op_mode_store(struct device *dev, 575 struct device_attribute *attr, const char *buf, 576 size_t size) 577 { 578 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 579 int i; 580 581 i = sysfs_match_string(dma_op_modes, buf); 582 if (i < 0) 583 return i; 584 585 spin_lock_irq(&mcbsp->lock); 586 if (!mcbsp->free) { 587 size = -EBUSY; 588 goto unlock; 589 } 590 mcbsp->dma_op_mode = i; 591 592 unlock: 593 spin_unlock_irq(&mcbsp->lock); 594 595 return size; 596 } 597 598 static DEVICE_ATTR_RW(dma_op_mode); 599 600 static const struct attribute *additional_attrs[] = { 601 &dev_attr_max_tx_thres.attr, 602 &dev_attr_max_rx_thres.attr, 603 &dev_attr_dma_op_mode.attr, 604 NULL, 605 }; 606 607 static const struct attribute_group additional_attr_group = { 608 .attrs = (struct attribute **)additional_attrs, 609 }; 610 611 /* 612 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 613 * 730 has only 2 McBSP, and both of them are MPU peripherals. 614 */ 615 static int omap_mcbsp_init(struct platform_device *pdev) 616 { 617 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 618 struct resource *res; 619 int ret; 620 621 spin_lock_init(&mcbsp->lock); 622 mcbsp->free = true; 623 624 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 625 if (!res) 626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 627 628 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res); 629 if (IS_ERR(mcbsp->io_base)) 630 return PTR_ERR(mcbsp->io_base); 631 632 mcbsp->phys_base = res->start; 633 mcbsp->reg_cache_size = resource_size(res); 634 635 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 636 if (!res) 637 mcbsp->phys_dma_base = mcbsp->phys_base; 638 else 639 mcbsp->phys_dma_base = res->start; 640 641 /* 642 * OMAP1, 2 uses two interrupt lines: TX, RX 643 * OMAP2430, OMAP3 SoC have combined IRQ line as well. 644 * OMAP4 and newer SoC only have the combined IRQ line. 645 * Use the combined IRQ if available since it gives better debugging 646 * possibilities. 647 */ 648 mcbsp->irq = platform_get_irq_byname(pdev, "common"); 649 if (mcbsp->irq == -ENXIO) { 650 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); 651 652 if (mcbsp->tx_irq == -ENXIO) { 653 mcbsp->irq = platform_get_irq(pdev, 0); 654 mcbsp->tx_irq = 0; 655 } else { 656 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); 657 mcbsp->irq = 0; 658 } 659 } 660 661 if (!pdev->dev.of_node) { 662 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 663 if (!res) { 664 dev_err(&pdev->dev, "invalid tx DMA channel\n"); 665 return -ENODEV; 666 } 667 mcbsp->dma_req[0] = res->start; 668 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0]; 669 670 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 671 if (!res) { 672 dev_err(&pdev->dev, "invalid rx DMA channel\n"); 673 return -ENODEV; 674 } 675 mcbsp->dma_req[1] = res->start; 676 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1]; 677 } else { 678 mcbsp->dma_data[0].filter_data = "tx"; 679 mcbsp->dma_data[1].filter_data = "rx"; 680 } 681 682 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 683 SNDRV_PCM_STREAM_PLAYBACK); 684 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 685 SNDRV_PCM_STREAM_CAPTURE); 686 687 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck"); 688 if (IS_ERR(mcbsp->fclk)) { 689 ret = PTR_ERR(mcbsp->fclk); 690 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret); 691 return ret; 692 } 693 694 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; 695 if (mcbsp->pdata->buffer_size) { 696 /* 697 * Initially configure the maximum thresholds to a safe value. 698 * The McBSP FIFO usage with these values should not go under 699 * 16 locations. 700 * If the whole FIFO without safety buffer is used, than there 701 * is a possibility that the DMA will be not able to push the 702 * new data on time, causing channel shifts in runtime. 703 */ 704 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; 705 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; 706 707 ret = devm_device_add_group(mcbsp->dev, &additional_attr_group); 708 if (ret) { 709 dev_err(mcbsp->dev, 710 "Unable to create additional controls\n"); 711 return ret; 712 } 713 } 714 715 return omap_mcbsp_st_init(pdev); 716 } 717 718 /* 719 * Stream DMA parameters. DMA request line and port address are set runtime 720 * since they are different between OMAP1 and later OMAPs 721 */ 722 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream, 723 unsigned int packet_size) 724 { 725 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 726 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); 727 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 728 int words; 729 730 /* No need to proceed further if McBSP does not have FIFO */ 731 if (mcbsp->pdata->buffer_size == 0) 732 return; 733 734 /* 735 * Configure McBSP threshold based on either: 736 * packet_size, when the sDMA is in packet mode, or based on the 737 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1 738 * for mono streams. 739 */ 740 if (packet_size) 741 words = packet_size; 742 else 743 words = 1; 744 745 /* Configure McBSP internal buffer usage */ 746 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 747 omap_mcbsp_set_tx_threshold(mcbsp, words); 748 else 749 omap_mcbsp_set_rx_threshold(mcbsp, words); 750 } 751 752 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, 753 struct snd_pcm_hw_rule *rule) 754 { 755 struct snd_interval *buffer_size = hw_param_interval(params, 756 SNDRV_PCM_HW_PARAM_BUFFER_SIZE); 757 struct snd_interval *channels = hw_param_interval(params, 758 SNDRV_PCM_HW_PARAM_CHANNELS); 759 struct omap_mcbsp *mcbsp = rule->private; 760 struct snd_interval frames; 761 int size; 762 763 snd_interval_any(&frames); 764 size = mcbsp->pdata->buffer_size; 765 766 frames.min = size / channels->min; 767 frames.integer = 1; 768 return snd_interval_refine(buffer_size, &frames); 769 } 770 771 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, 772 struct snd_soc_dai *cpu_dai) 773 { 774 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 775 int err = 0; 776 777 if (!snd_soc_dai_active(cpu_dai)) 778 err = omap_mcbsp_request(mcbsp); 779 780 /* 781 * OMAP3 McBSP FIFO is word structured. 782 * McBSP2 has 1024 + 256 = 1280 word long buffer, 783 * McBSP1,3,4,5 has 128 word long buffer 784 * This means that the size of the FIFO depends on the sample format. 785 * For example on McBSP3: 786 * 16bit samples: size is 128 * 2 = 256 bytes 787 * 32bit samples: size is 128 * 4 = 512 bytes 788 * It is simpler to place constraint for buffer and period based on 789 * channels. 790 * McBSP3 as example again (16 or 32 bit samples): 791 * 1 channel (mono): size is 128 frames (128 words) 792 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) 793 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) 794 */ 795 if (mcbsp->pdata->buffer_size) { 796 /* 797 * Rule for the buffer size. We should not allow 798 * smaller buffer than the FIFO size to avoid underruns. 799 * This applies only for the playback stream. 800 */ 801 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 802 snd_pcm_hw_rule_add(substream->runtime, 0, 803 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 804 omap_mcbsp_hwrule_min_buffersize, 805 mcbsp, 806 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 807 808 /* Make sure, that the period size is always even */ 809 snd_pcm_hw_constraint_step(substream->runtime, 0, 810 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 811 } 812 813 return err; 814 } 815 816 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, 817 struct snd_soc_dai *cpu_dai) 818 { 819 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 820 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 821 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 822 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 823 824 if (mcbsp->latency[stream2]) 825 cpu_latency_qos_update_request(&mcbsp->pm_qos_req, 826 mcbsp->latency[stream2]); 827 else if (mcbsp->latency[stream1]) 828 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req); 829 830 mcbsp->latency[stream1] = 0; 831 832 if (!snd_soc_dai_active(cpu_dai)) { 833 omap_mcbsp_free(mcbsp); 834 mcbsp->configured = 0; 835 } 836 } 837 838 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream, 839 struct snd_soc_dai *cpu_dai) 840 { 841 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 842 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req; 843 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 844 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 845 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 846 int latency = mcbsp->latency[stream2]; 847 848 /* Prevent omap hardware from hitting off between FIFO fills */ 849 if (!latency || mcbsp->latency[stream1] < latency) 850 latency = mcbsp->latency[stream1]; 851 852 if (cpu_latency_qos_request_active(pm_qos_req)) 853 cpu_latency_qos_update_request(pm_qos_req, latency); 854 else if (latency) 855 cpu_latency_qos_add_request(pm_qos_req, latency); 856 857 return 0; 858 } 859 860 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, 861 struct snd_soc_dai *cpu_dai) 862 { 863 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 864 865 switch (cmd) { 866 case SNDRV_PCM_TRIGGER_START: 867 case SNDRV_PCM_TRIGGER_RESUME: 868 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 869 mcbsp->active++; 870 omap_mcbsp_start(mcbsp, substream->stream); 871 break; 872 873 case SNDRV_PCM_TRIGGER_STOP: 874 case SNDRV_PCM_TRIGGER_SUSPEND: 875 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 876 omap_mcbsp_stop(mcbsp, substream->stream); 877 mcbsp->active--; 878 break; 879 default: 880 return -EINVAL; 881 } 882 883 return 0; 884 } 885 886 static snd_pcm_sframes_t omap_mcbsp_dai_delay( 887 struct snd_pcm_substream *substream, 888 struct snd_soc_dai *dai) 889 { 890 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 891 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); 892 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 893 u16 fifo_use; 894 snd_pcm_sframes_t delay; 895 896 /* No need to proceed further if McBSP does not have FIFO */ 897 if (mcbsp->pdata->buffer_size == 0) 898 return 0; 899 900 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 901 fifo_use = omap_mcbsp_get_tx_delay(mcbsp); 902 else 903 fifo_use = omap_mcbsp_get_rx_delay(mcbsp); 904 905 /* 906 * Divide the used locations with the channel count to get the 907 * FIFO usage in samples (don't care about partial samples in the 908 * buffer). 909 */ 910 delay = fifo_use / substream->runtime->channels; 911 912 return delay; 913 } 914 915 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 916 struct snd_pcm_hw_params *params, 917 struct snd_soc_dai *cpu_dai) 918 { 919 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 920 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 921 struct snd_dmaengine_dai_dma_data *dma_data; 922 int wlen, channels, wpf; 923 int pkt_size = 0; 924 unsigned int format, div, framesize, master; 925 unsigned int buffer_size = mcbsp->pdata->buffer_size; 926 927 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); 928 channels = params_channels(params); 929 930 switch (params_format(params)) { 931 case SNDRV_PCM_FORMAT_S16_LE: 932 wlen = 16; 933 break; 934 case SNDRV_PCM_FORMAT_S32_LE: 935 wlen = 32; 936 break; 937 default: 938 return -EINVAL; 939 } 940 if (buffer_size) { 941 int latency; 942 943 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { 944 int period_words, max_thrsh; 945 int divider = 0; 946 947 period_words = params_period_bytes(params) / (wlen / 8); 948 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 949 max_thrsh = mcbsp->max_tx_thres; 950 else 951 max_thrsh = mcbsp->max_rx_thres; 952 /* 953 * Use sDMA packet mode if McBSP is in threshold mode: 954 * If period words less than the FIFO size the packet 955 * size is set to the number of period words, otherwise 956 * Look for the biggest threshold value which divides 957 * the period size evenly. 958 */ 959 divider = period_words / max_thrsh; 960 if (period_words % max_thrsh) 961 divider++; 962 while (period_words % divider && 963 divider < period_words) 964 divider++; 965 if (divider == period_words) 966 return -EINVAL; 967 968 pkt_size = period_words / divider; 969 } else if (channels > 1) { 970 /* Use packet mode for non mono streams */ 971 pkt_size = channels; 972 } 973 974 latency = (buffer_size - pkt_size) / channels; 975 latency = latency * USEC_PER_SEC / 976 (params->rate_num / params->rate_den); 977 mcbsp->latency[substream->stream] = latency; 978 979 omap_mcbsp_set_threshold(substream, pkt_size); 980 } 981 982 dma_data->maxburst = pkt_size; 983 984 if (mcbsp->configured) { 985 /* McBSP already configured by another stream */ 986 return 0; 987 } 988 989 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); 990 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); 991 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); 992 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); 993 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 994 wpf = channels; 995 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || 996 format == SND_SOC_DAIFMT_LEFT_J)) { 997 /* Use dual-phase frames */ 998 regs->rcr2 |= RPHASE; 999 regs->xcr2 |= XPHASE; 1000 /* Set 1 word per (McBSP) frame for phase1 and phase2 */ 1001 wpf--; 1002 regs->rcr2 |= RFRLEN2(wpf - 1); 1003 regs->xcr2 |= XFRLEN2(wpf - 1); 1004 } 1005 1006 regs->rcr1 |= RFRLEN1(wpf - 1); 1007 regs->xcr1 |= XFRLEN1(wpf - 1); 1008 1009 switch (params_format(params)) { 1010 case SNDRV_PCM_FORMAT_S16_LE: 1011 /* Set word lengths */ 1012 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); 1013 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); 1014 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); 1015 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); 1016 break; 1017 case SNDRV_PCM_FORMAT_S32_LE: 1018 /* Set word lengths */ 1019 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); 1020 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); 1021 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); 1022 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); 1023 break; 1024 default: 1025 /* Unsupported PCM format */ 1026 return -EINVAL; 1027 } 1028 1029 /* In McBSP master modes, FRAME (i.e. sample rate) is generated 1030 * by _counting_ BCLKs. Calculate frame size in BCLKs */ 1031 master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; 1032 if (master == SND_SOC_DAIFMT_BP_FP) { 1033 div = mcbsp->clk_div ? mcbsp->clk_div : 1; 1034 framesize = (mcbsp->in_freq / div) / params_rate(params); 1035 1036 if (framesize < wlen * channels) { 1037 printk(KERN_ERR "%s: not enough bandwidth for desired rate and " 1038 "channels\n", __func__); 1039 return -EINVAL; 1040 } 1041 } else 1042 framesize = wlen * channels; 1043 1044 /* Set FS period and length in terms of bit clock periods */ 1045 regs->srgr2 &= ~FPER(0xfff); 1046 regs->srgr1 &= ~FWID(0xff); 1047 switch (format) { 1048 case SND_SOC_DAIFMT_I2S: 1049 case SND_SOC_DAIFMT_LEFT_J: 1050 regs->srgr2 |= FPER(framesize - 1); 1051 regs->srgr1 |= FWID((framesize >> 1) - 1); 1052 break; 1053 case SND_SOC_DAIFMT_DSP_A: 1054 case SND_SOC_DAIFMT_DSP_B: 1055 regs->srgr2 |= FPER(framesize - 1); 1056 regs->srgr1 |= FWID(0); 1057 break; 1058 } 1059 1060 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs); 1061 mcbsp->wlen = wlen; 1062 mcbsp->configured = 1; 1063 1064 return 0; 1065 } 1066 1067 /* 1068 * This must be called before _set_clkdiv and _set_sysclk since McBSP register 1069 * cache is initialized here 1070 */ 1071 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 1072 unsigned int fmt) 1073 { 1074 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1075 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1076 bool inv_fs = false; 1077 1078 if (mcbsp->configured) 1079 return 0; 1080 1081 mcbsp->fmt = fmt; 1082 memset(regs, 0, sizeof(*regs)); 1083 /* Generic McBSP register settings */ 1084 regs->spcr2 |= XINTM(3) | FREE; 1085 regs->spcr1 |= RINTM(3); 1086 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */ 1087 if (!mcbsp->pdata->has_ccr) { 1088 regs->rcr2 |= RFIG; 1089 regs->xcr2 |= XFIG; 1090 } 1091 1092 /* Configure XCCR/RCCR only for revisions which have ccr registers */ 1093 if (mcbsp->pdata->has_ccr) { 1094 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; 1095 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; 1096 } 1097 1098 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1099 case SND_SOC_DAIFMT_I2S: 1100 /* 1-bit data delay */ 1101 regs->rcr2 |= RDATDLY(1); 1102 regs->xcr2 |= XDATDLY(1); 1103 break; 1104 case SND_SOC_DAIFMT_LEFT_J: 1105 /* 0-bit data delay */ 1106 regs->rcr2 |= RDATDLY(0); 1107 regs->xcr2 |= XDATDLY(0); 1108 regs->spcr1 |= RJUST(2); 1109 /* Invert FS polarity configuration */ 1110 inv_fs = true; 1111 break; 1112 case SND_SOC_DAIFMT_DSP_A: 1113 /* 1-bit data delay */ 1114 regs->rcr2 |= RDATDLY(1); 1115 regs->xcr2 |= XDATDLY(1); 1116 /* Invert FS polarity configuration */ 1117 inv_fs = true; 1118 break; 1119 case SND_SOC_DAIFMT_DSP_B: 1120 /* 0-bit data delay */ 1121 regs->rcr2 |= RDATDLY(0); 1122 regs->xcr2 |= XDATDLY(0); 1123 /* Invert FS polarity configuration */ 1124 inv_fs = true; 1125 break; 1126 default: 1127 /* Unsupported data format */ 1128 return -EINVAL; 1129 } 1130 1131 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1132 case SND_SOC_DAIFMT_BP_FP: 1133 /* McBSP master. Set FS and bit clocks as outputs */ 1134 regs->pcr0 |= FSXM | FSRM | 1135 CLKXM | CLKRM; 1136 /* Sample rate generator drives the FS */ 1137 regs->srgr2 |= FSGM; 1138 break; 1139 case SND_SOC_DAIFMT_BC_FP: 1140 /* McBSP slave. FS clock as output */ 1141 regs->srgr2 |= FSGM; 1142 regs->pcr0 |= FSXM | FSRM; 1143 break; 1144 case SND_SOC_DAIFMT_BC_FC: 1145 /* McBSP slave */ 1146 break; 1147 default: 1148 /* Unsupported master/slave configuration */ 1149 return -EINVAL; 1150 } 1151 1152 /* Set bit clock (CLKX/CLKR) and FS polarities */ 1153 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1154 case SND_SOC_DAIFMT_NB_NF: 1155 /* 1156 * Normal BCLK + FS. 1157 * FS active low. TX data driven on falling edge of bit clock 1158 * and RX data sampled on rising edge of bit clock. 1159 */ 1160 regs->pcr0 |= FSXP | FSRP | 1161 CLKXP | CLKRP; 1162 break; 1163 case SND_SOC_DAIFMT_NB_IF: 1164 regs->pcr0 |= CLKXP | CLKRP; 1165 break; 1166 case SND_SOC_DAIFMT_IB_NF: 1167 regs->pcr0 |= FSXP | FSRP; 1168 break; 1169 case SND_SOC_DAIFMT_IB_IF: 1170 break; 1171 default: 1172 return -EINVAL; 1173 } 1174 if (inv_fs) 1175 regs->pcr0 ^= FSXP | FSRP; 1176 1177 return 0; 1178 } 1179 1180 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, 1181 int div_id, int div) 1182 { 1183 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1184 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1185 1186 if (div_id != OMAP_MCBSP_CLKGDV) 1187 return -ENODEV; 1188 1189 mcbsp->clk_div = div; 1190 regs->srgr1 &= ~CLKGDV(0xff); 1191 regs->srgr1 |= CLKGDV(div - 1); 1192 1193 return 0; 1194 } 1195 1196 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 1197 int clk_id, unsigned int freq, 1198 int dir) 1199 { 1200 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1201 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1202 int err = 0; 1203 1204 if (mcbsp->active) { 1205 if (freq == mcbsp->in_freq) 1206 return 0; 1207 else 1208 return -EBUSY; 1209 } 1210 1211 mcbsp->in_freq = freq; 1212 regs->srgr2 &= ~CLKSM; 1213 regs->pcr0 &= ~SCLKME; 1214 1215 switch (clk_id) { 1216 case OMAP_MCBSP_SYSCLK_CLK: 1217 regs->srgr2 |= CLKSM; 1218 break; 1219 case OMAP_MCBSP_SYSCLK_CLKS_FCLK: 1220 if (mcbsp_omap1()) { 1221 err = -EINVAL; 1222 break; 1223 } 1224 err = omap2_mcbsp_set_clks_src(mcbsp, 1225 MCBSP_CLKS_PRCM_SRC); 1226 break; 1227 case OMAP_MCBSP_SYSCLK_CLKS_EXT: 1228 if (mcbsp_omap1()) { 1229 err = 0; 1230 break; 1231 } 1232 err = omap2_mcbsp_set_clks_src(mcbsp, 1233 MCBSP_CLKS_PAD_SRC); 1234 break; 1235 1236 case OMAP_MCBSP_SYSCLK_CLKX_EXT: 1237 regs->srgr2 |= CLKSM; 1238 regs->pcr0 |= SCLKME; 1239 /* 1240 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG, 1241 * disable output on those pins. This enables to inject the 1242 * reference clock through CLKX/CLKR. For this to work 1243 * set_dai_sysclk() _needs_ to be called after set_dai_fmt(). 1244 */ 1245 regs->pcr0 &= ~CLKXM; 1246 break; 1247 case OMAP_MCBSP_SYSCLK_CLKR_EXT: 1248 regs->pcr0 |= SCLKME; 1249 /* Disable ouput on CLKR pin in master mode */ 1250 regs->pcr0 &= ~CLKRM; 1251 break; 1252 default: 1253 err = -ENODEV; 1254 } 1255 1256 return err; 1257 } 1258 1259 static int omap_mcbsp_probe(struct snd_soc_dai *dai) 1260 { 1261 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1262 1263 pm_runtime_enable(mcbsp->dev); 1264 1265 snd_soc_dai_init_dma_data(dai, 1266 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK], 1267 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]); 1268 1269 return 0; 1270 } 1271 1272 static int omap_mcbsp_remove(struct snd_soc_dai *dai) 1273 { 1274 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1275 1276 pm_runtime_disable(mcbsp->dev); 1277 1278 return 0; 1279 } 1280 1281 static const struct snd_soc_dai_ops mcbsp_dai_ops = { 1282 .probe = omap_mcbsp_probe, 1283 .remove = omap_mcbsp_remove, 1284 .startup = omap_mcbsp_dai_startup, 1285 .shutdown = omap_mcbsp_dai_shutdown, 1286 .prepare = omap_mcbsp_dai_prepare, 1287 .trigger = omap_mcbsp_dai_trigger, 1288 .delay = omap_mcbsp_dai_delay, 1289 .hw_params = omap_mcbsp_dai_hw_params, 1290 .set_fmt = omap_mcbsp_dai_set_dai_fmt, 1291 .set_clkdiv = omap_mcbsp_dai_set_clkdiv, 1292 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, 1293 }; 1294 1295 static struct snd_soc_dai_driver omap_mcbsp_dai = { 1296 .playback = { 1297 .channels_min = 1, 1298 .channels_max = 16, 1299 .rates = OMAP_MCBSP_RATES, 1300 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1301 }, 1302 .capture = { 1303 .channels_min = 1, 1304 .channels_max = 16, 1305 .rates = OMAP_MCBSP_RATES, 1306 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1307 }, 1308 .ops = &mcbsp_dai_ops, 1309 }; 1310 1311 static const struct snd_soc_component_driver omap_mcbsp_component = { 1312 .name = "omap-mcbsp", 1313 .legacy_dai_naming = 1, 1314 }; 1315 1316 static struct omap_mcbsp_platform_data omap2420_pdata = { 1317 .reg_step = 4, 1318 .reg_size = 2, 1319 }; 1320 1321 static struct omap_mcbsp_platform_data omap2430_pdata = { 1322 .reg_step = 4, 1323 .reg_size = 4, 1324 .has_ccr = true, 1325 }; 1326 1327 static struct omap_mcbsp_platform_data omap3_pdata = { 1328 .reg_step = 4, 1329 .reg_size = 4, 1330 .has_ccr = true, 1331 .has_wakeup = true, 1332 }; 1333 1334 static struct omap_mcbsp_platform_data omap4_pdata = { 1335 .reg_step = 4, 1336 .reg_size = 4, 1337 .has_ccr = true, 1338 .has_wakeup = true, 1339 }; 1340 1341 static const struct of_device_id omap_mcbsp_of_match[] = { 1342 { 1343 .compatible = "ti,omap2420-mcbsp", 1344 .data = &omap2420_pdata, 1345 }, 1346 { 1347 .compatible = "ti,omap2430-mcbsp", 1348 .data = &omap2430_pdata, 1349 }, 1350 { 1351 .compatible = "ti,omap3-mcbsp", 1352 .data = &omap3_pdata, 1353 }, 1354 { 1355 .compatible = "ti,omap4-mcbsp", 1356 .data = &omap4_pdata, 1357 }, 1358 { }, 1359 }; 1360 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match); 1361 1362 static int asoc_mcbsp_probe(struct platform_device *pdev) 1363 { 1364 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev); 1365 struct omap_mcbsp *mcbsp; 1366 const struct of_device_id *match; 1367 int ret; 1368 1369 match = of_match_device(omap_mcbsp_of_match, &pdev->dev); 1370 if (match) { 1371 struct device_node *node = pdev->dev.of_node; 1372 struct omap_mcbsp_platform_data *pdata_quirk = pdata; 1373 int buffer_size; 1374 1375 pdata = devm_kzalloc(&pdev->dev, 1376 sizeof(struct omap_mcbsp_platform_data), 1377 GFP_KERNEL); 1378 if (!pdata) 1379 return -ENOMEM; 1380 1381 memcpy(pdata, match->data, sizeof(*pdata)); 1382 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size)) 1383 pdata->buffer_size = buffer_size; 1384 if (pdata_quirk) 1385 pdata->force_ick_on = pdata_quirk->force_ick_on; 1386 } else if (!pdata) { 1387 dev_err(&pdev->dev, "missing platform data.\n"); 1388 return -EINVAL; 1389 } 1390 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL); 1391 if (!mcbsp) 1392 return -ENOMEM; 1393 1394 mcbsp->id = pdev->id; 1395 mcbsp->pdata = pdata; 1396 mcbsp->dev = &pdev->dev; 1397 platform_set_drvdata(pdev, mcbsp); 1398 1399 ret = omap_mcbsp_init(pdev); 1400 if (ret) 1401 return ret; 1402 1403 if (mcbsp->pdata->reg_size == 2) { 1404 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1405 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1406 } 1407 1408 ret = devm_snd_soc_register_component(&pdev->dev, 1409 &omap_mcbsp_component, 1410 &omap_mcbsp_dai, 1); 1411 if (ret) 1412 return ret; 1413 1414 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 1415 } 1416 1417 static void asoc_mcbsp_remove(struct platform_device *pdev) 1418 { 1419 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 1420 1421 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free) 1422 mcbsp->pdata->ops->free(mcbsp->id); 1423 1424 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req)) 1425 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req); 1426 } 1427 1428 static struct platform_driver asoc_mcbsp_driver = { 1429 .driver = { 1430 .name = "omap-mcbsp", 1431 .of_match_table = omap_mcbsp_of_match, 1432 }, 1433 1434 .probe = asoc_mcbsp_probe, 1435 .remove_new = asoc_mcbsp_remove, 1436 }; 1437 1438 module_platform_driver(asoc_mcbsp_driver); 1439 1440 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); 1441 MODULE_DESCRIPTION("OMAP I2S SoC Interface"); 1442 MODULE_LICENSE("GPL"); 1443 MODULE_ALIAS("platform:omap-mcbsp"); 1444