1 /* 2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 3 * 4 * Multi-channel Audio Serial Port Driver 5 * 6 * Author: Nirmal Pandey <n-pandey@ti.com>, 7 * Suresh Rajashekara <suresh.r@ti.com> 8 * Steve Chen <schen@.mvista.com> 9 * 10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 11 * Copyright: (C) 2009 Texas Instruments, India 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/slab.h> 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_data/davinci_asp.h> 30 #include <linux/math64.h> 31 #include <linux/bitmap.h> 32 #include <linux/gpio/driver.h> 33 34 #include <sound/asoundef.h> 35 #include <sound/core.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/initval.h> 39 #include <sound/soc.h> 40 #include <sound/dmaengine_pcm.h> 41 42 #include "edma-pcm.h" 43 #include "sdma-pcm.h" 44 #include "davinci-mcasp.h" 45 46 #define MCASP_MAX_AFIFO_DEPTH 64 47 48 #ifdef CONFIG_PM 49 static u32 context_regs[] = { 50 DAVINCI_MCASP_TXFMCTL_REG, 51 DAVINCI_MCASP_RXFMCTL_REG, 52 DAVINCI_MCASP_TXFMT_REG, 53 DAVINCI_MCASP_RXFMT_REG, 54 DAVINCI_MCASP_ACLKXCTL_REG, 55 DAVINCI_MCASP_ACLKRCTL_REG, 56 DAVINCI_MCASP_AHCLKXCTL_REG, 57 DAVINCI_MCASP_AHCLKRCTL_REG, 58 DAVINCI_MCASP_PDIR_REG, 59 DAVINCI_MCASP_PFUNC_REG, 60 DAVINCI_MCASP_RXMASK_REG, 61 DAVINCI_MCASP_TXMASK_REG, 62 DAVINCI_MCASP_RXTDM_REG, 63 DAVINCI_MCASP_TXTDM_REG, 64 }; 65 66 struct davinci_mcasp_context { 67 u32 config_regs[ARRAY_SIZE(context_regs)]; 68 u32 afifo_regs[2]; /* for read/write fifo control registers */ 69 u32 *xrsr_regs; /* for serializer configuration */ 70 bool pm_state; 71 }; 72 #endif 73 74 struct davinci_mcasp_ruledata { 75 struct davinci_mcasp *mcasp; 76 int serializers; 77 }; 78 79 struct davinci_mcasp { 80 struct snd_dmaengine_dai_dma_data dma_data[2]; 81 void __iomem *base; 82 u32 fifo_base; 83 struct device *dev; 84 struct snd_pcm_substream *substreams[2]; 85 unsigned int dai_fmt; 86 87 /* McASP specific data */ 88 int tdm_slots; 89 u32 tdm_mask[2]; 90 int slot_width; 91 u8 op_mode; 92 u8 dismod; 93 u8 num_serializer; 94 u8 *serial_dir; 95 u8 version; 96 u8 bclk_div; 97 int streams; 98 u32 irq_request[2]; 99 int dma_request[2]; 100 101 int sysclk_freq; 102 bool bclk_master; 103 104 unsigned long pdir; /* Pin direction bitfield */ 105 106 /* McASP FIFO related */ 107 u8 txnumevt; 108 u8 rxnumevt; 109 110 bool dat_port; 111 112 /* Used for comstraint setting on the second stream */ 113 u32 channels; 114 115 #ifdef CONFIG_GPIOLIB 116 struct gpio_chip gpio_chip; 117 #endif 118 119 #ifdef CONFIG_PM 120 struct davinci_mcasp_context context; 121 #endif 122 123 struct davinci_mcasp_ruledata ruledata[2]; 124 struct snd_pcm_hw_constraint_list chconstr[2]; 125 }; 126 127 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 128 u32 val) 129 { 130 void __iomem *reg = mcasp->base + offset; 131 __raw_writel(__raw_readl(reg) | val, reg); 132 } 133 134 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 135 u32 val) 136 { 137 void __iomem *reg = mcasp->base + offset; 138 __raw_writel((__raw_readl(reg) & ~(val)), reg); 139 } 140 141 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 142 u32 val, u32 mask) 143 { 144 void __iomem *reg = mcasp->base + offset; 145 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 146 } 147 148 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 149 u32 val) 150 { 151 __raw_writel(val, mcasp->base + offset); 152 } 153 154 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 155 { 156 return (u32)__raw_readl(mcasp->base + offset); 157 } 158 159 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 160 { 161 int i = 0; 162 163 mcasp_set_bits(mcasp, ctl_reg, val); 164 165 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 166 /* loop count is to avoid the lock-up */ 167 for (i = 0; i < 1000; i++) { 168 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 169 break; 170 } 171 172 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 173 printk(KERN_ERR "GBLCTL write error\n"); 174 } 175 176 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 177 { 178 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 179 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 180 181 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 182 } 183 184 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 185 { 186 u32 bit = PIN_BIT_AMUTE; 187 188 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 189 if (enable) 190 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 191 else 192 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 193 } 194 } 195 196 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 197 { 198 u32 bit; 199 200 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) { 201 if (enable) 202 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 203 else 204 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 205 } 206 } 207 208 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 209 { 210 if (mcasp->rxnumevt) { /* enable FIFO */ 211 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 212 213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 215 } 216 217 /* Start clocks */ 218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 220 /* 221 * When ASYNC == 0 the transmit and receive sections operate 222 * synchronously from the transmit clock and frame sync. We need to make 223 * sure that the TX signlas are enabled when starting reception. 224 */ 225 if (mcasp_is_synchronous(mcasp)) { 226 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 228 } 229 230 /* Activate serializer(s) */ 231 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 233 /* Release RX state machine */ 234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 235 /* Release Frame Sync generator */ 236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 237 if (mcasp_is_synchronous(mcasp)) 238 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 239 240 /* enable receive IRQs */ 241 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 242 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 243 } 244 245 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 246 { 247 u32 cnt; 248 249 if (mcasp->txnumevt) { /* enable FIFO */ 250 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 251 252 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 253 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 254 } 255 256 /* Start clocks */ 257 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 258 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 259 mcasp_set_clk_pdir(mcasp, true); 260 261 /* Activate serializer(s) */ 262 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 263 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 264 265 /* wait for XDATA to be cleared */ 266 cnt = 0; 267 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 268 (cnt < 100000)) 269 cnt++; 270 271 mcasp_set_axr_pdir(mcasp, true); 272 273 /* Release TX state machine */ 274 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 275 /* Release Frame Sync generator */ 276 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 277 278 /* enable transmit IRQs */ 279 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 280 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 281 } 282 283 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 284 { 285 mcasp->streams++; 286 287 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 288 mcasp_start_tx(mcasp); 289 else 290 mcasp_start_rx(mcasp); 291 } 292 293 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 294 { 295 /* disable IRQ sources */ 296 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 297 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 298 299 /* 300 * In synchronous mode stop the TX clocks if no other stream is 301 * running 302 */ 303 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 304 mcasp_set_clk_pdir(mcasp, false); 305 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 306 } 307 308 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 309 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 310 311 if (mcasp->rxnumevt) { /* disable FIFO */ 312 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 313 314 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 315 } 316 } 317 318 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 319 { 320 u32 val = 0; 321 322 /* disable IRQ sources */ 323 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 324 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 325 326 /* 327 * In synchronous mode keep TX clocks running if the capture stream is 328 * still running. 329 */ 330 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 331 val = TXHCLKRST | TXCLKRST | TXFSRST; 332 else 333 mcasp_set_clk_pdir(mcasp, false); 334 335 336 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 337 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 338 339 if (mcasp->txnumevt) { /* disable FIFO */ 340 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 341 342 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 343 } 344 345 mcasp_set_axr_pdir(mcasp, false); 346 } 347 348 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 349 { 350 mcasp->streams--; 351 352 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 353 mcasp_stop_tx(mcasp); 354 else 355 mcasp_stop_rx(mcasp); 356 } 357 358 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 359 { 360 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 361 struct snd_pcm_substream *substream; 362 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 363 u32 handled_mask = 0; 364 u32 stat; 365 366 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 367 if (stat & XUNDRN & irq_mask) { 368 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 369 handled_mask |= XUNDRN; 370 371 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 372 if (substream) 373 snd_pcm_stop_xrun(substream); 374 } 375 376 if (!handled_mask) 377 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 378 stat); 379 380 if (stat & XRERR) 381 handled_mask |= XRERR; 382 383 /* Ack the handled event only */ 384 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 385 386 return IRQ_RETVAL(handled_mask); 387 } 388 389 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 390 { 391 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 392 struct snd_pcm_substream *substream; 393 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 394 u32 handled_mask = 0; 395 u32 stat; 396 397 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 398 if (stat & ROVRN & irq_mask) { 399 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 400 handled_mask |= ROVRN; 401 402 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 403 if (substream) 404 snd_pcm_stop_xrun(substream); 405 } 406 407 if (!handled_mask) 408 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 409 stat); 410 411 if (stat & XRERR) 412 handled_mask |= XRERR; 413 414 /* Ack the handled event only */ 415 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 416 417 return IRQ_RETVAL(handled_mask); 418 } 419 420 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 421 { 422 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 423 irqreturn_t ret = IRQ_NONE; 424 425 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 426 ret = davinci_mcasp_tx_irq_handler(irq, data); 427 428 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 429 ret |= davinci_mcasp_rx_irq_handler(irq, data); 430 431 return ret; 432 } 433 434 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 435 unsigned int fmt) 436 { 437 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 438 int ret = 0; 439 u32 data_delay; 440 bool fs_pol_rising; 441 bool inv_fs = false; 442 443 if (!fmt) 444 return 0; 445 446 pm_runtime_get_sync(mcasp->dev); 447 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 448 case SND_SOC_DAIFMT_DSP_A: 449 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 450 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 451 /* 1st data bit occur one ACLK cycle after the frame sync */ 452 data_delay = 1; 453 break; 454 case SND_SOC_DAIFMT_DSP_B: 455 case SND_SOC_DAIFMT_AC97: 456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 458 /* No delay after FS */ 459 data_delay = 0; 460 break; 461 case SND_SOC_DAIFMT_I2S: 462 /* configure a full-word SYNC pulse (LRCLK) */ 463 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 464 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 465 /* 1st data bit occur one ACLK cycle after the frame sync */ 466 data_delay = 1; 467 /* FS need to be inverted */ 468 inv_fs = true; 469 break; 470 case SND_SOC_DAIFMT_LEFT_J: 471 /* configure a full-word SYNC pulse (LRCLK) */ 472 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 473 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 474 /* No delay after FS */ 475 data_delay = 0; 476 break; 477 default: 478 ret = -EINVAL; 479 goto out; 480 } 481 482 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 483 FSXDLY(3)); 484 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 485 FSRDLY(3)); 486 487 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 488 case SND_SOC_DAIFMT_CBS_CFS: 489 /* codec is clock and frame slave */ 490 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 491 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 492 493 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 494 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 495 496 /* BCLK */ 497 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 498 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 499 /* Frame Sync */ 500 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 501 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 502 503 mcasp->bclk_master = 1; 504 break; 505 case SND_SOC_DAIFMT_CBS_CFM: 506 /* codec is clock slave and frame master */ 507 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 509 510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 512 513 /* BCLK */ 514 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 515 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 516 /* Frame Sync */ 517 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 518 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 519 520 mcasp->bclk_master = 1; 521 break; 522 case SND_SOC_DAIFMT_CBM_CFS: 523 /* codec is clock master and frame slave */ 524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 525 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 526 527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 528 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 529 530 /* BCLK */ 531 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 532 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 533 /* Frame Sync */ 534 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 535 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 536 537 mcasp->bclk_master = 0; 538 break; 539 case SND_SOC_DAIFMT_CBM_CFM: 540 /* codec is clock and frame master */ 541 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 542 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 543 544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 546 547 /* BCLK */ 548 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 549 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 550 /* Frame Sync */ 551 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 552 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 553 554 mcasp->bclk_master = 0; 555 break; 556 default: 557 ret = -EINVAL; 558 goto out; 559 } 560 561 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 562 case SND_SOC_DAIFMT_IB_NF: 563 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 564 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 565 fs_pol_rising = true; 566 break; 567 case SND_SOC_DAIFMT_NB_IF: 568 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 569 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 570 fs_pol_rising = false; 571 break; 572 case SND_SOC_DAIFMT_IB_IF: 573 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 574 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 575 fs_pol_rising = false; 576 break; 577 case SND_SOC_DAIFMT_NB_NF: 578 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 579 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 580 fs_pol_rising = true; 581 break; 582 default: 583 ret = -EINVAL; 584 goto out; 585 } 586 587 if (inv_fs) 588 fs_pol_rising = !fs_pol_rising; 589 590 if (fs_pol_rising) { 591 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 592 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 593 } else { 594 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 595 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 596 } 597 598 mcasp->dai_fmt = fmt; 599 out: 600 pm_runtime_put(mcasp->dev); 601 return ret; 602 } 603 604 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 605 int div, bool explicit) 606 { 607 pm_runtime_get_sync(mcasp->dev); 608 switch (div_id) { 609 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 610 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 611 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 612 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 613 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 614 break; 615 616 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 617 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 618 ACLKXDIV(div - 1), ACLKXDIV_MASK); 619 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 620 ACLKRDIV(div - 1), ACLKRDIV_MASK); 621 if (explicit) 622 mcasp->bclk_div = div; 623 break; 624 625 case MCASP_CLKDIV_BCLK_FS_RATIO: 626 /* 627 * BCLK/LRCLK ratio descries how many bit-clock cycles 628 * fit into one frame. The clock ratio is given for a 629 * full period of data (for I2S format both left and 630 * right channels), so it has to be divided by number 631 * of tdm-slots (for I2S - divided by 2). 632 * Instead of storing this ratio, we calculate a new 633 * tdm_slot width by dividing the the ratio by the 634 * number of configured tdm slots. 635 */ 636 mcasp->slot_width = div / mcasp->tdm_slots; 637 if (div % mcasp->tdm_slots) 638 dev_warn(mcasp->dev, 639 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 640 __func__, div, mcasp->tdm_slots); 641 break; 642 643 default: 644 return -EINVAL; 645 } 646 647 pm_runtime_put(mcasp->dev); 648 return 0; 649 } 650 651 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 652 int div) 653 { 654 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 655 656 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 657 } 658 659 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 660 unsigned int freq, int dir) 661 { 662 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 663 664 pm_runtime_get_sync(mcasp->dev); 665 if (dir == SND_SOC_CLOCK_OUT) { 666 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 667 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 668 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 669 } else { 670 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 671 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 672 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 673 } 674 675 mcasp->sysclk_freq = freq; 676 677 pm_runtime_put(mcasp->dev); 678 return 0; 679 } 680 681 /* All serializers must have equal number of channels */ 682 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 683 int serializers) 684 { 685 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 686 unsigned int *list = (unsigned int *) cl->list; 687 int slots = mcasp->tdm_slots; 688 int i, count = 0; 689 690 if (mcasp->tdm_mask[stream]) 691 slots = hweight32(mcasp->tdm_mask[stream]); 692 693 for (i = 1; i <= slots; i++) 694 list[count++] = i; 695 696 for (i = 2; i <= serializers; i++) 697 list[count++] = i*slots; 698 699 cl->count = count; 700 701 return 0; 702 } 703 704 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 705 { 706 int rx_serializers = 0, tx_serializers = 0, ret, i; 707 708 for (i = 0; i < mcasp->num_serializer; i++) 709 if (mcasp->serial_dir[i] == TX_MODE) 710 tx_serializers++; 711 else if (mcasp->serial_dir[i] == RX_MODE) 712 rx_serializers++; 713 714 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 715 tx_serializers); 716 if (ret) 717 return ret; 718 719 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 720 rx_serializers); 721 722 return ret; 723 } 724 725 726 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 727 unsigned int tx_mask, 728 unsigned int rx_mask, 729 int slots, int slot_width) 730 { 731 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 732 733 dev_dbg(mcasp->dev, 734 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 735 __func__, tx_mask, rx_mask, slots, slot_width); 736 737 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 738 dev_err(mcasp->dev, 739 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 740 tx_mask, rx_mask, slots); 741 return -EINVAL; 742 } 743 744 if (slot_width && 745 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 746 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 747 __func__, slot_width); 748 return -EINVAL; 749 } 750 751 mcasp->tdm_slots = slots; 752 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 753 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 754 mcasp->slot_width = slot_width; 755 756 return davinci_mcasp_set_ch_constraints(mcasp); 757 } 758 759 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 760 int sample_width) 761 { 762 u32 fmt; 763 u32 tx_rotate = (sample_width / 4) & 0x7; 764 u32 mask = (1ULL << sample_width) - 1; 765 u32 slot_width = sample_width; 766 767 /* 768 * For captured data we should not rotate, inversion and masking is 769 * enoguh to get the data to the right position: 770 * Format data from bus after reverse (XRBUF) 771 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| 772 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 773 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 774 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| 775 */ 776 u32 rx_rotate = 0; 777 778 /* 779 * Setting the tdm slot width either with set_clkdiv() or 780 * set_tdm_slot() allows us to for example send 32 bits per 781 * channel to the codec, while only 16 of them carry audio 782 * payload. 783 */ 784 if (mcasp->slot_width) { 785 /* 786 * When we have more bclk then it is needed for the 787 * data, we need to use the rotation to move the 788 * received samples to have correct alignment. 789 */ 790 slot_width = mcasp->slot_width; 791 rx_rotate = (slot_width - sample_width) / 4; 792 } 793 794 /* mapping of the XSSZ bit-field as described in the datasheet */ 795 fmt = (slot_width >> 1) - 1; 796 797 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 798 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 799 RXSSZ(0x0F)); 800 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 801 TXSSZ(0x0F)); 802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 803 TXROT(7)); 804 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 805 RXROT(7)); 806 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 807 } 808 809 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 810 811 return 0; 812 } 813 814 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 815 int period_words, int channels) 816 { 817 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 818 int i; 819 u8 tx_ser = 0; 820 u8 rx_ser = 0; 821 u8 slots = mcasp->tdm_slots; 822 u8 max_active_serializers = (channels + slots - 1) / slots; 823 int active_serializers, numevt; 824 u32 reg; 825 /* Default configuration */ 826 if (mcasp->version < MCASP_VERSION_3) 827 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 828 829 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 830 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 831 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 832 } else { 833 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 834 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 835 } 836 837 for (i = 0; i < mcasp->num_serializer; i++) { 838 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 839 mcasp->serial_dir[i]); 840 if (mcasp->serial_dir[i] == TX_MODE && 841 tx_ser < max_active_serializers) { 842 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 843 mcasp->dismod, DISMOD_MASK); 844 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 845 tx_ser++; 846 } else if (mcasp->serial_dir[i] == RX_MODE && 847 rx_ser < max_active_serializers) { 848 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 849 rx_ser++; 850 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) { 851 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 852 SRMOD_INACTIVE, SRMOD_MASK); 853 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 854 } else if (mcasp->serial_dir[i] == TX_MODE) { 855 /* Unused TX pins, clear PDIR */ 856 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 857 mcasp->dismod, DISMOD_MASK); 858 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 859 } 860 } 861 862 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 863 active_serializers = tx_ser; 864 numevt = mcasp->txnumevt; 865 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 866 } else { 867 active_serializers = rx_ser; 868 numevt = mcasp->rxnumevt; 869 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 870 } 871 872 if (active_serializers < max_active_serializers) { 873 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 874 "enabled in mcasp (%d)\n", channels, 875 active_serializers * slots); 876 return -EINVAL; 877 } 878 879 /* AFIFO is not in use */ 880 if (!numevt) { 881 /* Configure the burst size for platform drivers */ 882 if (active_serializers > 1) { 883 /* 884 * If more than one serializers are in use we have one 885 * DMA request to provide data for all serializers. 886 * For example if three serializers are enabled the DMA 887 * need to transfer three words per DMA request. 888 */ 889 dma_data->maxburst = active_serializers; 890 } else { 891 dma_data->maxburst = 0; 892 } 893 return 0; 894 } 895 896 if (period_words % active_serializers) { 897 dev_err(mcasp->dev, "Invalid combination of period words and " 898 "active serializers: %d, %d\n", period_words, 899 active_serializers); 900 return -EINVAL; 901 } 902 903 /* 904 * Calculate the optimal AFIFO depth for platform side: 905 * The number of words for numevt need to be in steps of active 906 * serializers. 907 */ 908 numevt = (numevt / active_serializers) * active_serializers; 909 910 while (period_words % numevt && numevt > 0) 911 numevt -= active_serializers; 912 if (numevt <= 0) 913 numevt = active_serializers; 914 915 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 916 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 917 918 /* Configure the burst size for platform drivers */ 919 if (numevt == 1) 920 numevt = 0; 921 dma_data->maxburst = numevt; 922 923 return 0; 924 } 925 926 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 927 int channels) 928 { 929 int i, active_slots; 930 int total_slots; 931 int active_serializers; 932 u32 mask = 0; 933 u32 busel = 0; 934 935 total_slots = mcasp->tdm_slots; 936 937 /* 938 * If more than one serializer is needed, then use them with 939 * all the specified tdm_slots. Otherwise, one serializer can 940 * cope with the transaction using just as many slots as there 941 * are channels in the stream. 942 */ 943 if (mcasp->tdm_mask[stream]) { 944 active_slots = hweight32(mcasp->tdm_mask[stream]); 945 active_serializers = (channels + active_slots - 1) / 946 active_slots; 947 if (active_serializers == 1) { 948 active_slots = channels; 949 for (i = 0; i < total_slots; i++) { 950 if ((1 << i) & mcasp->tdm_mask[stream]) { 951 mask |= (1 << i); 952 if (--active_slots <= 0) 953 break; 954 } 955 } 956 } 957 } else { 958 active_serializers = (channels + total_slots - 1) / total_slots; 959 if (active_serializers == 1) 960 active_slots = channels; 961 else 962 active_slots = total_slots; 963 964 for (i = 0; i < active_slots; i++) 965 mask |= (1 << i); 966 } 967 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 968 969 if (!mcasp->dat_port) 970 busel = TXSEL; 971 972 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 973 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 974 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 975 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 976 FSXMOD(total_slots), FSXMOD(0x1FF)); 977 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 978 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 979 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 980 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 981 FSRMOD(total_slots), FSRMOD(0x1FF)); 982 /* 983 * If McASP is set to be TX/RX synchronous and the playback is 984 * not running already we need to configure the TX slots in 985 * order to have correct FSX on the bus 986 */ 987 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 988 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 989 FSXMOD(total_slots), FSXMOD(0x1FF)); 990 } 991 992 return 0; 993 } 994 995 /* S/PDIF */ 996 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 997 unsigned int rate) 998 { 999 u32 cs_value = 0; 1000 u8 *cs_bytes = (u8*) &cs_value; 1001 1002 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 1003 and LSB first */ 1004 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); 1005 1006 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1007 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1008 1009 /* Set the TX tdm : for all the slots */ 1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1011 1012 /* Set the TX clock controls : div = 1 and internal */ 1013 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1014 1015 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1016 1017 /* Only 44100 and 48000 are valid, both have the same setting */ 1018 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 1019 1020 /* Enable the DIT */ 1021 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1022 1023 /* Set S/PDIF channel status bits */ 1024 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 1025 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; 1026 1027 switch (rate) { 1028 case 22050: 1029 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1030 break; 1031 case 24000: 1032 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1033 break; 1034 case 32000: 1035 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1036 break; 1037 case 44100: 1038 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1039 break; 1040 case 48000: 1041 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1042 break; 1043 case 88200: 1044 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1045 break; 1046 case 96000: 1047 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1048 break; 1049 case 176400: 1050 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1051 break; 1052 case 192000: 1053 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1054 break; 1055 default: 1056 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); 1057 return -EINVAL; 1058 } 1059 1060 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); 1061 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); 1062 1063 return 0; 1064 } 1065 1066 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1067 unsigned int bclk_freq, bool set) 1068 { 1069 int error_ppm; 1070 unsigned int sysclk_freq = mcasp->sysclk_freq; 1071 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1072 int div = sysclk_freq / bclk_freq; 1073 int rem = sysclk_freq % bclk_freq; 1074 int aux_div = 1; 1075 1076 if (div > (ACLKXDIV_MASK + 1)) { 1077 if (reg & AHCLKXE) { 1078 aux_div = div / (ACLKXDIV_MASK + 1); 1079 if (div % (ACLKXDIV_MASK + 1)) 1080 aux_div++; 1081 1082 sysclk_freq /= aux_div; 1083 div = sysclk_freq / bclk_freq; 1084 rem = sysclk_freq % bclk_freq; 1085 } else if (set) { 1086 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1087 sysclk_freq); 1088 } 1089 } 1090 1091 if (rem != 0) { 1092 if (div == 0 || 1093 ((sysclk_freq / div) - bclk_freq) > 1094 (bclk_freq - (sysclk_freq / (div+1)))) { 1095 div++; 1096 rem = rem - bclk_freq; 1097 } 1098 } 1099 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1100 (int)bclk_freq)) / div - 1000000; 1101 1102 if (set) { 1103 if (error_ppm) 1104 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1105 error_ppm); 1106 1107 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1108 if (reg & AHCLKXE) 1109 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1110 aux_div, 0); 1111 } 1112 1113 return error_ppm; 1114 } 1115 1116 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1117 { 1118 if (!mcasp->txnumevt) 1119 return 0; 1120 1121 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1122 } 1123 1124 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1125 { 1126 if (!mcasp->rxnumevt) 1127 return 0; 1128 1129 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1130 } 1131 1132 static snd_pcm_sframes_t davinci_mcasp_delay( 1133 struct snd_pcm_substream *substream, 1134 struct snd_soc_dai *cpu_dai) 1135 { 1136 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1137 u32 fifo_use; 1138 1139 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1140 fifo_use = davinci_mcasp_tx_delay(mcasp); 1141 else 1142 fifo_use = davinci_mcasp_rx_delay(mcasp); 1143 1144 /* 1145 * Divide the used locations with the channel count to get the 1146 * FIFO usage in samples (don't care about partial samples in the 1147 * buffer). 1148 */ 1149 return fifo_use / substream->runtime->channels; 1150 } 1151 1152 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1153 struct snd_pcm_hw_params *params, 1154 struct snd_soc_dai *cpu_dai) 1155 { 1156 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1157 int word_length; 1158 int channels = params_channels(params); 1159 int period_size = params_period_size(params); 1160 int ret; 1161 1162 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1163 if (ret) 1164 return ret; 1165 1166 /* 1167 * If mcasp is BCLK master, and a BCLK divider was not provided by 1168 * the machine driver, we need to calculate the ratio. 1169 */ 1170 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1171 int slots = mcasp->tdm_slots; 1172 int rate = params_rate(params); 1173 int sbits = params_width(params); 1174 1175 if (mcasp->slot_width) 1176 sbits = mcasp->slot_width; 1177 1178 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true); 1179 } 1180 1181 ret = mcasp_common_hw_param(mcasp, substream->stream, 1182 period_size * channels, channels); 1183 if (ret) 1184 return ret; 1185 1186 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1187 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1188 else 1189 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1190 channels); 1191 1192 if (ret) 1193 return ret; 1194 1195 switch (params_format(params)) { 1196 case SNDRV_PCM_FORMAT_U8: 1197 case SNDRV_PCM_FORMAT_S8: 1198 word_length = 8; 1199 break; 1200 1201 case SNDRV_PCM_FORMAT_U16_LE: 1202 case SNDRV_PCM_FORMAT_S16_LE: 1203 word_length = 16; 1204 break; 1205 1206 case SNDRV_PCM_FORMAT_U24_3LE: 1207 case SNDRV_PCM_FORMAT_S24_3LE: 1208 word_length = 24; 1209 break; 1210 1211 case SNDRV_PCM_FORMAT_U24_LE: 1212 case SNDRV_PCM_FORMAT_S24_LE: 1213 word_length = 24; 1214 break; 1215 1216 case SNDRV_PCM_FORMAT_U32_LE: 1217 case SNDRV_PCM_FORMAT_S32_LE: 1218 word_length = 32; 1219 break; 1220 1221 default: 1222 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1223 return -EINVAL; 1224 } 1225 1226 davinci_config_channel_size(mcasp, word_length); 1227 1228 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1229 mcasp->channels = channels; 1230 1231 return 0; 1232 } 1233 1234 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1235 int cmd, struct snd_soc_dai *cpu_dai) 1236 { 1237 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1238 int ret = 0; 1239 1240 switch (cmd) { 1241 case SNDRV_PCM_TRIGGER_RESUME: 1242 case SNDRV_PCM_TRIGGER_START: 1243 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1244 davinci_mcasp_start(mcasp, substream->stream); 1245 break; 1246 case SNDRV_PCM_TRIGGER_SUSPEND: 1247 case SNDRV_PCM_TRIGGER_STOP: 1248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1249 davinci_mcasp_stop(mcasp, substream->stream); 1250 break; 1251 1252 default: 1253 ret = -EINVAL; 1254 } 1255 1256 return ret; 1257 } 1258 1259 static const unsigned int davinci_mcasp_dai_rates[] = { 1260 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1261 88200, 96000, 176400, 192000, 1262 }; 1263 1264 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1265 1266 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1267 struct snd_pcm_hw_rule *rule) 1268 { 1269 struct davinci_mcasp_ruledata *rd = rule->private; 1270 struct snd_interval *ri = 1271 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1272 int sbits = params_width(params); 1273 int slots = rd->mcasp->tdm_slots; 1274 struct snd_interval range; 1275 int i; 1276 1277 if (rd->mcasp->slot_width) 1278 sbits = rd->mcasp->slot_width; 1279 1280 snd_interval_any(&range); 1281 range.empty = 1; 1282 1283 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1284 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1285 uint bclk_freq = sbits*slots* 1286 davinci_mcasp_dai_rates[i]; 1287 int ppm; 1288 1289 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, 1290 false); 1291 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1292 if (range.empty) { 1293 range.min = davinci_mcasp_dai_rates[i]; 1294 range.empty = 0; 1295 } 1296 range.max = davinci_mcasp_dai_rates[i]; 1297 } 1298 } 1299 } 1300 1301 dev_dbg(rd->mcasp->dev, 1302 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1303 ri->min, ri->max, range.min, range.max, sbits, slots); 1304 1305 return snd_interval_refine(hw_param_interval(params, rule->var), 1306 &range); 1307 } 1308 1309 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1310 struct snd_pcm_hw_rule *rule) 1311 { 1312 struct davinci_mcasp_ruledata *rd = rule->private; 1313 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1314 struct snd_mask nfmt; 1315 int rate = params_rate(params); 1316 int slots = rd->mcasp->tdm_slots; 1317 int i, count = 0; 1318 1319 snd_mask_none(&nfmt); 1320 1321 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1322 if (snd_mask_test(fmt, i)) { 1323 uint sbits = snd_pcm_format_width(i); 1324 int ppm; 1325 1326 if (rd->mcasp->slot_width) 1327 sbits = rd->mcasp->slot_width; 1328 1329 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, 1330 sbits * slots * rate, 1331 false); 1332 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1333 snd_mask_set(&nfmt, i); 1334 count++; 1335 } 1336 } 1337 } 1338 dev_dbg(rd->mcasp->dev, 1339 "%d possible sample format for %d Hz and %d tdm slots\n", 1340 count, rate, slots); 1341 1342 return snd_mask_refine(fmt, &nfmt); 1343 } 1344 1345 static int davinci_mcasp_hw_rule_min_periodsize( 1346 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1347 { 1348 struct snd_interval *period_size = hw_param_interval(params, 1349 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1350 struct snd_interval frames; 1351 1352 snd_interval_any(&frames); 1353 frames.min = 64; 1354 frames.integer = 1; 1355 1356 return snd_interval_refine(period_size, &frames); 1357 } 1358 1359 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1360 struct snd_soc_dai *cpu_dai) 1361 { 1362 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1363 struct davinci_mcasp_ruledata *ruledata = 1364 &mcasp->ruledata[substream->stream]; 1365 u32 max_channels = 0; 1366 int i, dir; 1367 int tdm_slots = mcasp->tdm_slots; 1368 1369 /* Do not allow more then one stream per direction */ 1370 if (mcasp->substreams[substream->stream]) 1371 return -EBUSY; 1372 1373 mcasp->substreams[substream->stream] = substream; 1374 1375 if (mcasp->tdm_mask[substream->stream]) 1376 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1377 1378 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1379 return 0; 1380 1381 /* 1382 * Limit the maximum allowed channels for the first stream: 1383 * number of serializers for the direction * tdm slots per serializer 1384 */ 1385 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1386 dir = TX_MODE; 1387 else 1388 dir = RX_MODE; 1389 1390 for (i = 0; i < mcasp->num_serializer; i++) { 1391 if (mcasp->serial_dir[i] == dir) 1392 max_channels++; 1393 } 1394 ruledata->serializers = max_channels; 1395 max_channels *= tdm_slots; 1396 /* 1397 * If the already active stream has less channels than the calculated 1398 * limnit based on the seirializers * tdm_slots, we need to use that as 1399 * a constraint for the second stream. 1400 * Otherwise (first stream or less allowed channels) we use the 1401 * calculated constraint. 1402 */ 1403 if (mcasp->channels && mcasp->channels < max_channels) 1404 max_channels = mcasp->channels; 1405 /* 1406 * But we can always allow channels upto the amount of 1407 * the available tdm_slots. 1408 */ 1409 if (max_channels < tdm_slots) 1410 max_channels = tdm_slots; 1411 1412 snd_pcm_hw_constraint_minmax(substream->runtime, 1413 SNDRV_PCM_HW_PARAM_CHANNELS, 1414 0, max_channels); 1415 1416 snd_pcm_hw_constraint_list(substream->runtime, 1417 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1418 &mcasp->chconstr[substream->stream]); 1419 1420 if (mcasp->slot_width) 1421 snd_pcm_hw_constraint_minmax(substream->runtime, 1422 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1423 8, mcasp->slot_width); 1424 1425 /* 1426 * If we rely on implicit BCLK divider setting we should 1427 * set constraints based on what we can provide. 1428 */ 1429 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1430 int ret; 1431 1432 ruledata->mcasp = mcasp; 1433 1434 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1435 SNDRV_PCM_HW_PARAM_RATE, 1436 davinci_mcasp_hw_rule_rate, 1437 ruledata, 1438 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1439 if (ret) 1440 return ret; 1441 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1442 SNDRV_PCM_HW_PARAM_FORMAT, 1443 davinci_mcasp_hw_rule_format, 1444 ruledata, 1445 SNDRV_PCM_HW_PARAM_RATE, -1); 1446 if (ret) 1447 return ret; 1448 } 1449 1450 snd_pcm_hw_rule_add(substream->runtime, 0, 1451 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1452 davinci_mcasp_hw_rule_min_periodsize, NULL, 1453 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1454 1455 return 0; 1456 } 1457 1458 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1459 struct snd_soc_dai *cpu_dai) 1460 { 1461 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1462 1463 mcasp->substreams[substream->stream] = NULL; 1464 1465 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1466 return; 1467 1468 if (!cpu_dai->active) 1469 mcasp->channels = 0; 1470 } 1471 1472 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1473 .startup = davinci_mcasp_startup, 1474 .shutdown = davinci_mcasp_shutdown, 1475 .trigger = davinci_mcasp_trigger, 1476 .delay = davinci_mcasp_delay, 1477 .hw_params = davinci_mcasp_hw_params, 1478 .set_fmt = davinci_mcasp_set_dai_fmt, 1479 .set_clkdiv = davinci_mcasp_set_clkdiv, 1480 .set_sysclk = davinci_mcasp_set_sysclk, 1481 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1482 }; 1483 1484 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1485 { 1486 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1487 1488 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1489 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 1490 1491 return 0; 1492 } 1493 1494 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1495 1496 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1497 SNDRV_PCM_FMTBIT_U8 | \ 1498 SNDRV_PCM_FMTBIT_S16_LE | \ 1499 SNDRV_PCM_FMTBIT_U16_LE | \ 1500 SNDRV_PCM_FMTBIT_S24_LE | \ 1501 SNDRV_PCM_FMTBIT_U24_LE | \ 1502 SNDRV_PCM_FMTBIT_S24_3LE | \ 1503 SNDRV_PCM_FMTBIT_U24_3LE | \ 1504 SNDRV_PCM_FMTBIT_S32_LE | \ 1505 SNDRV_PCM_FMTBIT_U32_LE) 1506 1507 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1508 { 1509 .name = "davinci-mcasp.0", 1510 .probe = davinci_mcasp_dai_probe, 1511 .playback = { 1512 .channels_min = 1, 1513 .channels_max = 32 * 16, 1514 .rates = DAVINCI_MCASP_RATES, 1515 .formats = DAVINCI_MCASP_PCM_FMTS, 1516 }, 1517 .capture = { 1518 .channels_min = 1, 1519 .channels_max = 32 * 16, 1520 .rates = DAVINCI_MCASP_RATES, 1521 .formats = DAVINCI_MCASP_PCM_FMTS, 1522 }, 1523 .ops = &davinci_mcasp_dai_ops, 1524 1525 .symmetric_samplebits = 1, 1526 .symmetric_rates = 1, 1527 }, 1528 { 1529 .name = "davinci-mcasp.1", 1530 .probe = davinci_mcasp_dai_probe, 1531 .playback = { 1532 .channels_min = 1, 1533 .channels_max = 384, 1534 .rates = DAVINCI_MCASP_RATES, 1535 .formats = DAVINCI_MCASP_PCM_FMTS, 1536 }, 1537 .ops = &davinci_mcasp_dai_ops, 1538 }, 1539 1540 }; 1541 1542 static const struct snd_soc_component_driver davinci_mcasp_component = { 1543 .name = "davinci-mcasp", 1544 }; 1545 1546 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1547 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1548 .tx_dma_offset = 0x400, 1549 .rx_dma_offset = 0x400, 1550 .version = MCASP_VERSION_1, 1551 }; 1552 1553 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1554 .tx_dma_offset = 0x2000, 1555 .rx_dma_offset = 0x2000, 1556 .version = MCASP_VERSION_2, 1557 }; 1558 1559 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1560 .tx_dma_offset = 0, 1561 .rx_dma_offset = 0, 1562 .version = MCASP_VERSION_3, 1563 }; 1564 1565 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1566 /* The CFG port offset will be calculated if it is needed */ 1567 .tx_dma_offset = 0, 1568 .rx_dma_offset = 0, 1569 .version = MCASP_VERSION_4, 1570 }; 1571 1572 static const struct of_device_id mcasp_dt_ids[] = { 1573 { 1574 .compatible = "ti,dm646x-mcasp-audio", 1575 .data = &dm646x_mcasp_pdata, 1576 }, 1577 { 1578 .compatible = "ti,da830-mcasp-audio", 1579 .data = &da830_mcasp_pdata, 1580 }, 1581 { 1582 .compatible = "ti,am33xx-mcasp-audio", 1583 .data = &am33xx_mcasp_pdata, 1584 }, 1585 { 1586 .compatible = "ti,dra7-mcasp-audio", 1587 .data = &dra7_mcasp_pdata, 1588 }, 1589 { /* sentinel */ } 1590 }; 1591 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1592 1593 static int mcasp_reparent_fck(struct platform_device *pdev) 1594 { 1595 struct device_node *node = pdev->dev.of_node; 1596 struct clk *gfclk, *parent_clk; 1597 const char *parent_name; 1598 int ret; 1599 1600 if (!node) 1601 return 0; 1602 1603 parent_name = of_get_property(node, "fck_parent", NULL); 1604 if (!parent_name) 1605 return 0; 1606 1607 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1608 1609 gfclk = clk_get(&pdev->dev, "fck"); 1610 if (IS_ERR(gfclk)) { 1611 dev_err(&pdev->dev, "failed to get fck\n"); 1612 return PTR_ERR(gfclk); 1613 } 1614 1615 parent_clk = clk_get(NULL, parent_name); 1616 if (IS_ERR(parent_clk)) { 1617 dev_err(&pdev->dev, "failed to get parent clock\n"); 1618 ret = PTR_ERR(parent_clk); 1619 goto err1; 1620 } 1621 1622 ret = clk_set_parent(gfclk, parent_clk); 1623 if (ret) { 1624 dev_err(&pdev->dev, "failed to reparent fck\n"); 1625 goto err2; 1626 } 1627 1628 err2: 1629 clk_put(parent_clk); 1630 err1: 1631 clk_put(gfclk); 1632 return ret; 1633 } 1634 1635 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( 1636 struct platform_device *pdev) 1637 { 1638 struct device_node *np = pdev->dev.of_node; 1639 struct davinci_mcasp_pdata *pdata = NULL; 1640 const struct of_device_id *match = 1641 of_match_device(mcasp_dt_ids, &pdev->dev); 1642 struct of_phandle_args dma_spec; 1643 1644 const u32 *of_serial_dir32; 1645 u32 val; 1646 int i, ret = 0; 1647 1648 if (pdev->dev.platform_data) { 1649 pdata = pdev->dev.platform_data; 1650 pdata->dismod = DISMOD_LOW; 1651 return pdata; 1652 } else if (match) { 1653 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), 1654 GFP_KERNEL); 1655 if (!pdata) { 1656 ret = -ENOMEM; 1657 return pdata; 1658 } 1659 } else { 1660 /* control shouldn't reach here. something is wrong */ 1661 ret = -EINVAL; 1662 goto nodata; 1663 } 1664 1665 ret = of_property_read_u32(np, "op-mode", &val); 1666 if (ret >= 0) 1667 pdata->op_mode = val; 1668 1669 ret = of_property_read_u32(np, "tdm-slots", &val); 1670 if (ret >= 0) { 1671 if (val < 2 || val > 32) { 1672 dev_err(&pdev->dev, 1673 "tdm-slots must be in rage [2-32]\n"); 1674 ret = -EINVAL; 1675 goto nodata; 1676 } 1677 1678 pdata->tdm_slots = val; 1679 } 1680 1681 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1682 val /= sizeof(u32); 1683 if (of_serial_dir32) { 1684 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1685 (sizeof(*of_serial_dir) * val), 1686 GFP_KERNEL); 1687 if (!of_serial_dir) { 1688 ret = -ENOMEM; 1689 goto nodata; 1690 } 1691 1692 for (i = 0; i < val; i++) 1693 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1694 1695 pdata->num_serializer = val; 1696 pdata->serial_dir = of_serial_dir; 1697 } 1698 1699 ret = of_property_match_string(np, "dma-names", "tx"); 1700 if (ret < 0) 1701 goto nodata; 1702 1703 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1704 &dma_spec); 1705 if (ret < 0) 1706 goto nodata; 1707 1708 pdata->tx_dma_channel = dma_spec.args[0]; 1709 1710 /* RX is not valid in DIT mode */ 1711 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { 1712 ret = of_property_match_string(np, "dma-names", "rx"); 1713 if (ret < 0) 1714 goto nodata; 1715 1716 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1717 &dma_spec); 1718 if (ret < 0) 1719 goto nodata; 1720 1721 pdata->rx_dma_channel = dma_spec.args[0]; 1722 } 1723 1724 ret = of_property_read_u32(np, "tx-num-evt", &val); 1725 if (ret >= 0) 1726 pdata->txnumevt = val; 1727 1728 ret = of_property_read_u32(np, "rx-num-evt", &val); 1729 if (ret >= 0) 1730 pdata->rxnumevt = val; 1731 1732 ret = of_property_read_u32(np, "sram-size-playback", &val); 1733 if (ret >= 0) 1734 pdata->sram_size_playback = val; 1735 1736 ret = of_property_read_u32(np, "sram-size-capture", &val); 1737 if (ret >= 0) 1738 pdata->sram_size_capture = val; 1739 1740 ret = of_property_read_u32(np, "dismod", &val); 1741 if (ret >= 0) { 1742 if (val == 0 || val == 2 || val == 3) { 1743 pdata->dismod = DISMOD_VAL(val); 1744 } else { 1745 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1746 pdata->dismod = DISMOD_LOW; 1747 } 1748 } else { 1749 pdata->dismod = DISMOD_LOW; 1750 } 1751 1752 return pdata; 1753 1754 nodata: 1755 if (ret < 0) { 1756 dev_err(&pdev->dev, "Error populating platform data, err %d\n", 1757 ret); 1758 pdata = NULL; 1759 } 1760 return pdata; 1761 } 1762 1763 enum { 1764 PCM_EDMA, 1765 PCM_SDMA, 1766 }; 1767 static const char *sdma_prefix = "ti,omap"; 1768 1769 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 1770 { 1771 struct dma_chan *chan; 1772 const char *tmp; 1773 int ret = PCM_EDMA; 1774 1775 if (!mcasp->dev->of_node) 1776 return PCM_EDMA; 1777 1778 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 1779 chan = dma_request_slave_channel_reason(mcasp->dev, tmp); 1780 if (IS_ERR(chan)) { 1781 if (PTR_ERR(chan) != -EPROBE_DEFER) 1782 dev_err(mcasp->dev, 1783 "Can't verify DMA configuration (%ld)\n", 1784 PTR_ERR(chan)); 1785 return PTR_ERR(chan); 1786 } 1787 if (WARN_ON(!chan->device || !chan->device->dev)) 1788 return -EINVAL; 1789 1790 if (chan->device->dev->of_node) 1791 ret = of_property_read_string(chan->device->dev->of_node, 1792 "compatible", &tmp); 1793 else 1794 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 1795 1796 dma_release_channel(chan); 1797 if (ret) 1798 return ret; 1799 1800 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 1801 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 1802 return PCM_SDMA; 1803 1804 return PCM_EDMA; 1805 } 1806 1807 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 1808 { 1809 int i; 1810 u32 offset = 0; 1811 1812 if (pdata->version != MCASP_VERSION_4) 1813 return pdata->tx_dma_offset; 1814 1815 for (i = 0; i < pdata->num_serializer; i++) { 1816 if (pdata->serial_dir[i] == TX_MODE) { 1817 if (!offset) { 1818 offset = DAVINCI_MCASP_TXBUF_REG(i); 1819 } else { 1820 pr_err("%s: Only one serializer allowed!\n", 1821 __func__); 1822 break; 1823 } 1824 } 1825 } 1826 1827 return offset; 1828 } 1829 1830 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 1831 { 1832 int i; 1833 u32 offset = 0; 1834 1835 if (pdata->version != MCASP_VERSION_4) 1836 return pdata->rx_dma_offset; 1837 1838 for (i = 0; i < pdata->num_serializer; i++) { 1839 if (pdata->serial_dir[i] == RX_MODE) { 1840 if (!offset) { 1841 offset = DAVINCI_MCASP_RXBUF_REG(i); 1842 } else { 1843 pr_err("%s: Only one serializer allowed!\n", 1844 __func__); 1845 break; 1846 } 1847 } 1848 } 1849 1850 return offset; 1851 } 1852 1853 #ifdef CONFIG_GPIOLIB 1854 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 1855 { 1856 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1857 1858 if (mcasp->num_serializer && offset < mcasp->num_serializer && 1859 mcasp->serial_dir[offset] != INACTIVE_MODE) { 1860 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 1861 return -EBUSY; 1862 } 1863 1864 /* Do not change the PIN yet */ 1865 1866 return pm_runtime_get_sync(mcasp->dev); 1867 } 1868 1869 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 1870 { 1871 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1872 1873 /* Set the direction to input */ 1874 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1875 1876 /* Set the pin as McASP pin */ 1877 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1878 1879 pm_runtime_put_sync(mcasp->dev); 1880 } 1881 1882 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 1883 unsigned offset, int value) 1884 { 1885 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1886 u32 val; 1887 1888 if (value) 1889 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1890 else 1891 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1892 1893 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 1894 if (!(val & BIT(offset))) { 1895 /* Set the pin as GPIO pin */ 1896 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1897 1898 /* Set the direction to output */ 1899 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1900 } 1901 1902 return 0; 1903 } 1904 1905 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, 1906 int value) 1907 { 1908 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1909 1910 if (value) 1911 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1912 else 1913 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1914 } 1915 1916 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 1917 unsigned offset) 1918 { 1919 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1920 u32 val; 1921 1922 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 1923 if (!(val & BIT(offset))) { 1924 /* Set the direction to input */ 1925 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1926 1927 /* Set the pin as GPIO pin */ 1928 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1929 } 1930 1931 return 0; 1932 } 1933 1934 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 1935 { 1936 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1937 u32 val; 1938 1939 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 1940 if (val & BIT(offset)) 1941 return 1; 1942 1943 return 0; 1944 } 1945 1946 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 1947 unsigned offset) 1948 { 1949 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1950 u32 val; 1951 1952 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 1953 if (val & BIT(offset)) 1954 return 0; 1955 1956 return 1; 1957 } 1958 1959 static const struct gpio_chip davinci_mcasp_template_chip = { 1960 .owner = THIS_MODULE, 1961 .request = davinci_mcasp_gpio_request, 1962 .free = davinci_mcasp_gpio_free, 1963 .direction_output = davinci_mcasp_gpio_direction_out, 1964 .set = davinci_mcasp_gpio_set, 1965 .direction_input = davinci_mcasp_gpio_direction_in, 1966 .get = davinci_mcasp_gpio_get, 1967 .get_direction = davinci_mcasp_gpio_get_direction, 1968 .base = -1, 1969 .ngpio = 32, 1970 }; 1971 1972 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 1973 { 1974 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) 1975 return 0; 1976 1977 mcasp->gpio_chip = davinci_mcasp_template_chip; 1978 mcasp->gpio_chip.label = dev_name(mcasp->dev); 1979 mcasp->gpio_chip.parent = mcasp->dev; 1980 #ifdef CONFIG_OF_GPIO 1981 mcasp->gpio_chip.of_node = mcasp->dev->of_node; 1982 #endif 1983 1984 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 1985 } 1986 1987 #else /* CONFIG_GPIOLIB */ 1988 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 1989 { 1990 return 0; 1991 } 1992 #endif /* CONFIG_GPIOLIB */ 1993 1994 static int davinci_mcasp_probe(struct platform_device *pdev) 1995 { 1996 struct snd_dmaengine_dai_dma_data *dma_data; 1997 struct resource *mem, *res, *dat; 1998 struct davinci_mcasp_pdata *pdata; 1999 struct davinci_mcasp *mcasp; 2000 char *irq_name; 2001 int *dma; 2002 int irq; 2003 int ret; 2004 2005 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2006 dev_err(&pdev->dev, "No platform data supplied\n"); 2007 return -EINVAL; 2008 } 2009 2010 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2011 GFP_KERNEL); 2012 if (!mcasp) 2013 return -ENOMEM; 2014 2015 pdata = davinci_mcasp_set_pdata_from_of(pdev); 2016 if (!pdata) { 2017 dev_err(&pdev->dev, "no platform data\n"); 2018 return -EINVAL; 2019 } 2020 2021 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2022 if (!mem) { 2023 dev_warn(mcasp->dev, 2024 "\"mpu\" mem resource not found, using index 0\n"); 2025 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2026 if (!mem) { 2027 dev_err(&pdev->dev, "no mem resource?\n"); 2028 return -ENODEV; 2029 } 2030 } 2031 2032 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2033 if (IS_ERR(mcasp->base)) 2034 return PTR_ERR(mcasp->base); 2035 2036 pm_runtime_enable(&pdev->dev); 2037 2038 mcasp->op_mode = pdata->op_mode; 2039 /* sanity check for tdm slots parameter */ 2040 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2041 if (pdata->tdm_slots < 2) { 2042 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2043 pdata->tdm_slots); 2044 mcasp->tdm_slots = 2; 2045 } else if (pdata->tdm_slots > 32) { 2046 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2047 pdata->tdm_slots); 2048 mcasp->tdm_slots = 32; 2049 } else { 2050 mcasp->tdm_slots = pdata->tdm_slots; 2051 } 2052 } 2053 2054 mcasp->num_serializer = pdata->num_serializer; 2055 #ifdef CONFIG_PM 2056 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2057 mcasp->num_serializer, sizeof(u32), 2058 GFP_KERNEL); 2059 if (!mcasp->context.xrsr_regs) { 2060 ret = -ENOMEM; 2061 goto err; 2062 } 2063 #endif 2064 mcasp->serial_dir = pdata->serial_dir; 2065 mcasp->version = pdata->version; 2066 mcasp->txnumevt = pdata->txnumevt; 2067 mcasp->rxnumevt = pdata->rxnumevt; 2068 mcasp->dismod = pdata->dismod; 2069 2070 mcasp->dev = &pdev->dev; 2071 2072 irq = platform_get_irq_byname(pdev, "common"); 2073 if (irq >= 0) { 2074 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2075 dev_name(&pdev->dev)); 2076 if (!irq_name) { 2077 ret = -ENOMEM; 2078 goto err; 2079 } 2080 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2081 davinci_mcasp_common_irq_handler, 2082 IRQF_ONESHOT | IRQF_SHARED, 2083 irq_name, mcasp); 2084 if (ret) { 2085 dev_err(&pdev->dev, "common IRQ request failed\n"); 2086 goto err; 2087 } 2088 2089 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2090 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2091 } 2092 2093 irq = platform_get_irq_byname(pdev, "rx"); 2094 if (irq >= 0) { 2095 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2096 dev_name(&pdev->dev)); 2097 if (!irq_name) { 2098 ret = -ENOMEM; 2099 goto err; 2100 } 2101 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2102 davinci_mcasp_rx_irq_handler, 2103 IRQF_ONESHOT, irq_name, mcasp); 2104 if (ret) { 2105 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2106 goto err; 2107 } 2108 2109 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2110 } 2111 2112 irq = platform_get_irq_byname(pdev, "tx"); 2113 if (irq >= 0) { 2114 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2115 dev_name(&pdev->dev)); 2116 if (!irq_name) { 2117 ret = -ENOMEM; 2118 goto err; 2119 } 2120 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2121 davinci_mcasp_tx_irq_handler, 2122 IRQF_ONESHOT, irq_name, mcasp); 2123 if (ret) { 2124 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2125 goto err; 2126 } 2127 2128 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2129 } 2130 2131 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2132 if (dat) 2133 mcasp->dat_port = true; 2134 2135 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2136 if (dat) 2137 dma_data->addr = dat->start; 2138 else 2139 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); 2140 2141 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; 2142 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 2143 if (res) 2144 *dma = res->start; 2145 else 2146 *dma = pdata->tx_dma_channel; 2147 2148 /* dmaengine filter data for DT and non-DT boot */ 2149 if (pdev->dev.of_node) 2150 dma_data->filter_data = "tx"; 2151 else 2152 dma_data->filter_data = dma; 2153 2154 /* RX is not valid in DIT mode */ 2155 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2156 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2157 if (dat) 2158 dma_data->addr = dat->start; 2159 else 2160 dma_data->addr = 2161 mem->start + davinci_mcasp_rxdma_offset(pdata); 2162 2163 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; 2164 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 2165 if (res) 2166 *dma = res->start; 2167 else 2168 *dma = pdata->rx_dma_channel; 2169 2170 /* dmaengine filter data for DT and non-DT boot */ 2171 if (pdev->dev.of_node) 2172 dma_data->filter_data = "rx"; 2173 else 2174 dma_data->filter_data = dma; 2175 } 2176 2177 if (mcasp->version < MCASP_VERSION_3) { 2178 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2179 /* dma_params->dma_addr is pointing to the data port address */ 2180 mcasp->dat_port = true; 2181 } else { 2182 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2183 } 2184 2185 /* Allocate memory for long enough list for all possible 2186 * scenarios. Maximum number tdm slots is 32 and there cannot 2187 * be more serializers than given in the configuration. The 2188 * serializer directions could be taken into account, but it 2189 * would make code much more complex and save only couple of 2190 * bytes. 2191 */ 2192 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2193 devm_kcalloc(mcasp->dev, 2194 32 + mcasp->num_serializer - 1, 2195 sizeof(unsigned int), 2196 GFP_KERNEL); 2197 2198 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2199 devm_kcalloc(mcasp->dev, 2200 32 + mcasp->num_serializer - 1, 2201 sizeof(unsigned int), 2202 GFP_KERNEL); 2203 2204 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2205 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2206 ret = -ENOMEM; 2207 goto err; 2208 } 2209 2210 ret = davinci_mcasp_set_ch_constraints(mcasp); 2211 if (ret) 2212 goto err; 2213 2214 dev_set_drvdata(&pdev->dev, mcasp); 2215 2216 mcasp_reparent_fck(pdev); 2217 2218 /* All PINS as McASP */ 2219 pm_runtime_get_sync(mcasp->dev); 2220 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2221 pm_runtime_put(mcasp->dev); 2222 2223 ret = davinci_mcasp_init_gpiochip(mcasp); 2224 if (ret) 2225 goto err; 2226 2227 ret = devm_snd_soc_register_component(&pdev->dev, 2228 &davinci_mcasp_component, 2229 &davinci_mcasp_dai[pdata->op_mode], 1); 2230 2231 if (ret != 0) 2232 goto err; 2233 2234 ret = davinci_mcasp_get_dma_type(mcasp); 2235 switch (ret) { 2236 case PCM_EDMA: 2237 ret = edma_pcm_platform_register(&pdev->dev); 2238 break; 2239 case PCM_SDMA: 2240 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL); 2241 break; 2242 default: 2243 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2244 case -EPROBE_DEFER: 2245 goto err; 2246 break; 2247 } 2248 2249 if (ret) { 2250 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2251 goto err; 2252 } 2253 2254 return 0; 2255 2256 err: 2257 pm_runtime_disable(&pdev->dev); 2258 return ret; 2259 } 2260 2261 static int davinci_mcasp_remove(struct platform_device *pdev) 2262 { 2263 pm_runtime_disable(&pdev->dev); 2264 2265 return 0; 2266 } 2267 2268 #ifdef CONFIG_PM 2269 static int davinci_mcasp_runtime_suspend(struct device *dev) 2270 { 2271 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2272 struct davinci_mcasp_context *context = &mcasp->context; 2273 u32 reg; 2274 int i; 2275 2276 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2277 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2278 2279 if (mcasp->txnumevt) { 2280 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2281 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2282 } 2283 if (mcasp->rxnumevt) { 2284 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2285 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2286 } 2287 2288 for (i = 0; i < mcasp->num_serializer; i++) 2289 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2290 DAVINCI_MCASP_XRSRCTL_REG(i)); 2291 2292 return 0; 2293 } 2294 2295 static int davinci_mcasp_runtime_resume(struct device *dev) 2296 { 2297 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2298 struct davinci_mcasp_context *context = &mcasp->context; 2299 u32 reg; 2300 int i; 2301 2302 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2303 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2304 2305 if (mcasp->txnumevt) { 2306 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2307 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2308 } 2309 if (mcasp->rxnumevt) { 2310 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2311 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2312 } 2313 2314 for (i = 0; i < mcasp->num_serializer; i++) 2315 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2316 context->xrsr_regs[i]); 2317 2318 return 0; 2319 } 2320 2321 #endif 2322 2323 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2324 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2325 davinci_mcasp_runtime_resume, 2326 NULL) 2327 }; 2328 2329 static struct platform_driver davinci_mcasp_driver = { 2330 .probe = davinci_mcasp_probe, 2331 .remove = davinci_mcasp_remove, 2332 .driver = { 2333 .name = "davinci-mcasp", 2334 .pm = &davinci_mcasp_pm_ops, 2335 .of_match_table = mcasp_dt_ids, 2336 }, 2337 }; 2338 2339 module_platform_driver(davinci_mcasp_driver); 2340 2341 MODULE_AUTHOR("Steve Chen"); 2342 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2343 MODULE_LICENSE("GPL"); 2344