1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_data/davinci_asp.h> 27 #include <linux/math64.h> 28 #include <linux/bitmap.h> 29 #include <linux/gpio/driver.h> 30 31 #include <sound/asoundef.h> 32 #include <sound/core.h> 33 #include <sound/pcm.h> 34 #include <sound/pcm_params.h> 35 #include <sound/initval.h> 36 #include <sound/soc.h> 37 #include <sound/dmaengine_pcm.h> 38 39 #include "edma-pcm.h" 40 #include "sdma-pcm.h" 41 #include "udma-pcm.h" 42 #include "davinci-mcasp.h" 43 44 #define MCASP_MAX_AFIFO_DEPTH 64 45 46 #ifdef CONFIG_PM 47 static u32 context_regs[] = { 48 DAVINCI_MCASP_TXFMCTL_REG, 49 DAVINCI_MCASP_RXFMCTL_REG, 50 DAVINCI_MCASP_TXFMT_REG, 51 DAVINCI_MCASP_RXFMT_REG, 52 DAVINCI_MCASP_ACLKXCTL_REG, 53 DAVINCI_MCASP_ACLKRCTL_REG, 54 DAVINCI_MCASP_AHCLKXCTL_REG, 55 DAVINCI_MCASP_AHCLKRCTL_REG, 56 DAVINCI_MCASP_PDIR_REG, 57 DAVINCI_MCASP_PFUNC_REG, 58 DAVINCI_MCASP_RXMASK_REG, 59 DAVINCI_MCASP_TXMASK_REG, 60 DAVINCI_MCASP_RXTDM_REG, 61 DAVINCI_MCASP_TXTDM_REG, 62 }; 63 64 struct davinci_mcasp_context { 65 u32 config_regs[ARRAY_SIZE(context_regs)]; 66 u32 afifo_regs[2]; /* for read/write fifo control registers */ 67 u32 *xrsr_regs; /* for serializer configuration */ 68 bool pm_state; 69 }; 70 #endif 71 72 struct davinci_mcasp_ruledata { 73 struct davinci_mcasp *mcasp; 74 int serializers; 75 }; 76 77 struct davinci_mcasp { 78 struct snd_dmaengine_dai_dma_data dma_data[2]; 79 struct davinci_mcasp_pdata *pdata; 80 void __iomem *base; 81 u32 fifo_base; 82 struct device *dev; 83 struct snd_pcm_substream *substreams[2]; 84 unsigned int dai_fmt; 85 86 /* Audio can not be enabled due to missing parameter(s) */ 87 bool missing_audio_param; 88 89 /* McASP specific data */ 90 int tdm_slots; 91 u32 tdm_mask[2]; 92 int slot_width; 93 u8 op_mode; 94 u8 dismod; 95 u8 num_serializer; 96 u8 *serial_dir; 97 u8 version; 98 u8 bclk_div; 99 int streams; 100 u32 irq_request[2]; 101 102 int sysclk_freq; 103 bool bclk_master; 104 u32 auxclk_fs_ratio; 105 106 unsigned long pdir; /* Pin direction bitfield */ 107 108 /* McASP FIFO related */ 109 u8 txnumevt; 110 u8 rxnumevt; 111 112 bool dat_port; 113 114 /* Used for comstraint setting on the second stream */ 115 u32 channels; 116 int max_format_width; 117 u8 active_serializers[2]; 118 119 #ifdef CONFIG_GPIOLIB 120 struct gpio_chip gpio_chip; 121 #endif 122 123 #ifdef CONFIG_PM 124 struct davinci_mcasp_context context; 125 #endif 126 127 struct davinci_mcasp_ruledata ruledata[2]; 128 struct snd_pcm_hw_constraint_list chconstr[2]; 129 }; 130 131 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 132 u32 val) 133 { 134 void __iomem *reg = mcasp->base + offset; 135 __raw_writel(__raw_readl(reg) | val, reg); 136 } 137 138 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 139 u32 val) 140 { 141 void __iomem *reg = mcasp->base + offset; 142 __raw_writel((__raw_readl(reg) & ~(val)), reg); 143 } 144 145 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 146 u32 val, u32 mask) 147 { 148 void __iomem *reg = mcasp->base + offset; 149 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 150 } 151 152 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 153 u32 val) 154 { 155 __raw_writel(val, mcasp->base + offset); 156 } 157 158 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 159 { 160 return (u32)__raw_readl(mcasp->base + offset); 161 } 162 163 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 164 { 165 int i = 0; 166 167 mcasp_set_bits(mcasp, ctl_reg, val); 168 169 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 170 /* loop count is to avoid the lock-up */ 171 for (i = 0; i < 1000; i++) { 172 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 173 break; 174 } 175 176 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 177 printk(KERN_ERR "GBLCTL write error\n"); 178 } 179 180 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 181 { 182 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 183 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 184 185 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 186 } 187 188 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 189 { 190 u32 bit = PIN_BIT_AMUTE; 191 192 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 193 if (enable) 194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 195 else 196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 197 } 198 } 199 200 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 201 { 202 u32 bit; 203 204 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { 205 if (enable) 206 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 207 else 208 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 209 } 210 } 211 212 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 213 { 214 if (mcasp->rxnumevt) { /* enable FIFO */ 215 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 216 217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 219 } 220 221 /* Start clocks */ 222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 224 /* 225 * When ASYNC == 0 the transmit and receive sections operate 226 * synchronously from the transmit clock and frame sync. We need to make 227 * sure that the TX signlas are enabled when starting reception. 228 */ 229 if (mcasp_is_synchronous(mcasp)) { 230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 232 mcasp_set_clk_pdir(mcasp, true); 233 } 234 235 /* Activate serializer(s) */ 236 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 238 /* Release RX state machine */ 239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 240 /* Release Frame Sync generator */ 241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 242 if (mcasp_is_synchronous(mcasp)) 243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 244 245 /* enable receive IRQs */ 246 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 247 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 248 } 249 250 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 251 { 252 u32 cnt; 253 254 if (mcasp->txnumevt) { /* enable FIFO */ 255 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 256 257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 258 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 259 } 260 261 /* Start clocks */ 262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 263 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 264 mcasp_set_clk_pdir(mcasp, true); 265 266 /* Activate serializer(s) */ 267 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 269 270 /* wait for XDATA to be cleared */ 271 cnt = 0; 272 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 273 (cnt < 100000)) 274 cnt++; 275 276 mcasp_set_axr_pdir(mcasp, true); 277 278 /* Release TX state machine */ 279 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 280 /* Release Frame Sync generator */ 281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 282 283 /* enable transmit IRQs */ 284 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 285 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 286 } 287 288 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 289 { 290 mcasp->streams++; 291 292 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 293 mcasp_start_tx(mcasp); 294 else 295 mcasp_start_rx(mcasp); 296 } 297 298 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 299 { 300 /* disable IRQ sources */ 301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 302 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 303 304 /* 305 * In synchronous mode stop the TX clocks if no other stream is 306 * running 307 */ 308 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 309 mcasp_set_clk_pdir(mcasp, false); 310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 311 } 312 313 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 314 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 315 316 if (mcasp->rxnumevt) { /* disable FIFO */ 317 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 318 319 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 320 } 321 } 322 323 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 324 { 325 u32 val = 0; 326 327 /* disable IRQ sources */ 328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 329 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 330 331 /* 332 * In synchronous mode keep TX clocks running if the capture stream is 333 * still running. 334 */ 335 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 336 val = TXHCLKRST | TXCLKRST | TXFSRST; 337 else 338 mcasp_set_clk_pdir(mcasp, false); 339 340 341 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 342 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 343 344 if (mcasp->txnumevt) { /* disable FIFO */ 345 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 346 347 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 348 } 349 350 mcasp_set_axr_pdir(mcasp, false); 351 } 352 353 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 354 { 355 mcasp->streams--; 356 357 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 358 mcasp_stop_tx(mcasp); 359 else 360 mcasp_stop_rx(mcasp); 361 } 362 363 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 364 { 365 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 366 struct snd_pcm_substream *substream; 367 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 368 u32 handled_mask = 0; 369 u32 stat; 370 371 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 372 if (stat & XUNDRN & irq_mask) { 373 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 374 handled_mask |= XUNDRN; 375 376 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 377 if (substream) 378 snd_pcm_stop_xrun(substream); 379 } 380 381 if (!handled_mask) 382 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 383 stat); 384 385 if (stat & XRERR) 386 handled_mask |= XRERR; 387 388 /* Ack the handled event only */ 389 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 390 391 return IRQ_RETVAL(handled_mask); 392 } 393 394 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 395 { 396 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 397 struct snd_pcm_substream *substream; 398 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 399 u32 handled_mask = 0; 400 u32 stat; 401 402 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 403 if (stat & ROVRN & irq_mask) { 404 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 405 handled_mask |= ROVRN; 406 407 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 408 if (substream) 409 snd_pcm_stop_xrun(substream); 410 } 411 412 if (!handled_mask) 413 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 414 stat); 415 416 if (stat & XRERR) 417 handled_mask |= XRERR; 418 419 /* Ack the handled event only */ 420 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 421 422 return IRQ_RETVAL(handled_mask); 423 } 424 425 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 426 { 427 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 428 irqreturn_t ret = IRQ_NONE; 429 430 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 431 ret = davinci_mcasp_tx_irq_handler(irq, data); 432 433 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 434 ret |= davinci_mcasp_rx_irq_handler(irq, data); 435 436 return ret; 437 } 438 439 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 440 unsigned int fmt) 441 { 442 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 443 int ret = 0; 444 u32 data_delay; 445 bool fs_pol_rising; 446 bool inv_fs = false; 447 448 if (!fmt) 449 return 0; 450 451 pm_runtime_get_sync(mcasp->dev); 452 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 453 case SND_SOC_DAIFMT_DSP_A: 454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 456 /* 1st data bit occur one ACLK cycle after the frame sync */ 457 data_delay = 1; 458 break; 459 case SND_SOC_DAIFMT_DSP_B: 460 case SND_SOC_DAIFMT_AC97: 461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 463 /* No delay after FS */ 464 data_delay = 0; 465 break; 466 case SND_SOC_DAIFMT_I2S: 467 /* configure a full-word SYNC pulse (LRCLK) */ 468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 470 /* 1st data bit occur one ACLK cycle after the frame sync */ 471 data_delay = 1; 472 /* FS need to be inverted */ 473 inv_fs = true; 474 break; 475 case SND_SOC_DAIFMT_RIGHT_J: 476 case SND_SOC_DAIFMT_LEFT_J: 477 /* configure a full-word SYNC pulse (LRCLK) */ 478 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 480 /* No delay after FS */ 481 data_delay = 0; 482 break; 483 default: 484 ret = -EINVAL; 485 goto out; 486 } 487 488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 489 FSXDLY(3)); 490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 491 FSRDLY(3)); 492 493 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 494 case SND_SOC_DAIFMT_CBS_CFS: 495 /* codec is clock and frame slave */ 496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 497 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 498 499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 500 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 501 502 /* BCLK */ 503 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 504 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 505 /* Frame Sync */ 506 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 507 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 508 509 mcasp->bclk_master = 1; 510 break; 511 case SND_SOC_DAIFMT_CBS_CFM: 512 /* codec is clock slave and frame master */ 513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 515 516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 517 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 518 519 /* BCLK */ 520 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 521 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 522 /* Frame Sync */ 523 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 524 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 525 526 mcasp->bclk_master = 1; 527 break; 528 case SND_SOC_DAIFMT_CBM_CFS: 529 /* codec is clock master and frame slave */ 530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 532 533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 534 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 535 536 /* BCLK */ 537 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 538 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 539 /* Frame Sync */ 540 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 541 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 542 543 mcasp->bclk_master = 0; 544 break; 545 case SND_SOC_DAIFMT_CBM_CFM: 546 /* codec is clock and frame master */ 547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 549 550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 551 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 552 553 /* BCLK */ 554 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 555 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 556 /* Frame Sync */ 557 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 558 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 559 560 mcasp->bclk_master = 0; 561 break; 562 default: 563 ret = -EINVAL; 564 goto out; 565 } 566 567 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 568 case SND_SOC_DAIFMT_IB_NF: 569 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 570 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 571 fs_pol_rising = true; 572 break; 573 case SND_SOC_DAIFMT_NB_IF: 574 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 575 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 576 fs_pol_rising = false; 577 break; 578 case SND_SOC_DAIFMT_IB_IF: 579 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 580 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 581 fs_pol_rising = false; 582 break; 583 case SND_SOC_DAIFMT_NB_NF: 584 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 585 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 586 fs_pol_rising = true; 587 break; 588 default: 589 ret = -EINVAL; 590 goto out; 591 } 592 593 if (inv_fs) 594 fs_pol_rising = !fs_pol_rising; 595 596 if (fs_pol_rising) { 597 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 598 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 599 } else { 600 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 601 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 602 } 603 604 mcasp->dai_fmt = fmt; 605 out: 606 pm_runtime_put(mcasp->dev); 607 return ret; 608 } 609 610 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 611 int div, bool explicit) 612 { 613 pm_runtime_get_sync(mcasp->dev); 614 switch (div_id) { 615 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 617 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 619 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 620 break; 621 622 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 623 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 624 ACLKXDIV(div - 1), ACLKXDIV_MASK); 625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 626 ACLKRDIV(div - 1), ACLKRDIV_MASK); 627 if (explicit) 628 mcasp->bclk_div = div; 629 break; 630 631 case MCASP_CLKDIV_BCLK_FS_RATIO: 632 /* 633 * BCLK/LRCLK ratio descries how many bit-clock cycles 634 * fit into one frame. The clock ratio is given for a 635 * full period of data (for I2S format both left and 636 * right channels), so it has to be divided by number 637 * of tdm-slots (for I2S - divided by 2). 638 * Instead of storing this ratio, we calculate a new 639 * tdm_slot width by dividing the ratio by the 640 * number of configured tdm slots. 641 */ 642 mcasp->slot_width = div / mcasp->tdm_slots; 643 if (div % mcasp->tdm_slots) 644 dev_warn(mcasp->dev, 645 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 646 __func__, div, mcasp->tdm_slots); 647 break; 648 649 default: 650 return -EINVAL; 651 } 652 653 pm_runtime_put(mcasp->dev); 654 return 0; 655 } 656 657 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 658 int div) 659 { 660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 661 662 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 663 } 664 665 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 666 unsigned int freq, int dir) 667 { 668 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 669 670 pm_runtime_get_sync(mcasp->dev); 671 672 if (dir == SND_SOC_CLOCK_IN) { 673 switch (clk_id) { 674 case MCASP_CLK_HCLK_AHCLK: 675 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 676 AHCLKXE); 677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 678 AHCLKRE); 679 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 680 break; 681 case MCASP_CLK_HCLK_AUXCLK: 682 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 683 AHCLKXE); 684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 685 AHCLKRE); 686 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 687 break; 688 default: 689 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); 690 goto out; 691 } 692 } else { 693 /* Select AUXCLK as HCLK */ 694 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 695 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 696 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 697 } 698 /* 699 * When AHCLK X/R is selected to be output it means that the HCLK is 700 * the same clock - coming via AUXCLK. 701 */ 702 mcasp->sysclk_freq = freq; 703 out: 704 pm_runtime_put(mcasp->dev); 705 return 0; 706 } 707 708 /* All serializers must have equal number of channels */ 709 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 710 int serializers) 711 { 712 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 713 unsigned int *list = (unsigned int *) cl->list; 714 int slots = mcasp->tdm_slots; 715 int i, count = 0; 716 717 if (mcasp->tdm_mask[stream]) 718 slots = hweight32(mcasp->tdm_mask[stream]); 719 720 for (i = 1; i <= slots; i++) 721 list[count++] = i; 722 723 for (i = 2; i <= serializers; i++) 724 list[count++] = i*slots; 725 726 cl->count = count; 727 728 return 0; 729 } 730 731 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 732 { 733 int rx_serializers = 0, tx_serializers = 0, ret, i; 734 735 for (i = 0; i < mcasp->num_serializer; i++) 736 if (mcasp->serial_dir[i] == TX_MODE) 737 tx_serializers++; 738 else if (mcasp->serial_dir[i] == RX_MODE) 739 rx_serializers++; 740 741 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 742 tx_serializers); 743 if (ret) 744 return ret; 745 746 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 747 rx_serializers); 748 749 return ret; 750 } 751 752 753 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 754 unsigned int tx_mask, 755 unsigned int rx_mask, 756 int slots, int slot_width) 757 { 758 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 759 760 dev_dbg(mcasp->dev, 761 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 762 __func__, tx_mask, rx_mask, slots, slot_width); 763 764 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 765 dev_err(mcasp->dev, 766 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 767 tx_mask, rx_mask, slots); 768 return -EINVAL; 769 } 770 771 if (slot_width && 772 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 773 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 774 __func__, slot_width); 775 return -EINVAL; 776 } 777 778 mcasp->tdm_slots = slots; 779 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 780 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 781 mcasp->slot_width = slot_width; 782 783 return davinci_mcasp_set_ch_constraints(mcasp); 784 } 785 786 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 787 int sample_width) 788 { 789 u32 fmt; 790 u32 tx_rotate, rx_rotate, slot_width; 791 u32 mask = (1ULL << sample_width) - 1; 792 793 if (mcasp->slot_width) 794 slot_width = mcasp->slot_width; 795 else if (mcasp->max_format_width) 796 slot_width = mcasp->max_format_width; 797 else 798 slot_width = sample_width; 799 /* 800 * TX rotation: 801 * right aligned formats: rotate w/ slot_width 802 * left aligned formats: rotate w/ sample_width 803 * 804 * RX rotation: 805 * right aligned formats: no rotation needed 806 * left aligned formats: rotate w/ (slot_width - sample_width) 807 */ 808 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 809 SND_SOC_DAIFMT_RIGHT_J) { 810 tx_rotate = (slot_width / 4) & 0x7; 811 rx_rotate = 0; 812 } else { 813 tx_rotate = (sample_width / 4) & 0x7; 814 rx_rotate = (slot_width - sample_width) / 4; 815 } 816 817 /* mapping of the XSSZ bit-field as described in the datasheet */ 818 fmt = (slot_width >> 1) - 1; 819 820 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 821 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 822 RXSSZ(0x0F)); 823 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 824 TXSSZ(0x0F)); 825 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 826 TXROT(7)); 827 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 828 RXROT(7)); 829 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 830 } 831 832 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 833 834 return 0; 835 } 836 837 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 838 int period_words, int channels) 839 { 840 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 841 int i; 842 u8 tx_ser = 0; 843 u8 rx_ser = 0; 844 u8 slots = mcasp->tdm_slots; 845 u8 max_active_serializers = (channels + slots - 1) / slots; 846 u8 max_rx_serializers, max_tx_serializers; 847 int active_serializers, numevt; 848 u32 reg; 849 /* Default configuration */ 850 if (mcasp->version < MCASP_VERSION_3) 851 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 852 853 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 854 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 855 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 856 max_tx_serializers = max_active_serializers; 857 max_rx_serializers = 858 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 859 } else { 860 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 861 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 862 max_tx_serializers = 863 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 864 max_rx_serializers = max_active_serializers; 865 } 866 867 for (i = 0; i < mcasp->num_serializer; i++) { 868 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 869 mcasp->serial_dir[i]); 870 if (mcasp->serial_dir[i] == TX_MODE && 871 tx_ser < max_tx_serializers) { 872 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 873 mcasp->dismod, DISMOD_MASK); 874 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 875 tx_ser++; 876 } else if (mcasp->serial_dir[i] == RX_MODE && 877 rx_ser < max_rx_serializers) { 878 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 879 rx_ser++; 880 } else { 881 /* Inactive or unused pin, set it to inactive */ 882 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 883 SRMOD_INACTIVE, SRMOD_MASK); 884 /* If unused, set DISMOD for the pin */ 885 if (mcasp->serial_dir[i] != INACTIVE_MODE) 886 mcasp_mod_bits(mcasp, 887 DAVINCI_MCASP_XRSRCTL_REG(i), 888 mcasp->dismod, DISMOD_MASK); 889 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 890 } 891 } 892 893 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 894 active_serializers = tx_ser; 895 numevt = mcasp->txnumevt; 896 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 897 } else { 898 active_serializers = rx_ser; 899 numevt = mcasp->rxnumevt; 900 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 901 } 902 903 if (active_serializers < max_active_serializers) { 904 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 905 "enabled in mcasp (%d)\n", channels, 906 active_serializers * slots); 907 return -EINVAL; 908 } 909 910 /* AFIFO is not in use */ 911 if (!numevt) { 912 /* Configure the burst size for platform drivers */ 913 if (active_serializers > 1) { 914 /* 915 * If more than one serializers are in use we have one 916 * DMA request to provide data for all serializers. 917 * For example if three serializers are enabled the DMA 918 * need to transfer three words per DMA request. 919 */ 920 dma_data->maxburst = active_serializers; 921 } else { 922 dma_data->maxburst = 0; 923 } 924 925 goto out; 926 } 927 928 if (period_words % active_serializers) { 929 dev_err(mcasp->dev, "Invalid combination of period words and " 930 "active serializers: %d, %d\n", period_words, 931 active_serializers); 932 return -EINVAL; 933 } 934 935 /* 936 * Calculate the optimal AFIFO depth for platform side: 937 * The number of words for numevt need to be in steps of active 938 * serializers. 939 */ 940 numevt = (numevt / active_serializers) * active_serializers; 941 942 while (period_words % numevt && numevt > 0) 943 numevt -= active_serializers; 944 if (numevt <= 0) 945 numevt = active_serializers; 946 947 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 948 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 949 950 /* Configure the burst size for platform drivers */ 951 if (numevt == 1) 952 numevt = 0; 953 dma_data->maxburst = numevt; 954 955 out: 956 mcasp->active_serializers[stream] = active_serializers; 957 958 return 0; 959 } 960 961 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 962 int channels) 963 { 964 int i, active_slots; 965 int total_slots; 966 int active_serializers; 967 u32 mask = 0; 968 u32 busel = 0; 969 970 total_slots = mcasp->tdm_slots; 971 972 /* 973 * If more than one serializer is needed, then use them with 974 * all the specified tdm_slots. Otherwise, one serializer can 975 * cope with the transaction using just as many slots as there 976 * are channels in the stream. 977 */ 978 if (mcasp->tdm_mask[stream]) { 979 active_slots = hweight32(mcasp->tdm_mask[stream]); 980 active_serializers = (channels + active_slots - 1) / 981 active_slots; 982 if (active_serializers == 1) 983 active_slots = channels; 984 for (i = 0; i < total_slots; i++) { 985 if ((1 << i) & mcasp->tdm_mask[stream]) { 986 mask |= (1 << i); 987 if (--active_slots <= 0) 988 break; 989 } 990 } 991 } else { 992 active_serializers = (channels + total_slots - 1) / total_slots; 993 if (active_serializers == 1) 994 active_slots = channels; 995 else 996 active_slots = total_slots; 997 998 for (i = 0; i < active_slots; i++) 999 mask |= (1 << i); 1000 } 1001 1002 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1003 1004 if (!mcasp->dat_port) 1005 busel = TXSEL; 1006 1007 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1008 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 1009 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 1010 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1011 FSXMOD(total_slots), FSXMOD(0x1FF)); 1012 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 1013 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 1014 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 1015 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 1016 FSRMOD(total_slots), FSRMOD(0x1FF)); 1017 /* 1018 * If McASP is set to be TX/RX synchronous and the playback is 1019 * not running already we need to configure the TX slots in 1020 * order to have correct FSX on the bus 1021 */ 1022 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 1023 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1024 FSXMOD(total_slots), FSXMOD(0x1FF)); 1025 } 1026 1027 return 0; 1028 } 1029 1030 /* S/PDIF */ 1031 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 1032 unsigned int rate) 1033 { 1034 u32 cs_value = 0; 1035 u8 *cs_bytes = (u8*) &cs_value; 1036 1037 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 1038 and LSB first */ 1039 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); 1040 1041 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1042 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1043 1044 /* Set the TX tdm : for all the slots */ 1045 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1046 1047 /* Set the TX clock controls : div = 1 and internal */ 1048 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1049 1050 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1051 1052 /* Only 44100 and 48000 are valid, both have the same setting */ 1053 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 1054 1055 /* Enable the DIT */ 1056 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1057 1058 /* Set S/PDIF channel status bits */ 1059 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 1060 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; 1061 1062 switch (rate) { 1063 case 22050: 1064 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1065 break; 1066 case 24000: 1067 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1068 break; 1069 case 32000: 1070 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1071 break; 1072 case 44100: 1073 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1074 break; 1075 case 48000: 1076 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1077 break; 1078 case 88200: 1079 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1080 break; 1081 case 96000: 1082 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1083 break; 1084 case 176400: 1085 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1086 break; 1087 case 192000: 1088 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1089 break; 1090 default: 1091 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); 1092 return -EINVAL; 1093 } 1094 1095 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); 1096 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); 1097 1098 return 0; 1099 } 1100 1101 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1102 unsigned int sysclk_freq, 1103 unsigned int bclk_freq, bool set) 1104 { 1105 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1106 int div = sysclk_freq / bclk_freq; 1107 int rem = sysclk_freq % bclk_freq; 1108 int error_ppm; 1109 int aux_div = 1; 1110 1111 if (div > (ACLKXDIV_MASK + 1)) { 1112 if (reg & AHCLKXE) { 1113 aux_div = div / (ACLKXDIV_MASK + 1); 1114 if (div % (ACLKXDIV_MASK + 1)) 1115 aux_div++; 1116 1117 sysclk_freq /= aux_div; 1118 div = sysclk_freq / bclk_freq; 1119 rem = sysclk_freq % bclk_freq; 1120 } else if (set) { 1121 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1122 sysclk_freq); 1123 } 1124 } 1125 1126 if (rem != 0) { 1127 if (div == 0 || 1128 ((sysclk_freq / div) - bclk_freq) > 1129 (bclk_freq - (sysclk_freq / (div+1)))) { 1130 div++; 1131 rem = rem - bclk_freq; 1132 } 1133 } 1134 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1135 (int)bclk_freq)) / div - 1000000; 1136 1137 if (set) { 1138 if (error_ppm) 1139 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1140 error_ppm); 1141 1142 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1143 if (reg & AHCLKXE) 1144 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1145 aux_div, 0); 1146 } 1147 1148 return error_ppm; 1149 } 1150 1151 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1152 { 1153 if (!mcasp->txnumevt) 1154 return 0; 1155 1156 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1157 } 1158 1159 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1160 { 1161 if (!mcasp->rxnumevt) 1162 return 0; 1163 1164 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1165 } 1166 1167 static snd_pcm_sframes_t davinci_mcasp_delay( 1168 struct snd_pcm_substream *substream, 1169 struct snd_soc_dai *cpu_dai) 1170 { 1171 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1172 u32 fifo_use; 1173 1174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1175 fifo_use = davinci_mcasp_tx_delay(mcasp); 1176 else 1177 fifo_use = davinci_mcasp_rx_delay(mcasp); 1178 1179 /* 1180 * Divide the used locations with the channel count to get the 1181 * FIFO usage in samples (don't care about partial samples in the 1182 * buffer). 1183 */ 1184 return fifo_use / substream->runtime->channels; 1185 } 1186 1187 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1188 struct snd_pcm_hw_params *params, 1189 struct snd_soc_dai *cpu_dai) 1190 { 1191 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1192 int word_length; 1193 int channels = params_channels(params); 1194 int period_size = params_period_size(params); 1195 int ret; 1196 1197 switch (params_format(params)) { 1198 case SNDRV_PCM_FORMAT_U8: 1199 case SNDRV_PCM_FORMAT_S8: 1200 word_length = 8; 1201 break; 1202 1203 case SNDRV_PCM_FORMAT_U16_LE: 1204 case SNDRV_PCM_FORMAT_S16_LE: 1205 word_length = 16; 1206 break; 1207 1208 case SNDRV_PCM_FORMAT_U24_3LE: 1209 case SNDRV_PCM_FORMAT_S24_3LE: 1210 word_length = 24; 1211 break; 1212 1213 case SNDRV_PCM_FORMAT_U24_LE: 1214 case SNDRV_PCM_FORMAT_S24_LE: 1215 word_length = 24; 1216 break; 1217 1218 case SNDRV_PCM_FORMAT_U32_LE: 1219 case SNDRV_PCM_FORMAT_S32_LE: 1220 word_length = 32; 1221 break; 1222 1223 default: 1224 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1225 return -EINVAL; 1226 } 1227 1228 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1229 if (ret) 1230 return ret; 1231 1232 /* 1233 * If mcasp is BCLK master, and a BCLK divider was not provided by 1234 * the machine driver, we need to calculate the ratio. 1235 */ 1236 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1237 int slots = mcasp->tdm_slots; 1238 int rate = params_rate(params); 1239 int sbits = params_width(params); 1240 1241 if (mcasp->slot_width) 1242 sbits = mcasp->slot_width; 1243 1244 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq, 1245 rate * sbits * slots, true); 1246 } 1247 1248 ret = mcasp_common_hw_param(mcasp, substream->stream, 1249 period_size * channels, channels); 1250 if (ret) 1251 return ret; 1252 1253 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1254 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1255 else 1256 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1257 channels); 1258 1259 if (ret) 1260 return ret; 1261 1262 davinci_config_channel_size(mcasp, word_length); 1263 1264 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 1265 mcasp->channels = channels; 1266 if (!mcasp->max_format_width) 1267 mcasp->max_format_width = word_length; 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1274 int cmd, struct snd_soc_dai *cpu_dai) 1275 { 1276 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1277 int ret = 0; 1278 1279 switch (cmd) { 1280 case SNDRV_PCM_TRIGGER_RESUME: 1281 case SNDRV_PCM_TRIGGER_START: 1282 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1283 davinci_mcasp_start(mcasp, substream->stream); 1284 break; 1285 case SNDRV_PCM_TRIGGER_SUSPEND: 1286 case SNDRV_PCM_TRIGGER_STOP: 1287 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1288 davinci_mcasp_stop(mcasp, substream->stream); 1289 break; 1290 1291 default: 1292 ret = -EINVAL; 1293 } 1294 1295 return ret; 1296 } 1297 1298 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params, 1299 struct snd_pcm_hw_rule *rule) 1300 { 1301 struct davinci_mcasp_ruledata *rd = rule->private; 1302 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1303 struct snd_mask nfmt; 1304 int i, slot_width; 1305 1306 snd_mask_none(&nfmt); 1307 slot_width = rd->mcasp->slot_width; 1308 1309 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1310 if (snd_mask_test(fmt, i)) { 1311 if (snd_pcm_format_width(i) <= slot_width) { 1312 snd_mask_set(&nfmt, i); 1313 } 1314 } 1315 } 1316 1317 return snd_mask_refine(fmt, &nfmt); 1318 } 1319 1320 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params, 1321 struct snd_pcm_hw_rule *rule) 1322 { 1323 struct davinci_mcasp_ruledata *rd = rule->private; 1324 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1325 struct snd_mask nfmt; 1326 int i, format_width; 1327 1328 snd_mask_none(&nfmt); 1329 format_width = rd->mcasp->max_format_width; 1330 1331 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1332 if (snd_mask_test(fmt, i)) { 1333 if (snd_pcm_format_width(i) == format_width) { 1334 snd_mask_set(&nfmt, i); 1335 } 1336 } 1337 } 1338 1339 return snd_mask_refine(fmt, &nfmt); 1340 } 1341 1342 static const unsigned int davinci_mcasp_dai_rates[] = { 1343 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1344 88200, 96000, 176400, 192000, 1345 }; 1346 1347 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1348 1349 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1350 struct snd_pcm_hw_rule *rule) 1351 { 1352 struct davinci_mcasp_ruledata *rd = rule->private; 1353 struct snd_interval *ri = 1354 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1355 int sbits = params_width(params); 1356 int slots = rd->mcasp->tdm_slots; 1357 struct snd_interval range; 1358 int i; 1359 1360 if (rd->mcasp->slot_width) 1361 sbits = rd->mcasp->slot_width; 1362 1363 snd_interval_any(&range); 1364 range.empty = 1; 1365 1366 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1367 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1368 uint bclk_freq = sbits * slots * 1369 davinci_mcasp_dai_rates[i]; 1370 unsigned int sysclk_freq; 1371 int ppm; 1372 1373 if (rd->mcasp->auxclk_fs_ratio) 1374 sysclk_freq = davinci_mcasp_dai_rates[i] * 1375 rd->mcasp->auxclk_fs_ratio; 1376 else 1377 sysclk_freq = rd->mcasp->sysclk_freq; 1378 1379 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1380 bclk_freq, false); 1381 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1382 if (range.empty) { 1383 range.min = davinci_mcasp_dai_rates[i]; 1384 range.empty = 0; 1385 } 1386 range.max = davinci_mcasp_dai_rates[i]; 1387 } 1388 } 1389 } 1390 1391 dev_dbg(rd->mcasp->dev, 1392 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1393 ri->min, ri->max, range.min, range.max, sbits, slots); 1394 1395 return snd_interval_refine(hw_param_interval(params, rule->var), 1396 &range); 1397 } 1398 1399 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1400 struct snd_pcm_hw_rule *rule) 1401 { 1402 struct davinci_mcasp_ruledata *rd = rule->private; 1403 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1404 struct snd_mask nfmt; 1405 int rate = params_rate(params); 1406 int slots = rd->mcasp->tdm_slots; 1407 int i, count = 0; 1408 1409 snd_mask_none(&nfmt); 1410 1411 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1412 if (snd_mask_test(fmt, i)) { 1413 uint sbits = snd_pcm_format_width(i); 1414 unsigned int sysclk_freq; 1415 int ppm; 1416 1417 if (rd->mcasp->auxclk_fs_ratio) 1418 sysclk_freq = rate * 1419 rd->mcasp->auxclk_fs_ratio; 1420 else 1421 sysclk_freq = rd->mcasp->sysclk_freq; 1422 1423 if (rd->mcasp->slot_width) 1424 sbits = rd->mcasp->slot_width; 1425 1426 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1427 sbits * slots * rate, 1428 false); 1429 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1430 snd_mask_set(&nfmt, i); 1431 count++; 1432 } 1433 } 1434 } 1435 dev_dbg(rd->mcasp->dev, 1436 "%d possible sample format for %d Hz and %d tdm slots\n", 1437 count, rate, slots); 1438 1439 return snd_mask_refine(fmt, &nfmt); 1440 } 1441 1442 static int davinci_mcasp_hw_rule_min_periodsize( 1443 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1444 { 1445 struct snd_interval *period_size = hw_param_interval(params, 1446 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1447 struct snd_interval frames; 1448 1449 snd_interval_any(&frames); 1450 frames.min = 64; 1451 frames.integer = 1; 1452 1453 return snd_interval_refine(period_size, &frames); 1454 } 1455 1456 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1457 struct snd_soc_dai *cpu_dai) 1458 { 1459 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1460 struct davinci_mcasp_ruledata *ruledata = 1461 &mcasp->ruledata[substream->stream]; 1462 u32 max_channels = 0; 1463 int i, dir, ret; 1464 int tdm_slots = mcasp->tdm_slots; 1465 1466 /* Do not allow more then one stream per direction */ 1467 if (mcasp->substreams[substream->stream]) 1468 return -EBUSY; 1469 1470 mcasp->substreams[substream->stream] = substream; 1471 1472 if (mcasp->tdm_mask[substream->stream]) 1473 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1474 1475 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1476 return 0; 1477 1478 /* 1479 * Limit the maximum allowed channels for the first stream: 1480 * number of serializers for the direction * tdm slots per serializer 1481 */ 1482 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1483 dir = TX_MODE; 1484 else 1485 dir = RX_MODE; 1486 1487 for (i = 0; i < mcasp->num_serializer; i++) { 1488 if (mcasp->serial_dir[i] == dir) 1489 max_channels++; 1490 } 1491 ruledata->serializers = max_channels; 1492 ruledata->mcasp = mcasp; 1493 max_channels *= tdm_slots; 1494 /* 1495 * If the already active stream has less channels than the calculated 1496 * limit based on the seirializers * tdm_slots, and only one serializer 1497 * is in use we need to use that as a constraint for the second stream. 1498 * Otherwise (first stream or less allowed channels or more than one 1499 * serializer in use) we use the calculated constraint. 1500 */ 1501 if (mcasp->channels && mcasp->channels < max_channels && 1502 ruledata->serializers == 1) 1503 max_channels = mcasp->channels; 1504 /* 1505 * But we can always allow channels upto the amount of 1506 * the available tdm_slots. 1507 */ 1508 if (max_channels < tdm_slots) 1509 max_channels = tdm_slots; 1510 1511 snd_pcm_hw_constraint_minmax(substream->runtime, 1512 SNDRV_PCM_HW_PARAM_CHANNELS, 1513 0, max_channels); 1514 1515 snd_pcm_hw_constraint_list(substream->runtime, 1516 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1517 &mcasp->chconstr[substream->stream]); 1518 1519 if (mcasp->max_format_width) { 1520 /* 1521 * Only allow formats which require same amount of bits on the 1522 * bus as the currently running stream 1523 */ 1524 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1525 SNDRV_PCM_HW_PARAM_FORMAT, 1526 davinci_mcasp_hw_rule_format_width, 1527 ruledata, 1528 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1529 if (ret) 1530 return ret; 1531 } 1532 else if (mcasp->slot_width) { 1533 /* Only allow formats require <= slot_width bits on the bus */ 1534 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1535 SNDRV_PCM_HW_PARAM_FORMAT, 1536 davinci_mcasp_hw_rule_slot_width, 1537 ruledata, 1538 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1539 if (ret) 1540 return ret; 1541 } 1542 1543 /* 1544 * If we rely on implicit BCLK divider setting we should 1545 * set constraints based on what we can provide. 1546 */ 1547 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1548 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1549 SNDRV_PCM_HW_PARAM_RATE, 1550 davinci_mcasp_hw_rule_rate, 1551 ruledata, 1552 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1553 if (ret) 1554 return ret; 1555 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1556 SNDRV_PCM_HW_PARAM_FORMAT, 1557 davinci_mcasp_hw_rule_format, 1558 ruledata, 1559 SNDRV_PCM_HW_PARAM_RATE, -1); 1560 if (ret) 1561 return ret; 1562 } 1563 1564 snd_pcm_hw_rule_add(substream->runtime, 0, 1565 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1566 davinci_mcasp_hw_rule_min_periodsize, NULL, 1567 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1568 1569 return 0; 1570 } 1571 1572 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1573 struct snd_soc_dai *cpu_dai) 1574 { 1575 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1576 1577 mcasp->substreams[substream->stream] = NULL; 1578 mcasp->active_serializers[substream->stream] = 0; 1579 1580 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1581 return; 1582 1583 if (!snd_soc_dai_active(cpu_dai)) { 1584 mcasp->channels = 0; 1585 mcasp->max_format_width = 0; 1586 } 1587 } 1588 1589 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1590 .startup = davinci_mcasp_startup, 1591 .shutdown = davinci_mcasp_shutdown, 1592 .trigger = davinci_mcasp_trigger, 1593 .delay = davinci_mcasp_delay, 1594 .hw_params = davinci_mcasp_hw_params, 1595 .set_fmt = davinci_mcasp_set_dai_fmt, 1596 .set_clkdiv = davinci_mcasp_set_clkdiv, 1597 .set_sysclk = davinci_mcasp_set_sysclk, 1598 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1599 }; 1600 1601 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1602 { 1603 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1604 1605 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1606 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 1607 1608 return 0; 1609 } 1610 1611 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1612 1613 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1614 SNDRV_PCM_FMTBIT_U8 | \ 1615 SNDRV_PCM_FMTBIT_S16_LE | \ 1616 SNDRV_PCM_FMTBIT_U16_LE | \ 1617 SNDRV_PCM_FMTBIT_S24_LE | \ 1618 SNDRV_PCM_FMTBIT_U24_LE | \ 1619 SNDRV_PCM_FMTBIT_S24_3LE | \ 1620 SNDRV_PCM_FMTBIT_U24_3LE | \ 1621 SNDRV_PCM_FMTBIT_S32_LE | \ 1622 SNDRV_PCM_FMTBIT_U32_LE) 1623 1624 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1625 { 1626 .name = "davinci-mcasp.0", 1627 .probe = davinci_mcasp_dai_probe, 1628 .playback = { 1629 .stream_name = "IIS Playback", 1630 .channels_min = 1, 1631 .channels_max = 32 * 16, 1632 .rates = DAVINCI_MCASP_RATES, 1633 .formats = DAVINCI_MCASP_PCM_FMTS, 1634 }, 1635 .capture = { 1636 .stream_name = "IIS Capture", 1637 .channels_min = 1, 1638 .channels_max = 32 * 16, 1639 .rates = DAVINCI_MCASP_RATES, 1640 .formats = DAVINCI_MCASP_PCM_FMTS, 1641 }, 1642 .ops = &davinci_mcasp_dai_ops, 1643 1644 .symmetric_rates = 1, 1645 }, 1646 { 1647 .name = "davinci-mcasp.1", 1648 .probe = davinci_mcasp_dai_probe, 1649 .playback = { 1650 .stream_name = "DIT Playback", 1651 .channels_min = 1, 1652 .channels_max = 384, 1653 .rates = DAVINCI_MCASP_RATES, 1654 .formats = DAVINCI_MCASP_PCM_FMTS, 1655 }, 1656 .ops = &davinci_mcasp_dai_ops, 1657 }, 1658 1659 }; 1660 1661 static const struct snd_soc_component_driver davinci_mcasp_component = { 1662 .name = "davinci-mcasp", 1663 }; 1664 1665 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1666 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1667 .tx_dma_offset = 0x400, 1668 .rx_dma_offset = 0x400, 1669 .version = MCASP_VERSION_1, 1670 }; 1671 1672 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1673 .tx_dma_offset = 0x2000, 1674 .rx_dma_offset = 0x2000, 1675 .version = MCASP_VERSION_2, 1676 }; 1677 1678 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1679 .tx_dma_offset = 0, 1680 .rx_dma_offset = 0, 1681 .version = MCASP_VERSION_3, 1682 }; 1683 1684 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1685 /* The CFG port offset will be calculated if it is needed */ 1686 .tx_dma_offset = 0, 1687 .rx_dma_offset = 0, 1688 .version = MCASP_VERSION_4, 1689 }; 1690 1691 static const struct of_device_id mcasp_dt_ids[] = { 1692 { 1693 .compatible = "ti,dm646x-mcasp-audio", 1694 .data = &dm646x_mcasp_pdata, 1695 }, 1696 { 1697 .compatible = "ti,da830-mcasp-audio", 1698 .data = &da830_mcasp_pdata, 1699 }, 1700 { 1701 .compatible = "ti,am33xx-mcasp-audio", 1702 .data = &am33xx_mcasp_pdata, 1703 }, 1704 { 1705 .compatible = "ti,dra7-mcasp-audio", 1706 .data = &dra7_mcasp_pdata, 1707 }, 1708 { /* sentinel */ } 1709 }; 1710 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1711 1712 static int mcasp_reparent_fck(struct platform_device *pdev) 1713 { 1714 struct device_node *node = pdev->dev.of_node; 1715 struct clk *gfclk, *parent_clk; 1716 const char *parent_name; 1717 int ret; 1718 1719 if (!node) 1720 return 0; 1721 1722 parent_name = of_get_property(node, "fck_parent", NULL); 1723 if (!parent_name) 1724 return 0; 1725 1726 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1727 1728 gfclk = clk_get(&pdev->dev, "fck"); 1729 if (IS_ERR(gfclk)) { 1730 dev_err(&pdev->dev, "failed to get fck\n"); 1731 return PTR_ERR(gfclk); 1732 } 1733 1734 parent_clk = clk_get(NULL, parent_name); 1735 if (IS_ERR(parent_clk)) { 1736 dev_err(&pdev->dev, "failed to get parent clock\n"); 1737 ret = PTR_ERR(parent_clk); 1738 goto err1; 1739 } 1740 1741 ret = clk_set_parent(gfclk, parent_clk); 1742 if (ret) { 1743 dev_err(&pdev->dev, "failed to reparent fck\n"); 1744 goto err2; 1745 } 1746 1747 err2: 1748 clk_put(parent_clk); 1749 err1: 1750 clk_put(gfclk); 1751 return ret; 1752 } 1753 1754 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp) 1755 { 1756 #ifdef CONFIG_OF_GPIO 1757 if (mcasp->dev->of_node && 1758 of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) 1759 return true; 1760 #endif 1761 1762 return false; 1763 } 1764 1765 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp, 1766 struct platform_device *pdev) 1767 { 1768 const struct of_device_id *match = of_match_device(mcasp_dt_ids, &pdev->dev); 1769 struct device_node *np = pdev->dev.of_node; 1770 struct davinci_mcasp_pdata *pdata = NULL; 1771 const u32 *of_serial_dir32; 1772 u32 val; 1773 int i; 1774 1775 if (pdev->dev.platform_data) { 1776 pdata = pdev->dev.platform_data; 1777 pdata->dismod = DISMOD_LOW; 1778 goto out; 1779 } else if (match) { 1780 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), 1781 GFP_KERNEL); 1782 if (!pdata) 1783 return -ENOMEM; 1784 } else { 1785 dev_err(&pdev->dev, "No compatible match found\n"); 1786 return -EINVAL; 1787 } 1788 1789 if (of_property_read_u32(np, "op-mode", &val) == 0) { 1790 pdata->op_mode = val; 1791 } else { 1792 mcasp->missing_audio_param = true; 1793 goto out; 1794 } 1795 1796 if (of_property_read_u32(np, "tdm-slots", &val) == 0) { 1797 if (val < 2 || val > 32) { 1798 dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n"); 1799 return -EINVAL; 1800 } 1801 1802 pdata->tdm_slots = val; 1803 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) { 1804 mcasp->missing_audio_param = true; 1805 goto out; 1806 } 1807 1808 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1809 val /= sizeof(u32); 1810 if (of_serial_dir32) { 1811 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1812 (sizeof(*of_serial_dir) * val), 1813 GFP_KERNEL); 1814 if (!of_serial_dir) 1815 return -ENOMEM; 1816 1817 for (i = 0; i < val; i++) 1818 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1819 1820 pdata->num_serializer = val; 1821 pdata->serial_dir = of_serial_dir; 1822 } else { 1823 mcasp->missing_audio_param = true; 1824 goto out; 1825 } 1826 1827 if (of_property_read_u32(np, "tx-num-evt", &val) == 0) 1828 pdata->txnumevt = val; 1829 1830 if (of_property_read_u32(np, "rx-num-evt", &val) == 0) 1831 pdata->rxnumevt = val; 1832 1833 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) 1834 mcasp->auxclk_fs_ratio = val; 1835 1836 if (of_property_read_u32(np, "dismod", &val) == 0) { 1837 if (val == 0 || val == 2 || val == 3) { 1838 pdata->dismod = DISMOD_VAL(val); 1839 } else { 1840 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1841 pdata->dismod = DISMOD_LOW; 1842 } 1843 } else { 1844 pdata->dismod = DISMOD_LOW; 1845 } 1846 1847 out: 1848 mcasp->pdata = pdata; 1849 1850 if (mcasp->missing_audio_param) { 1851 if (davinci_mcasp_have_gpiochip(mcasp)) { 1852 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n"); 1853 return 0; 1854 } 1855 1856 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n"); 1857 return -ENODEV; 1858 } 1859 1860 mcasp->op_mode = pdata->op_mode; 1861 /* sanity check for tdm slots parameter */ 1862 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 1863 if (pdata->tdm_slots < 2) { 1864 dev_warn(&pdev->dev, "invalid tdm slots: %d\n", 1865 pdata->tdm_slots); 1866 mcasp->tdm_slots = 2; 1867 } else if (pdata->tdm_slots > 32) { 1868 dev_warn(&pdev->dev, "invalid tdm slots: %d\n", 1869 pdata->tdm_slots); 1870 mcasp->tdm_slots = 32; 1871 } else { 1872 mcasp->tdm_slots = pdata->tdm_slots; 1873 } 1874 } 1875 1876 mcasp->num_serializer = pdata->num_serializer; 1877 #ifdef CONFIG_PM 1878 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 1879 mcasp->num_serializer, sizeof(u32), 1880 GFP_KERNEL); 1881 if (!mcasp->context.xrsr_regs) 1882 return -ENOMEM; 1883 #endif 1884 mcasp->serial_dir = pdata->serial_dir; 1885 mcasp->version = pdata->version; 1886 mcasp->txnumevt = pdata->txnumevt; 1887 mcasp->rxnumevt = pdata->rxnumevt; 1888 mcasp->dismod = pdata->dismod; 1889 1890 return 0; 1891 } 1892 1893 enum { 1894 PCM_EDMA, 1895 PCM_SDMA, 1896 PCM_UDMA, 1897 }; 1898 static const char *sdma_prefix = "ti,omap"; 1899 1900 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 1901 { 1902 struct dma_chan *chan; 1903 const char *tmp; 1904 int ret = PCM_EDMA; 1905 1906 if (!mcasp->dev->of_node) 1907 return PCM_EDMA; 1908 1909 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 1910 chan = dma_request_chan(mcasp->dev, tmp); 1911 if (IS_ERR(chan)) { 1912 if (PTR_ERR(chan) != -EPROBE_DEFER) 1913 dev_err(mcasp->dev, 1914 "Can't verify DMA configuration (%ld)\n", 1915 PTR_ERR(chan)); 1916 return PTR_ERR(chan); 1917 } 1918 if (WARN_ON(!chan->device || !chan->device->dev)) { 1919 dma_release_channel(chan); 1920 return -EINVAL; 1921 } 1922 1923 if (chan->device->dev->of_node) 1924 ret = of_property_read_string(chan->device->dev->of_node, 1925 "compatible", &tmp); 1926 else 1927 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 1928 1929 dma_release_channel(chan); 1930 if (ret) 1931 return ret; 1932 1933 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 1934 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 1935 return PCM_SDMA; 1936 else if (strstr(tmp, "udmap")) 1937 return PCM_UDMA; 1938 1939 return PCM_EDMA; 1940 } 1941 1942 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 1943 { 1944 int i; 1945 u32 offset = 0; 1946 1947 if (pdata->version != MCASP_VERSION_4) 1948 return pdata->tx_dma_offset; 1949 1950 for (i = 0; i < pdata->num_serializer; i++) { 1951 if (pdata->serial_dir[i] == TX_MODE) { 1952 if (!offset) { 1953 offset = DAVINCI_MCASP_TXBUF_REG(i); 1954 } else { 1955 pr_err("%s: Only one serializer allowed!\n", 1956 __func__); 1957 break; 1958 } 1959 } 1960 } 1961 1962 return offset; 1963 } 1964 1965 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 1966 { 1967 int i; 1968 u32 offset = 0; 1969 1970 if (pdata->version != MCASP_VERSION_4) 1971 return pdata->rx_dma_offset; 1972 1973 for (i = 0; i < pdata->num_serializer; i++) { 1974 if (pdata->serial_dir[i] == RX_MODE) { 1975 if (!offset) { 1976 offset = DAVINCI_MCASP_RXBUF_REG(i); 1977 } else { 1978 pr_err("%s: Only one serializer allowed!\n", 1979 __func__); 1980 break; 1981 } 1982 } 1983 } 1984 1985 return offset; 1986 } 1987 1988 #ifdef CONFIG_GPIOLIB 1989 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 1990 { 1991 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1992 1993 if (mcasp->num_serializer && offset < mcasp->num_serializer && 1994 mcasp->serial_dir[offset] != INACTIVE_MODE) { 1995 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 1996 return -EBUSY; 1997 } 1998 1999 /* Do not change the PIN yet */ 2000 2001 return pm_runtime_get_sync(mcasp->dev); 2002 } 2003 2004 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 2005 { 2006 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2007 2008 /* Set the direction to input */ 2009 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2010 2011 /* Set the pin as McASP pin */ 2012 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2013 2014 pm_runtime_put_sync(mcasp->dev); 2015 } 2016 2017 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 2018 unsigned offset, int value) 2019 { 2020 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2021 u32 val; 2022 2023 if (value) 2024 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2025 else 2026 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2027 2028 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2029 if (!(val & BIT(offset))) { 2030 /* Set the pin as GPIO pin */ 2031 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2032 2033 /* Set the direction to output */ 2034 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2035 } 2036 2037 return 0; 2038 } 2039 2040 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, 2041 int value) 2042 { 2043 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2044 2045 if (value) 2046 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2047 else 2048 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2049 } 2050 2051 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 2052 unsigned offset) 2053 { 2054 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2055 u32 val; 2056 2057 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2058 if (!(val & BIT(offset))) { 2059 /* Set the direction to input */ 2060 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2061 2062 /* Set the pin as GPIO pin */ 2063 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2064 } 2065 2066 return 0; 2067 } 2068 2069 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 2070 { 2071 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2072 u32 val; 2073 2074 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 2075 if (val & BIT(offset)) 2076 return 1; 2077 2078 return 0; 2079 } 2080 2081 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 2082 unsigned offset) 2083 { 2084 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2085 u32 val; 2086 2087 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 2088 if (val & BIT(offset)) 2089 return 0; 2090 2091 return 1; 2092 } 2093 2094 static const struct gpio_chip davinci_mcasp_template_chip = { 2095 .owner = THIS_MODULE, 2096 .request = davinci_mcasp_gpio_request, 2097 .free = davinci_mcasp_gpio_free, 2098 .direction_output = davinci_mcasp_gpio_direction_out, 2099 .set = davinci_mcasp_gpio_set, 2100 .direction_input = davinci_mcasp_gpio_direction_in, 2101 .get = davinci_mcasp_gpio_get, 2102 .get_direction = davinci_mcasp_gpio_get_direction, 2103 .base = -1, 2104 .ngpio = 32, 2105 }; 2106 2107 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2108 { 2109 if (!davinci_mcasp_have_gpiochip(mcasp)) 2110 return 0; 2111 2112 mcasp->gpio_chip = davinci_mcasp_template_chip; 2113 mcasp->gpio_chip.label = dev_name(mcasp->dev); 2114 mcasp->gpio_chip.parent = mcasp->dev; 2115 #ifdef CONFIG_OF_GPIO 2116 mcasp->gpio_chip.of_node = mcasp->dev->of_node; 2117 #endif 2118 2119 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 2120 } 2121 2122 #else /* CONFIG_GPIOLIB */ 2123 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2124 { 2125 return 0; 2126 } 2127 #endif /* CONFIG_GPIOLIB */ 2128 2129 static int davinci_mcasp_probe(struct platform_device *pdev) 2130 { 2131 struct snd_dmaengine_dai_dma_data *dma_data; 2132 struct resource *mem, *dat; 2133 struct davinci_mcasp *mcasp; 2134 char *irq_name; 2135 int irq; 2136 int ret; 2137 2138 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2139 dev_err(&pdev->dev, "No platform data supplied\n"); 2140 return -EINVAL; 2141 } 2142 2143 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2144 GFP_KERNEL); 2145 if (!mcasp) 2146 return -ENOMEM; 2147 2148 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2149 if (!mem) { 2150 dev_warn(&pdev->dev, 2151 "\"mpu\" mem resource not found, using index 0\n"); 2152 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2153 if (!mem) { 2154 dev_err(&pdev->dev, "no mem resource?\n"); 2155 return -ENODEV; 2156 } 2157 } 2158 2159 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2160 if (IS_ERR(mcasp->base)) 2161 return PTR_ERR(mcasp->base); 2162 2163 dev_set_drvdata(&pdev->dev, mcasp); 2164 pm_runtime_enable(&pdev->dev); 2165 2166 mcasp->dev = &pdev->dev; 2167 ret = davinci_mcasp_get_config(mcasp, pdev); 2168 if (ret) 2169 goto err; 2170 2171 /* All PINS as McASP */ 2172 pm_runtime_get_sync(mcasp->dev); 2173 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2174 pm_runtime_put(mcasp->dev); 2175 2176 /* Skip audio related setup code if the configuration is not adequat */ 2177 if (mcasp->missing_audio_param) 2178 goto no_audio; 2179 2180 irq = platform_get_irq_byname_optional(pdev, "common"); 2181 if (irq > 0) { 2182 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2183 dev_name(&pdev->dev)); 2184 if (!irq_name) { 2185 ret = -ENOMEM; 2186 goto err; 2187 } 2188 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2189 davinci_mcasp_common_irq_handler, 2190 IRQF_ONESHOT | IRQF_SHARED, 2191 irq_name, mcasp); 2192 if (ret) { 2193 dev_err(&pdev->dev, "common IRQ request failed\n"); 2194 goto err; 2195 } 2196 2197 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2198 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2199 } 2200 2201 irq = platform_get_irq_byname_optional(pdev, "rx"); 2202 if (irq > 0) { 2203 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2204 dev_name(&pdev->dev)); 2205 if (!irq_name) { 2206 ret = -ENOMEM; 2207 goto err; 2208 } 2209 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2210 davinci_mcasp_rx_irq_handler, 2211 IRQF_ONESHOT, irq_name, mcasp); 2212 if (ret) { 2213 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2214 goto err; 2215 } 2216 2217 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2218 } 2219 2220 irq = platform_get_irq_byname_optional(pdev, "tx"); 2221 if (irq > 0) { 2222 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2223 dev_name(&pdev->dev)); 2224 if (!irq_name) { 2225 ret = -ENOMEM; 2226 goto err; 2227 } 2228 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2229 davinci_mcasp_tx_irq_handler, 2230 IRQF_ONESHOT, irq_name, mcasp); 2231 if (ret) { 2232 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2233 goto err; 2234 } 2235 2236 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2237 } 2238 2239 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2240 if (dat) 2241 mcasp->dat_port = true; 2242 2243 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2244 dma_data->filter_data = "tx"; 2245 if (dat) 2246 dma_data->addr = dat->start; 2247 else 2248 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata); 2249 2250 2251 /* RX is not valid in DIT mode */ 2252 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2253 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2254 dma_data->filter_data = "rx"; 2255 if (dat) 2256 dma_data->addr = dat->start; 2257 else 2258 dma_data->addr = 2259 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata); 2260 } 2261 2262 if (mcasp->version < MCASP_VERSION_3) { 2263 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2264 /* dma_params->dma_addr is pointing to the data port address */ 2265 mcasp->dat_port = true; 2266 } else { 2267 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2268 } 2269 2270 /* Allocate memory for long enough list for all possible 2271 * scenarios. Maximum number tdm slots is 32 and there cannot 2272 * be more serializers than given in the configuration. The 2273 * serializer directions could be taken into account, but it 2274 * would make code much more complex and save only couple of 2275 * bytes. 2276 */ 2277 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2278 devm_kcalloc(mcasp->dev, 2279 32 + mcasp->num_serializer - 1, 2280 sizeof(unsigned int), 2281 GFP_KERNEL); 2282 2283 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2284 devm_kcalloc(mcasp->dev, 2285 32 + mcasp->num_serializer - 1, 2286 sizeof(unsigned int), 2287 GFP_KERNEL); 2288 2289 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2290 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2291 ret = -ENOMEM; 2292 goto err; 2293 } 2294 2295 ret = davinci_mcasp_set_ch_constraints(mcasp); 2296 if (ret) 2297 goto err; 2298 2299 mcasp_reparent_fck(pdev); 2300 2301 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, 2302 &davinci_mcasp_dai[mcasp->op_mode], 1); 2303 2304 if (ret != 0) 2305 goto err; 2306 2307 ret = davinci_mcasp_get_dma_type(mcasp); 2308 switch (ret) { 2309 case PCM_EDMA: 2310 ret = edma_pcm_platform_register(&pdev->dev); 2311 break; 2312 case PCM_SDMA: 2313 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2314 break; 2315 case PCM_UDMA: 2316 ret = udma_pcm_platform_register(&pdev->dev); 2317 break; 2318 default: 2319 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2320 case -EPROBE_DEFER: 2321 goto err; 2322 } 2323 2324 if (ret) { 2325 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2326 goto err; 2327 } 2328 2329 no_audio: 2330 ret = davinci_mcasp_init_gpiochip(mcasp); 2331 if (ret) { 2332 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret); 2333 goto err; 2334 } 2335 2336 return 0; 2337 err: 2338 pm_runtime_disable(&pdev->dev); 2339 return ret; 2340 } 2341 2342 static int davinci_mcasp_remove(struct platform_device *pdev) 2343 { 2344 pm_runtime_disable(&pdev->dev); 2345 2346 return 0; 2347 } 2348 2349 #ifdef CONFIG_PM 2350 static int davinci_mcasp_runtime_suspend(struct device *dev) 2351 { 2352 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2353 struct davinci_mcasp_context *context = &mcasp->context; 2354 u32 reg; 2355 int i; 2356 2357 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2358 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2359 2360 if (mcasp->txnumevt) { 2361 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2362 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2363 } 2364 if (mcasp->rxnumevt) { 2365 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2366 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2367 } 2368 2369 for (i = 0; i < mcasp->num_serializer; i++) 2370 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2371 DAVINCI_MCASP_XRSRCTL_REG(i)); 2372 2373 return 0; 2374 } 2375 2376 static int davinci_mcasp_runtime_resume(struct device *dev) 2377 { 2378 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2379 struct davinci_mcasp_context *context = &mcasp->context; 2380 u32 reg; 2381 int i; 2382 2383 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2384 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2385 2386 if (mcasp->txnumevt) { 2387 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2388 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2389 } 2390 if (mcasp->rxnumevt) { 2391 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2392 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2393 } 2394 2395 for (i = 0; i < mcasp->num_serializer; i++) 2396 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2397 context->xrsr_regs[i]); 2398 2399 return 0; 2400 } 2401 2402 #endif 2403 2404 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2405 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2406 davinci_mcasp_runtime_resume, 2407 NULL) 2408 }; 2409 2410 static struct platform_driver davinci_mcasp_driver = { 2411 .probe = davinci_mcasp_probe, 2412 .remove = davinci_mcasp_remove, 2413 .driver = { 2414 .name = "davinci-mcasp", 2415 .pm = &davinci_mcasp_pm_ops, 2416 .of_match_table = mcasp_dt_ids, 2417 }, 2418 }; 2419 2420 module_platform_driver(davinci_mcasp_driver); 2421 2422 MODULE_AUTHOR("Steve Chen"); 2423 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2424 MODULE_LICENSE("GPL"); 2425