1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_data/davinci_asp.h> 27 #include <linux/math64.h> 28 #include <linux/bitmap.h> 29 #include <linux/gpio/driver.h> 30 31 #include <sound/asoundef.h> 32 #include <sound/core.h> 33 #include <sound/pcm.h> 34 #include <sound/pcm_params.h> 35 #include <sound/initval.h> 36 #include <sound/soc.h> 37 #include <sound/dmaengine_pcm.h> 38 39 #include "edma-pcm.h" 40 #include "sdma-pcm.h" 41 #include "udma-pcm.h" 42 #include "davinci-mcasp.h" 43 44 #define MCASP_MAX_AFIFO_DEPTH 64 45 46 #ifdef CONFIG_PM 47 static u32 context_regs[] = { 48 DAVINCI_MCASP_TXFMCTL_REG, 49 DAVINCI_MCASP_RXFMCTL_REG, 50 DAVINCI_MCASP_TXFMT_REG, 51 DAVINCI_MCASP_RXFMT_REG, 52 DAVINCI_MCASP_ACLKXCTL_REG, 53 DAVINCI_MCASP_ACLKRCTL_REG, 54 DAVINCI_MCASP_AHCLKXCTL_REG, 55 DAVINCI_MCASP_AHCLKRCTL_REG, 56 DAVINCI_MCASP_PDIR_REG, 57 DAVINCI_MCASP_PFUNC_REG, 58 DAVINCI_MCASP_RXMASK_REG, 59 DAVINCI_MCASP_TXMASK_REG, 60 DAVINCI_MCASP_RXTDM_REG, 61 DAVINCI_MCASP_TXTDM_REG, 62 }; 63 64 struct davinci_mcasp_context { 65 u32 config_regs[ARRAY_SIZE(context_regs)]; 66 u32 afifo_regs[2]; /* for read/write fifo control registers */ 67 u32 *xrsr_regs; /* for serializer configuration */ 68 bool pm_state; 69 }; 70 #endif 71 72 struct davinci_mcasp_ruledata { 73 struct davinci_mcasp *mcasp; 74 int serializers; 75 }; 76 77 struct davinci_mcasp { 78 struct snd_dmaengine_dai_dma_data dma_data[2]; 79 void __iomem *base; 80 u32 fifo_base; 81 struct device *dev; 82 struct snd_pcm_substream *substreams[2]; 83 unsigned int dai_fmt; 84 85 /* McASP specific data */ 86 int tdm_slots; 87 u32 tdm_mask[2]; 88 int slot_width; 89 u8 op_mode; 90 u8 dismod; 91 u8 num_serializer; 92 u8 *serial_dir; 93 u8 version; 94 u8 bclk_div; 95 int streams; 96 u32 irq_request[2]; 97 int dma_request[2]; 98 99 int sysclk_freq; 100 bool bclk_master; 101 u32 auxclk_fs_ratio; 102 103 unsigned long pdir; /* Pin direction bitfield */ 104 105 /* McASP FIFO related */ 106 u8 txnumevt; 107 u8 rxnumevt; 108 109 bool dat_port; 110 111 /* Used for comstraint setting on the second stream */ 112 u32 channels; 113 int max_format_width; 114 u8 active_serializers[2]; 115 116 #ifdef CONFIG_GPIOLIB 117 struct gpio_chip gpio_chip; 118 #endif 119 120 #ifdef CONFIG_PM 121 struct davinci_mcasp_context context; 122 #endif 123 124 struct davinci_mcasp_ruledata ruledata[2]; 125 struct snd_pcm_hw_constraint_list chconstr[2]; 126 }; 127 128 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 129 u32 val) 130 { 131 void __iomem *reg = mcasp->base + offset; 132 __raw_writel(__raw_readl(reg) | val, reg); 133 } 134 135 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 136 u32 val) 137 { 138 void __iomem *reg = mcasp->base + offset; 139 __raw_writel((__raw_readl(reg) & ~(val)), reg); 140 } 141 142 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 143 u32 val, u32 mask) 144 { 145 void __iomem *reg = mcasp->base + offset; 146 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 147 } 148 149 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 150 u32 val) 151 { 152 __raw_writel(val, mcasp->base + offset); 153 } 154 155 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 156 { 157 return (u32)__raw_readl(mcasp->base + offset); 158 } 159 160 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 161 { 162 int i = 0; 163 164 mcasp_set_bits(mcasp, ctl_reg, val); 165 166 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 167 /* loop count is to avoid the lock-up */ 168 for (i = 0; i < 1000; i++) { 169 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 170 break; 171 } 172 173 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 174 printk(KERN_ERR "GBLCTL write error\n"); 175 } 176 177 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 178 { 179 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 180 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 181 182 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 183 } 184 185 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 186 { 187 u32 bit = PIN_BIT_AMUTE; 188 189 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 190 if (enable) 191 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 192 else 193 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 194 } 195 } 196 197 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 198 { 199 u32 bit; 200 201 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { 202 if (enable) 203 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 204 else 205 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 206 } 207 } 208 209 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 210 { 211 if (mcasp->rxnumevt) { /* enable FIFO */ 212 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 213 214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 216 } 217 218 /* Start clocks */ 219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 221 /* 222 * When ASYNC == 0 the transmit and receive sections operate 223 * synchronously from the transmit clock and frame sync. We need to make 224 * sure that the TX signlas are enabled when starting reception. 225 */ 226 if (mcasp_is_synchronous(mcasp)) { 227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 229 mcasp_set_clk_pdir(mcasp, true); 230 } 231 232 /* Activate serializer(s) */ 233 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 235 /* Release RX state machine */ 236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 237 /* Release Frame Sync generator */ 238 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 239 if (mcasp_is_synchronous(mcasp)) 240 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 241 242 /* enable receive IRQs */ 243 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 245 } 246 247 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 248 { 249 u32 cnt; 250 251 if (mcasp->txnumevt) { /* enable FIFO */ 252 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 253 254 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 255 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 256 } 257 258 /* Start clocks */ 259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 260 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 261 mcasp_set_clk_pdir(mcasp, true); 262 263 /* Activate serializer(s) */ 264 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 266 267 /* wait for XDATA to be cleared */ 268 cnt = 0; 269 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 270 (cnt < 100000)) 271 cnt++; 272 273 mcasp_set_axr_pdir(mcasp, true); 274 275 /* Release TX state machine */ 276 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 277 /* Release Frame Sync generator */ 278 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 279 280 /* enable transmit IRQs */ 281 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 283 } 284 285 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 286 { 287 mcasp->streams++; 288 289 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 290 mcasp_start_tx(mcasp); 291 else 292 mcasp_start_rx(mcasp); 293 } 294 295 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 296 { 297 /* disable IRQ sources */ 298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 299 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 300 301 /* 302 * In synchronous mode stop the TX clocks if no other stream is 303 * running 304 */ 305 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 306 mcasp_set_clk_pdir(mcasp, false); 307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 308 } 309 310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 311 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 312 313 if (mcasp->rxnumevt) { /* disable FIFO */ 314 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 315 316 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 317 } 318 } 319 320 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 321 { 322 u32 val = 0; 323 324 /* disable IRQ sources */ 325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 326 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 327 328 /* 329 * In synchronous mode keep TX clocks running if the capture stream is 330 * still running. 331 */ 332 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 333 val = TXHCLKRST | TXCLKRST | TXFSRST; 334 else 335 mcasp_set_clk_pdir(mcasp, false); 336 337 338 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 340 341 if (mcasp->txnumevt) { /* disable FIFO */ 342 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 343 344 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 345 } 346 347 mcasp_set_axr_pdir(mcasp, false); 348 } 349 350 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 351 { 352 mcasp->streams--; 353 354 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 355 mcasp_stop_tx(mcasp); 356 else 357 mcasp_stop_rx(mcasp); 358 } 359 360 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 361 { 362 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 363 struct snd_pcm_substream *substream; 364 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 365 u32 handled_mask = 0; 366 u32 stat; 367 368 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 369 if (stat & XUNDRN & irq_mask) { 370 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 371 handled_mask |= XUNDRN; 372 373 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 374 if (substream) 375 snd_pcm_stop_xrun(substream); 376 } 377 378 if (!handled_mask) 379 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 380 stat); 381 382 if (stat & XRERR) 383 handled_mask |= XRERR; 384 385 /* Ack the handled event only */ 386 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 387 388 return IRQ_RETVAL(handled_mask); 389 } 390 391 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 392 { 393 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 394 struct snd_pcm_substream *substream; 395 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 396 u32 handled_mask = 0; 397 u32 stat; 398 399 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 400 if (stat & ROVRN & irq_mask) { 401 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 402 handled_mask |= ROVRN; 403 404 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 405 if (substream) 406 snd_pcm_stop_xrun(substream); 407 } 408 409 if (!handled_mask) 410 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 411 stat); 412 413 if (stat & XRERR) 414 handled_mask |= XRERR; 415 416 /* Ack the handled event only */ 417 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 418 419 return IRQ_RETVAL(handled_mask); 420 } 421 422 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 423 { 424 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 425 irqreturn_t ret = IRQ_NONE; 426 427 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 428 ret = davinci_mcasp_tx_irq_handler(irq, data); 429 430 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 431 ret |= davinci_mcasp_rx_irq_handler(irq, data); 432 433 return ret; 434 } 435 436 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 437 unsigned int fmt) 438 { 439 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 440 int ret = 0; 441 u32 data_delay; 442 bool fs_pol_rising; 443 bool inv_fs = false; 444 445 if (!fmt) 446 return 0; 447 448 pm_runtime_get_sync(mcasp->dev); 449 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 450 case SND_SOC_DAIFMT_DSP_A: 451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 452 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 453 /* 1st data bit occur one ACLK cycle after the frame sync */ 454 data_delay = 1; 455 break; 456 case SND_SOC_DAIFMT_DSP_B: 457 case SND_SOC_DAIFMT_AC97: 458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 460 /* No delay after FS */ 461 data_delay = 0; 462 break; 463 case SND_SOC_DAIFMT_I2S: 464 /* configure a full-word SYNC pulse (LRCLK) */ 465 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 466 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 467 /* 1st data bit occur one ACLK cycle after the frame sync */ 468 data_delay = 1; 469 /* FS need to be inverted */ 470 inv_fs = true; 471 break; 472 case SND_SOC_DAIFMT_RIGHT_J: 473 case SND_SOC_DAIFMT_LEFT_J: 474 /* configure a full-word SYNC pulse (LRCLK) */ 475 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 476 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 477 /* No delay after FS */ 478 data_delay = 0; 479 break; 480 default: 481 ret = -EINVAL; 482 goto out; 483 } 484 485 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 486 FSXDLY(3)); 487 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 488 FSRDLY(3)); 489 490 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 491 case SND_SOC_DAIFMT_CBS_CFS: 492 /* codec is clock and frame slave */ 493 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 494 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 495 496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 497 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 498 499 /* BCLK */ 500 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 501 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 502 /* Frame Sync */ 503 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 504 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 505 506 mcasp->bclk_master = 1; 507 break; 508 case SND_SOC_DAIFMT_CBS_CFM: 509 /* codec is clock slave and frame master */ 510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 512 513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 515 516 /* BCLK */ 517 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 518 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 519 /* Frame Sync */ 520 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 521 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 522 523 mcasp->bclk_master = 1; 524 break; 525 case SND_SOC_DAIFMT_CBM_CFS: 526 /* codec is clock master and frame slave */ 527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 529 530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 531 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 532 533 /* BCLK */ 534 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 535 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 536 /* Frame Sync */ 537 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 538 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 539 540 mcasp->bclk_master = 0; 541 break; 542 case SND_SOC_DAIFMT_CBM_CFM: 543 /* codec is clock and frame master */ 544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 546 547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 549 550 /* BCLK */ 551 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 552 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 553 /* Frame Sync */ 554 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 555 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 556 557 mcasp->bclk_master = 0; 558 break; 559 default: 560 ret = -EINVAL; 561 goto out; 562 } 563 564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 565 case SND_SOC_DAIFMT_IB_NF: 566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 567 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 568 fs_pol_rising = true; 569 break; 570 case SND_SOC_DAIFMT_NB_IF: 571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 572 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 573 fs_pol_rising = false; 574 break; 575 case SND_SOC_DAIFMT_IB_IF: 576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 577 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 578 fs_pol_rising = false; 579 break; 580 case SND_SOC_DAIFMT_NB_NF: 581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 583 fs_pol_rising = true; 584 break; 585 default: 586 ret = -EINVAL; 587 goto out; 588 } 589 590 if (inv_fs) 591 fs_pol_rising = !fs_pol_rising; 592 593 if (fs_pol_rising) { 594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 595 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 596 } else { 597 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 598 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 599 } 600 601 mcasp->dai_fmt = fmt; 602 out: 603 pm_runtime_put(mcasp->dev); 604 return ret; 605 } 606 607 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 608 int div, bool explicit) 609 { 610 pm_runtime_get_sync(mcasp->dev); 611 switch (div_id) { 612 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 613 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 614 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 616 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 617 break; 618 619 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 621 ACLKXDIV(div - 1), ACLKXDIV_MASK); 622 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 623 ACLKRDIV(div - 1), ACLKRDIV_MASK); 624 if (explicit) 625 mcasp->bclk_div = div; 626 break; 627 628 case MCASP_CLKDIV_BCLK_FS_RATIO: 629 /* 630 * BCLK/LRCLK ratio descries how many bit-clock cycles 631 * fit into one frame. The clock ratio is given for a 632 * full period of data (for I2S format both left and 633 * right channels), so it has to be divided by number 634 * of tdm-slots (for I2S - divided by 2). 635 * Instead of storing this ratio, we calculate a new 636 * tdm_slot width by dividing the the ratio by the 637 * number of configured tdm slots. 638 */ 639 mcasp->slot_width = div / mcasp->tdm_slots; 640 if (div % mcasp->tdm_slots) 641 dev_warn(mcasp->dev, 642 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 643 __func__, div, mcasp->tdm_slots); 644 break; 645 646 default: 647 return -EINVAL; 648 } 649 650 pm_runtime_put(mcasp->dev); 651 return 0; 652 } 653 654 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 655 int div) 656 { 657 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 658 659 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 660 } 661 662 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 663 unsigned int freq, int dir) 664 { 665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 666 667 pm_runtime_get_sync(mcasp->dev); 668 669 if (dir == SND_SOC_CLOCK_IN) { 670 switch (clk_id) { 671 case MCASP_CLK_HCLK_AHCLK: 672 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 673 AHCLKXE); 674 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 675 AHCLKRE); 676 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 677 break; 678 case MCASP_CLK_HCLK_AUXCLK: 679 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 680 AHCLKXE); 681 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 682 AHCLKRE); 683 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 684 break; 685 default: 686 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); 687 goto out; 688 } 689 } else { 690 /* Select AUXCLK as HCLK */ 691 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 692 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 693 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 694 } 695 /* 696 * When AHCLK X/R is selected to be output it means that the HCLK is 697 * the same clock - coming via AUXCLK. 698 */ 699 mcasp->sysclk_freq = freq; 700 out: 701 pm_runtime_put(mcasp->dev); 702 return 0; 703 } 704 705 /* All serializers must have equal number of channels */ 706 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 707 int serializers) 708 { 709 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 710 unsigned int *list = (unsigned int *) cl->list; 711 int slots = mcasp->tdm_slots; 712 int i, count = 0; 713 714 if (mcasp->tdm_mask[stream]) 715 slots = hweight32(mcasp->tdm_mask[stream]); 716 717 for (i = 1; i <= slots; i++) 718 list[count++] = i; 719 720 for (i = 2; i <= serializers; i++) 721 list[count++] = i*slots; 722 723 cl->count = count; 724 725 return 0; 726 } 727 728 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 729 { 730 int rx_serializers = 0, tx_serializers = 0, ret, i; 731 732 for (i = 0; i < mcasp->num_serializer; i++) 733 if (mcasp->serial_dir[i] == TX_MODE) 734 tx_serializers++; 735 else if (mcasp->serial_dir[i] == RX_MODE) 736 rx_serializers++; 737 738 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 739 tx_serializers); 740 if (ret) 741 return ret; 742 743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 744 rx_serializers); 745 746 return ret; 747 } 748 749 750 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 751 unsigned int tx_mask, 752 unsigned int rx_mask, 753 int slots, int slot_width) 754 { 755 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 756 757 dev_dbg(mcasp->dev, 758 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 759 __func__, tx_mask, rx_mask, slots, slot_width); 760 761 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 762 dev_err(mcasp->dev, 763 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 764 tx_mask, rx_mask, slots); 765 return -EINVAL; 766 } 767 768 if (slot_width && 769 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 770 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 771 __func__, slot_width); 772 return -EINVAL; 773 } 774 775 mcasp->tdm_slots = slots; 776 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 777 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 778 mcasp->slot_width = slot_width; 779 780 return davinci_mcasp_set_ch_constraints(mcasp); 781 } 782 783 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 784 int sample_width) 785 { 786 u32 fmt; 787 u32 tx_rotate, rx_rotate, slot_width; 788 u32 mask = (1ULL << sample_width) - 1; 789 790 if (mcasp->slot_width) 791 slot_width = mcasp->slot_width; 792 else if (mcasp->max_format_width) 793 slot_width = mcasp->max_format_width; 794 else 795 slot_width = sample_width; 796 /* 797 * TX rotation: 798 * right aligned formats: rotate w/ slot_width 799 * left aligned formats: rotate w/ sample_width 800 * 801 * RX rotation: 802 * right aligned formats: no rotation needed 803 * left aligned formats: rotate w/ (slot_width - sample_width) 804 */ 805 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 806 SND_SOC_DAIFMT_RIGHT_J) { 807 tx_rotate = (slot_width / 4) & 0x7; 808 rx_rotate = 0; 809 } else { 810 tx_rotate = (sample_width / 4) & 0x7; 811 rx_rotate = (slot_width - sample_width) / 4; 812 } 813 814 /* mapping of the XSSZ bit-field as described in the datasheet */ 815 fmt = (slot_width >> 1) - 1; 816 817 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 818 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 819 RXSSZ(0x0F)); 820 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 821 TXSSZ(0x0F)); 822 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 823 TXROT(7)); 824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 825 RXROT(7)); 826 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 827 } 828 829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 830 831 return 0; 832 } 833 834 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 835 int period_words, int channels) 836 { 837 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 838 int i; 839 u8 tx_ser = 0; 840 u8 rx_ser = 0; 841 u8 slots = mcasp->tdm_slots; 842 u8 max_active_serializers = (channels + slots - 1) / slots; 843 u8 max_rx_serializers, max_tx_serializers; 844 int active_serializers, numevt; 845 u32 reg; 846 /* Default configuration */ 847 if (mcasp->version < MCASP_VERSION_3) 848 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 849 850 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 852 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 853 max_tx_serializers = max_active_serializers; 854 max_rx_serializers = 855 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 856 } else { 857 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 858 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 859 max_tx_serializers = 860 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 861 max_rx_serializers = max_active_serializers; 862 } 863 864 for (i = 0; i < mcasp->num_serializer; i++) { 865 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 866 mcasp->serial_dir[i]); 867 if (mcasp->serial_dir[i] == TX_MODE && 868 tx_ser < max_tx_serializers) { 869 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 870 mcasp->dismod, DISMOD_MASK); 871 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 872 tx_ser++; 873 } else if (mcasp->serial_dir[i] == RX_MODE && 874 rx_ser < max_rx_serializers) { 875 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 876 rx_ser++; 877 } else { 878 /* Inactive or unused pin, set it to inactive */ 879 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 880 SRMOD_INACTIVE, SRMOD_MASK); 881 /* If unused, set DISMOD for the pin */ 882 if (mcasp->serial_dir[i] != INACTIVE_MODE) 883 mcasp_mod_bits(mcasp, 884 DAVINCI_MCASP_XRSRCTL_REG(i), 885 mcasp->dismod, DISMOD_MASK); 886 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 887 } 888 } 889 890 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 891 active_serializers = tx_ser; 892 numevt = mcasp->txnumevt; 893 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 894 } else { 895 active_serializers = rx_ser; 896 numevt = mcasp->rxnumevt; 897 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 898 } 899 900 if (active_serializers < max_active_serializers) { 901 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 902 "enabled in mcasp (%d)\n", channels, 903 active_serializers * slots); 904 return -EINVAL; 905 } 906 907 /* AFIFO is not in use */ 908 if (!numevt) { 909 /* Configure the burst size for platform drivers */ 910 if (active_serializers > 1) { 911 /* 912 * If more than one serializers are in use we have one 913 * DMA request to provide data for all serializers. 914 * For example if three serializers are enabled the DMA 915 * need to transfer three words per DMA request. 916 */ 917 dma_data->maxburst = active_serializers; 918 } else { 919 dma_data->maxburst = 0; 920 } 921 922 goto out; 923 } 924 925 if (period_words % active_serializers) { 926 dev_err(mcasp->dev, "Invalid combination of period words and " 927 "active serializers: %d, %d\n", period_words, 928 active_serializers); 929 return -EINVAL; 930 } 931 932 /* 933 * Calculate the optimal AFIFO depth for platform side: 934 * The number of words for numevt need to be in steps of active 935 * serializers. 936 */ 937 numevt = (numevt / active_serializers) * active_serializers; 938 939 while (period_words % numevt && numevt > 0) 940 numevt -= active_serializers; 941 if (numevt <= 0) 942 numevt = active_serializers; 943 944 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 945 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 946 947 /* Configure the burst size for platform drivers */ 948 if (numevt == 1) 949 numevt = 0; 950 dma_data->maxburst = numevt; 951 952 out: 953 mcasp->active_serializers[stream] = active_serializers; 954 955 return 0; 956 } 957 958 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 959 int channels) 960 { 961 int i, active_slots; 962 int total_slots; 963 int active_serializers; 964 u32 mask = 0; 965 u32 busel = 0; 966 967 total_slots = mcasp->tdm_slots; 968 969 /* 970 * If more than one serializer is needed, then use them with 971 * all the specified tdm_slots. Otherwise, one serializer can 972 * cope with the transaction using just as many slots as there 973 * are channels in the stream. 974 */ 975 if (mcasp->tdm_mask[stream]) { 976 active_slots = hweight32(mcasp->tdm_mask[stream]); 977 active_serializers = (channels + active_slots - 1) / 978 active_slots; 979 if (active_serializers == 1) 980 active_slots = channels; 981 for (i = 0; i < total_slots; i++) { 982 if ((1 << i) & mcasp->tdm_mask[stream]) { 983 mask |= (1 << i); 984 if (--active_slots <= 0) 985 break; 986 } 987 } 988 } else { 989 active_serializers = (channels + total_slots - 1) / total_slots; 990 if (active_serializers == 1) 991 active_slots = channels; 992 else 993 active_slots = total_slots; 994 995 for (i = 0; i < active_slots; i++) 996 mask |= (1 << i); 997 } 998 999 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1000 1001 if (!mcasp->dat_port) 1002 busel = TXSEL; 1003 1004 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 1006 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 1007 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1008 FSXMOD(total_slots), FSXMOD(0x1FF)); 1009 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 1011 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 1012 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 1013 FSRMOD(total_slots), FSRMOD(0x1FF)); 1014 /* 1015 * If McASP is set to be TX/RX synchronous and the playback is 1016 * not running already we need to configure the TX slots in 1017 * order to have correct FSX on the bus 1018 */ 1019 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 1020 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1021 FSXMOD(total_slots), FSXMOD(0x1FF)); 1022 } 1023 1024 return 0; 1025 } 1026 1027 /* S/PDIF */ 1028 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 1029 unsigned int rate) 1030 { 1031 u32 cs_value = 0; 1032 u8 *cs_bytes = (u8*) &cs_value; 1033 1034 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 1035 and LSB first */ 1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); 1037 1038 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1039 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1040 1041 /* Set the TX tdm : for all the slots */ 1042 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1043 1044 /* Set the TX clock controls : div = 1 and internal */ 1045 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1046 1047 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1048 1049 /* Only 44100 and 48000 are valid, both have the same setting */ 1050 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 1051 1052 /* Enable the DIT */ 1053 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1054 1055 /* Set S/PDIF channel status bits */ 1056 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 1057 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; 1058 1059 switch (rate) { 1060 case 22050: 1061 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1062 break; 1063 case 24000: 1064 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1065 break; 1066 case 32000: 1067 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1068 break; 1069 case 44100: 1070 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1071 break; 1072 case 48000: 1073 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1074 break; 1075 case 88200: 1076 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1077 break; 1078 case 96000: 1079 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1080 break; 1081 case 176400: 1082 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1083 break; 1084 case 192000: 1085 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1086 break; 1087 default: 1088 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); 1089 return -EINVAL; 1090 } 1091 1092 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); 1093 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); 1094 1095 return 0; 1096 } 1097 1098 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1099 unsigned int sysclk_freq, 1100 unsigned int bclk_freq, bool set) 1101 { 1102 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1103 int div = sysclk_freq / bclk_freq; 1104 int rem = sysclk_freq % bclk_freq; 1105 int error_ppm; 1106 int aux_div = 1; 1107 1108 if (div > (ACLKXDIV_MASK + 1)) { 1109 if (reg & AHCLKXE) { 1110 aux_div = div / (ACLKXDIV_MASK + 1); 1111 if (div % (ACLKXDIV_MASK + 1)) 1112 aux_div++; 1113 1114 sysclk_freq /= aux_div; 1115 div = sysclk_freq / bclk_freq; 1116 rem = sysclk_freq % bclk_freq; 1117 } else if (set) { 1118 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1119 sysclk_freq); 1120 } 1121 } 1122 1123 if (rem != 0) { 1124 if (div == 0 || 1125 ((sysclk_freq / div) - bclk_freq) > 1126 (bclk_freq - (sysclk_freq / (div+1)))) { 1127 div++; 1128 rem = rem - bclk_freq; 1129 } 1130 } 1131 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1132 (int)bclk_freq)) / div - 1000000; 1133 1134 if (set) { 1135 if (error_ppm) 1136 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1137 error_ppm); 1138 1139 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1140 if (reg & AHCLKXE) 1141 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1142 aux_div, 0); 1143 } 1144 1145 return error_ppm; 1146 } 1147 1148 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1149 { 1150 if (!mcasp->txnumevt) 1151 return 0; 1152 1153 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1154 } 1155 1156 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1157 { 1158 if (!mcasp->rxnumevt) 1159 return 0; 1160 1161 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1162 } 1163 1164 static snd_pcm_sframes_t davinci_mcasp_delay( 1165 struct snd_pcm_substream *substream, 1166 struct snd_soc_dai *cpu_dai) 1167 { 1168 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1169 u32 fifo_use; 1170 1171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1172 fifo_use = davinci_mcasp_tx_delay(mcasp); 1173 else 1174 fifo_use = davinci_mcasp_rx_delay(mcasp); 1175 1176 /* 1177 * Divide the used locations with the channel count to get the 1178 * FIFO usage in samples (don't care about partial samples in the 1179 * buffer). 1180 */ 1181 return fifo_use / substream->runtime->channels; 1182 } 1183 1184 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1185 struct snd_pcm_hw_params *params, 1186 struct snd_soc_dai *cpu_dai) 1187 { 1188 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1189 int word_length; 1190 int channels = params_channels(params); 1191 int period_size = params_period_size(params); 1192 int ret; 1193 1194 switch (params_format(params)) { 1195 case SNDRV_PCM_FORMAT_U8: 1196 case SNDRV_PCM_FORMAT_S8: 1197 word_length = 8; 1198 break; 1199 1200 case SNDRV_PCM_FORMAT_U16_LE: 1201 case SNDRV_PCM_FORMAT_S16_LE: 1202 word_length = 16; 1203 break; 1204 1205 case SNDRV_PCM_FORMAT_U24_3LE: 1206 case SNDRV_PCM_FORMAT_S24_3LE: 1207 word_length = 24; 1208 break; 1209 1210 case SNDRV_PCM_FORMAT_U24_LE: 1211 case SNDRV_PCM_FORMAT_S24_LE: 1212 word_length = 24; 1213 break; 1214 1215 case SNDRV_PCM_FORMAT_U32_LE: 1216 case SNDRV_PCM_FORMAT_S32_LE: 1217 word_length = 32; 1218 break; 1219 1220 default: 1221 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1222 return -EINVAL; 1223 } 1224 1225 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1226 if (ret) 1227 return ret; 1228 1229 /* 1230 * If mcasp is BCLK master, and a BCLK divider was not provided by 1231 * the machine driver, we need to calculate the ratio. 1232 */ 1233 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1234 int slots = mcasp->tdm_slots; 1235 int rate = params_rate(params); 1236 int sbits = params_width(params); 1237 1238 if (mcasp->slot_width) 1239 sbits = mcasp->slot_width; 1240 1241 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq, 1242 rate * sbits * slots, true); 1243 } 1244 1245 ret = mcasp_common_hw_param(mcasp, substream->stream, 1246 period_size * channels, channels); 1247 if (ret) 1248 return ret; 1249 1250 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1251 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1252 else 1253 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1254 channels); 1255 1256 if (ret) 1257 return ret; 1258 1259 davinci_config_channel_size(mcasp, word_length); 1260 1261 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 1262 mcasp->channels = channels; 1263 if (!mcasp->max_format_width) 1264 mcasp->max_format_width = word_length; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1271 int cmd, struct snd_soc_dai *cpu_dai) 1272 { 1273 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1274 int ret = 0; 1275 1276 switch (cmd) { 1277 case SNDRV_PCM_TRIGGER_RESUME: 1278 case SNDRV_PCM_TRIGGER_START: 1279 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1280 davinci_mcasp_start(mcasp, substream->stream); 1281 break; 1282 case SNDRV_PCM_TRIGGER_SUSPEND: 1283 case SNDRV_PCM_TRIGGER_STOP: 1284 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1285 davinci_mcasp_stop(mcasp, substream->stream); 1286 break; 1287 1288 default: 1289 ret = -EINVAL; 1290 } 1291 1292 return ret; 1293 } 1294 1295 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params, 1296 struct snd_pcm_hw_rule *rule) 1297 { 1298 struct davinci_mcasp_ruledata *rd = rule->private; 1299 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1300 struct snd_mask nfmt; 1301 int i, slot_width; 1302 1303 snd_mask_none(&nfmt); 1304 slot_width = rd->mcasp->slot_width; 1305 1306 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1307 if (snd_mask_test(fmt, i)) { 1308 if (snd_pcm_format_width(i) <= slot_width) { 1309 snd_mask_set(&nfmt, i); 1310 } 1311 } 1312 } 1313 1314 return snd_mask_refine(fmt, &nfmt); 1315 } 1316 1317 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params, 1318 struct snd_pcm_hw_rule *rule) 1319 { 1320 struct davinci_mcasp_ruledata *rd = rule->private; 1321 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1322 struct snd_mask nfmt; 1323 int i, format_width; 1324 1325 snd_mask_none(&nfmt); 1326 format_width = rd->mcasp->max_format_width; 1327 1328 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1329 if (snd_mask_test(fmt, i)) { 1330 if (snd_pcm_format_width(i) == format_width) { 1331 snd_mask_set(&nfmt, i); 1332 } 1333 } 1334 } 1335 1336 return snd_mask_refine(fmt, &nfmt); 1337 } 1338 1339 static const unsigned int davinci_mcasp_dai_rates[] = { 1340 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1341 88200, 96000, 176400, 192000, 1342 }; 1343 1344 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1345 1346 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1347 struct snd_pcm_hw_rule *rule) 1348 { 1349 struct davinci_mcasp_ruledata *rd = rule->private; 1350 struct snd_interval *ri = 1351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1352 int sbits = params_width(params); 1353 int slots = rd->mcasp->tdm_slots; 1354 struct snd_interval range; 1355 int i; 1356 1357 if (rd->mcasp->slot_width) 1358 sbits = rd->mcasp->slot_width; 1359 1360 snd_interval_any(&range); 1361 range.empty = 1; 1362 1363 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1364 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1365 uint bclk_freq = sbits * slots * 1366 davinci_mcasp_dai_rates[i]; 1367 unsigned int sysclk_freq; 1368 int ppm; 1369 1370 if (rd->mcasp->auxclk_fs_ratio) 1371 sysclk_freq = davinci_mcasp_dai_rates[i] * 1372 rd->mcasp->auxclk_fs_ratio; 1373 else 1374 sysclk_freq = rd->mcasp->sysclk_freq; 1375 1376 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1377 bclk_freq, false); 1378 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1379 if (range.empty) { 1380 range.min = davinci_mcasp_dai_rates[i]; 1381 range.empty = 0; 1382 } 1383 range.max = davinci_mcasp_dai_rates[i]; 1384 } 1385 } 1386 } 1387 1388 dev_dbg(rd->mcasp->dev, 1389 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1390 ri->min, ri->max, range.min, range.max, sbits, slots); 1391 1392 return snd_interval_refine(hw_param_interval(params, rule->var), 1393 &range); 1394 } 1395 1396 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1397 struct snd_pcm_hw_rule *rule) 1398 { 1399 struct davinci_mcasp_ruledata *rd = rule->private; 1400 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1401 struct snd_mask nfmt; 1402 int rate = params_rate(params); 1403 int slots = rd->mcasp->tdm_slots; 1404 int i, count = 0; 1405 1406 snd_mask_none(&nfmt); 1407 1408 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1409 if (snd_mask_test(fmt, i)) { 1410 uint sbits = snd_pcm_format_width(i); 1411 unsigned int sysclk_freq; 1412 int ppm; 1413 1414 if (rd->mcasp->auxclk_fs_ratio) 1415 sysclk_freq = rate * 1416 rd->mcasp->auxclk_fs_ratio; 1417 else 1418 sysclk_freq = rd->mcasp->sysclk_freq; 1419 1420 if (rd->mcasp->slot_width) 1421 sbits = rd->mcasp->slot_width; 1422 1423 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1424 sbits * slots * rate, 1425 false); 1426 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1427 snd_mask_set(&nfmt, i); 1428 count++; 1429 } 1430 } 1431 } 1432 dev_dbg(rd->mcasp->dev, 1433 "%d possible sample format for %d Hz and %d tdm slots\n", 1434 count, rate, slots); 1435 1436 return snd_mask_refine(fmt, &nfmt); 1437 } 1438 1439 static int davinci_mcasp_hw_rule_min_periodsize( 1440 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1441 { 1442 struct snd_interval *period_size = hw_param_interval(params, 1443 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1444 struct snd_interval frames; 1445 1446 snd_interval_any(&frames); 1447 frames.min = 64; 1448 frames.integer = 1; 1449 1450 return snd_interval_refine(period_size, &frames); 1451 } 1452 1453 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1454 struct snd_soc_dai *cpu_dai) 1455 { 1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1457 struct davinci_mcasp_ruledata *ruledata = 1458 &mcasp->ruledata[substream->stream]; 1459 u32 max_channels = 0; 1460 int i, dir, ret; 1461 int tdm_slots = mcasp->tdm_slots; 1462 1463 /* Do not allow more then one stream per direction */ 1464 if (mcasp->substreams[substream->stream]) 1465 return -EBUSY; 1466 1467 mcasp->substreams[substream->stream] = substream; 1468 1469 if (mcasp->tdm_mask[substream->stream]) 1470 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1471 1472 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1473 return 0; 1474 1475 /* 1476 * Limit the maximum allowed channels for the first stream: 1477 * number of serializers for the direction * tdm slots per serializer 1478 */ 1479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1480 dir = TX_MODE; 1481 else 1482 dir = RX_MODE; 1483 1484 for (i = 0; i < mcasp->num_serializer; i++) { 1485 if (mcasp->serial_dir[i] == dir) 1486 max_channels++; 1487 } 1488 ruledata->serializers = max_channels; 1489 ruledata->mcasp = mcasp; 1490 max_channels *= tdm_slots; 1491 /* 1492 * If the already active stream has less channels than the calculated 1493 * limit based on the seirializers * tdm_slots, and only one serializer 1494 * is in use we need to use that as a constraint for the second stream. 1495 * Otherwise (first stream or less allowed channels or more than one 1496 * serializer in use) we use the calculated constraint. 1497 */ 1498 if (mcasp->channels && mcasp->channels < max_channels && 1499 ruledata->serializers == 1) 1500 max_channels = mcasp->channels; 1501 /* 1502 * But we can always allow channels upto the amount of 1503 * the available tdm_slots. 1504 */ 1505 if (max_channels < tdm_slots) 1506 max_channels = tdm_slots; 1507 1508 snd_pcm_hw_constraint_minmax(substream->runtime, 1509 SNDRV_PCM_HW_PARAM_CHANNELS, 1510 0, max_channels); 1511 1512 snd_pcm_hw_constraint_list(substream->runtime, 1513 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1514 &mcasp->chconstr[substream->stream]); 1515 1516 if (mcasp->max_format_width) { 1517 /* 1518 * Only allow formats which require same amount of bits on the 1519 * bus as the currently running stream 1520 */ 1521 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1522 SNDRV_PCM_HW_PARAM_FORMAT, 1523 davinci_mcasp_hw_rule_format_width, 1524 ruledata, 1525 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1526 if (ret) 1527 return ret; 1528 } 1529 else if (mcasp->slot_width) { 1530 /* Only allow formats require <= slot_width bits on the bus */ 1531 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1532 SNDRV_PCM_HW_PARAM_FORMAT, 1533 davinci_mcasp_hw_rule_slot_width, 1534 ruledata, 1535 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1536 if (ret) 1537 return ret; 1538 } 1539 1540 /* 1541 * If we rely on implicit BCLK divider setting we should 1542 * set constraints based on what we can provide. 1543 */ 1544 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1545 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1546 SNDRV_PCM_HW_PARAM_RATE, 1547 davinci_mcasp_hw_rule_rate, 1548 ruledata, 1549 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1550 if (ret) 1551 return ret; 1552 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1553 SNDRV_PCM_HW_PARAM_FORMAT, 1554 davinci_mcasp_hw_rule_format, 1555 ruledata, 1556 SNDRV_PCM_HW_PARAM_RATE, -1); 1557 if (ret) 1558 return ret; 1559 } 1560 1561 snd_pcm_hw_rule_add(substream->runtime, 0, 1562 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1563 davinci_mcasp_hw_rule_min_periodsize, NULL, 1564 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1565 1566 return 0; 1567 } 1568 1569 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1570 struct snd_soc_dai *cpu_dai) 1571 { 1572 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1573 1574 mcasp->substreams[substream->stream] = NULL; 1575 mcasp->active_serializers[substream->stream] = 0; 1576 1577 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1578 return; 1579 1580 if (!snd_soc_dai_active(cpu_dai)) { 1581 mcasp->channels = 0; 1582 mcasp->max_format_width = 0; 1583 } 1584 } 1585 1586 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1587 .startup = davinci_mcasp_startup, 1588 .shutdown = davinci_mcasp_shutdown, 1589 .trigger = davinci_mcasp_trigger, 1590 .delay = davinci_mcasp_delay, 1591 .hw_params = davinci_mcasp_hw_params, 1592 .set_fmt = davinci_mcasp_set_dai_fmt, 1593 .set_clkdiv = davinci_mcasp_set_clkdiv, 1594 .set_sysclk = davinci_mcasp_set_sysclk, 1595 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1596 }; 1597 1598 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1599 { 1600 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1601 1602 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1603 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 1604 1605 return 0; 1606 } 1607 1608 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1609 1610 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1611 SNDRV_PCM_FMTBIT_U8 | \ 1612 SNDRV_PCM_FMTBIT_S16_LE | \ 1613 SNDRV_PCM_FMTBIT_U16_LE | \ 1614 SNDRV_PCM_FMTBIT_S24_LE | \ 1615 SNDRV_PCM_FMTBIT_U24_LE | \ 1616 SNDRV_PCM_FMTBIT_S24_3LE | \ 1617 SNDRV_PCM_FMTBIT_U24_3LE | \ 1618 SNDRV_PCM_FMTBIT_S32_LE | \ 1619 SNDRV_PCM_FMTBIT_U32_LE) 1620 1621 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1622 { 1623 .name = "davinci-mcasp.0", 1624 .probe = davinci_mcasp_dai_probe, 1625 .playback = { 1626 .stream_name = "IIS Playback", 1627 .channels_min = 1, 1628 .channels_max = 32 * 16, 1629 .rates = DAVINCI_MCASP_RATES, 1630 .formats = DAVINCI_MCASP_PCM_FMTS, 1631 }, 1632 .capture = { 1633 .stream_name = "IIS Capture", 1634 .channels_min = 1, 1635 .channels_max = 32 * 16, 1636 .rates = DAVINCI_MCASP_RATES, 1637 .formats = DAVINCI_MCASP_PCM_FMTS, 1638 }, 1639 .ops = &davinci_mcasp_dai_ops, 1640 1641 .symmetric_rates = 1, 1642 }, 1643 { 1644 .name = "davinci-mcasp.1", 1645 .probe = davinci_mcasp_dai_probe, 1646 .playback = { 1647 .stream_name = "DIT Playback", 1648 .channels_min = 1, 1649 .channels_max = 384, 1650 .rates = DAVINCI_MCASP_RATES, 1651 .formats = DAVINCI_MCASP_PCM_FMTS, 1652 }, 1653 .ops = &davinci_mcasp_dai_ops, 1654 }, 1655 1656 }; 1657 1658 static const struct snd_soc_component_driver davinci_mcasp_component = { 1659 .name = "davinci-mcasp", 1660 }; 1661 1662 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1663 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1664 .tx_dma_offset = 0x400, 1665 .rx_dma_offset = 0x400, 1666 .version = MCASP_VERSION_1, 1667 }; 1668 1669 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1670 .tx_dma_offset = 0x2000, 1671 .rx_dma_offset = 0x2000, 1672 .version = MCASP_VERSION_2, 1673 }; 1674 1675 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1676 .tx_dma_offset = 0, 1677 .rx_dma_offset = 0, 1678 .version = MCASP_VERSION_3, 1679 }; 1680 1681 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1682 /* The CFG port offset will be calculated if it is needed */ 1683 .tx_dma_offset = 0, 1684 .rx_dma_offset = 0, 1685 .version = MCASP_VERSION_4, 1686 }; 1687 1688 static const struct of_device_id mcasp_dt_ids[] = { 1689 { 1690 .compatible = "ti,dm646x-mcasp-audio", 1691 .data = &dm646x_mcasp_pdata, 1692 }, 1693 { 1694 .compatible = "ti,da830-mcasp-audio", 1695 .data = &da830_mcasp_pdata, 1696 }, 1697 { 1698 .compatible = "ti,am33xx-mcasp-audio", 1699 .data = &am33xx_mcasp_pdata, 1700 }, 1701 { 1702 .compatible = "ti,dra7-mcasp-audio", 1703 .data = &dra7_mcasp_pdata, 1704 }, 1705 { /* sentinel */ } 1706 }; 1707 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1708 1709 static int mcasp_reparent_fck(struct platform_device *pdev) 1710 { 1711 struct device_node *node = pdev->dev.of_node; 1712 struct clk *gfclk, *parent_clk; 1713 const char *parent_name; 1714 int ret; 1715 1716 if (!node) 1717 return 0; 1718 1719 parent_name = of_get_property(node, "fck_parent", NULL); 1720 if (!parent_name) 1721 return 0; 1722 1723 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1724 1725 gfclk = clk_get(&pdev->dev, "fck"); 1726 if (IS_ERR(gfclk)) { 1727 dev_err(&pdev->dev, "failed to get fck\n"); 1728 return PTR_ERR(gfclk); 1729 } 1730 1731 parent_clk = clk_get(NULL, parent_name); 1732 if (IS_ERR(parent_clk)) { 1733 dev_err(&pdev->dev, "failed to get parent clock\n"); 1734 ret = PTR_ERR(parent_clk); 1735 goto err1; 1736 } 1737 1738 ret = clk_set_parent(gfclk, parent_clk); 1739 if (ret) { 1740 dev_err(&pdev->dev, "failed to reparent fck\n"); 1741 goto err2; 1742 } 1743 1744 err2: 1745 clk_put(parent_clk); 1746 err1: 1747 clk_put(gfclk); 1748 return ret; 1749 } 1750 1751 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( 1752 struct platform_device *pdev) 1753 { 1754 struct device_node *np = pdev->dev.of_node; 1755 struct davinci_mcasp_pdata *pdata = NULL; 1756 const struct of_device_id *match = 1757 of_match_device(mcasp_dt_ids, &pdev->dev); 1758 struct of_phandle_args dma_spec; 1759 1760 const u32 *of_serial_dir32; 1761 u32 val; 1762 int i, ret = 0; 1763 1764 if (pdev->dev.platform_data) { 1765 pdata = pdev->dev.platform_data; 1766 pdata->dismod = DISMOD_LOW; 1767 return pdata; 1768 } else if (match) { 1769 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), 1770 GFP_KERNEL); 1771 if (!pdata) 1772 return NULL; 1773 } else { 1774 /* control shouldn't reach here. something is wrong */ 1775 ret = -EINVAL; 1776 goto nodata; 1777 } 1778 1779 ret = of_property_read_u32(np, "op-mode", &val); 1780 if (ret >= 0) 1781 pdata->op_mode = val; 1782 1783 ret = of_property_read_u32(np, "tdm-slots", &val); 1784 if (ret >= 0) { 1785 if (val < 2 || val > 32) { 1786 dev_err(&pdev->dev, 1787 "tdm-slots must be in rage [2-32]\n"); 1788 ret = -EINVAL; 1789 goto nodata; 1790 } 1791 1792 pdata->tdm_slots = val; 1793 } 1794 1795 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1796 val /= sizeof(u32); 1797 if (of_serial_dir32) { 1798 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1799 (sizeof(*of_serial_dir) * val), 1800 GFP_KERNEL); 1801 if (!of_serial_dir) { 1802 ret = -ENOMEM; 1803 goto nodata; 1804 } 1805 1806 for (i = 0; i < val; i++) 1807 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1808 1809 pdata->num_serializer = val; 1810 pdata->serial_dir = of_serial_dir; 1811 } 1812 1813 ret = of_property_match_string(np, "dma-names", "tx"); 1814 if (ret < 0) 1815 goto nodata; 1816 1817 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1818 &dma_spec); 1819 if (ret < 0) 1820 goto nodata; 1821 1822 pdata->tx_dma_channel = dma_spec.args[0]; 1823 1824 /* RX is not valid in DIT mode */ 1825 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { 1826 ret = of_property_match_string(np, "dma-names", "rx"); 1827 if (ret < 0) 1828 goto nodata; 1829 1830 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1831 &dma_spec); 1832 if (ret < 0) 1833 goto nodata; 1834 1835 pdata->rx_dma_channel = dma_spec.args[0]; 1836 } 1837 1838 ret = of_property_read_u32(np, "tx-num-evt", &val); 1839 if (ret >= 0) 1840 pdata->txnumevt = val; 1841 1842 ret = of_property_read_u32(np, "rx-num-evt", &val); 1843 if (ret >= 0) 1844 pdata->rxnumevt = val; 1845 1846 ret = of_property_read_u32(np, "sram-size-playback", &val); 1847 if (ret >= 0) 1848 pdata->sram_size_playback = val; 1849 1850 ret = of_property_read_u32(np, "sram-size-capture", &val); 1851 if (ret >= 0) 1852 pdata->sram_size_capture = val; 1853 1854 ret = of_property_read_u32(np, "dismod", &val); 1855 if (ret >= 0) { 1856 if (val == 0 || val == 2 || val == 3) { 1857 pdata->dismod = DISMOD_VAL(val); 1858 } else { 1859 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1860 pdata->dismod = DISMOD_LOW; 1861 } 1862 } else { 1863 pdata->dismod = DISMOD_LOW; 1864 } 1865 1866 return pdata; 1867 1868 nodata: 1869 if (ret < 0) { 1870 dev_err(&pdev->dev, "Error populating platform data, err %d\n", 1871 ret); 1872 pdata = NULL; 1873 } 1874 return pdata; 1875 } 1876 1877 enum { 1878 PCM_EDMA, 1879 PCM_SDMA, 1880 PCM_UDMA, 1881 }; 1882 static const char *sdma_prefix = "ti,omap"; 1883 1884 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 1885 { 1886 struct dma_chan *chan; 1887 const char *tmp; 1888 int ret = PCM_EDMA; 1889 1890 if (!mcasp->dev->of_node) 1891 return PCM_EDMA; 1892 1893 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 1894 chan = dma_request_chan(mcasp->dev, tmp); 1895 if (IS_ERR(chan)) { 1896 if (PTR_ERR(chan) != -EPROBE_DEFER) 1897 dev_err(mcasp->dev, 1898 "Can't verify DMA configuration (%ld)\n", 1899 PTR_ERR(chan)); 1900 return PTR_ERR(chan); 1901 } 1902 if (WARN_ON(!chan->device || !chan->device->dev)) { 1903 dma_release_channel(chan); 1904 return -EINVAL; 1905 } 1906 1907 if (chan->device->dev->of_node) 1908 ret = of_property_read_string(chan->device->dev->of_node, 1909 "compatible", &tmp); 1910 else 1911 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 1912 1913 dma_release_channel(chan); 1914 if (ret) 1915 return ret; 1916 1917 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 1918 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 1919 return PCM_SDMA; 1920 else if (strstr(tmp, "udmap")) 1921 return PCM_UDMA; 1922 1923 return PCM_EDMA; 1924 } 1925 1926 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 1927 { 1928 int i; 1929 u32 offset = 0; 1930 1931 if (pdata->version != MCASP_VERSION_4) 1932 return pdata->tx_dma_offset; 1933 1934 for (i = 0; i < pdata->num_serializer; i++) { 1935 if (pdata->serial_dir[i] == TX_MODE) { 1936 if (!offset) { 1937 offset = DAVINCI_MCASP_TXBUF_REG(i); 1938 } else { 1939 pr_err("%s: Only one serializer allowed!\n", 1940 __func__); 1941 break; 1942 } 1943 } 1944 } 1945 1946 return offset; 1947 } 1948 1949 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 1950 { 1951 int i; 1952 u32 offset = 0; 1953 1954 if (pdata->version != MCASP_VERSION_4) 1955 return pdata->rx_dma_offset; 1956 1957 for (i = 0; i < pdata->num_serializer; i++) { 1958 if (pdata->serial_dir[i] == RX_MODE) { 1959 if (!offset) { 1960 offset = DAVINCI_MCASP_RXBUF_REG(i); 1961 } else { 1962 pr_err("%s: Only one serializer allowed!\n", 1963 __func__); 1964 break; 1965 } 1966 } 1967 } 1968 1969 return offset; 1970 } 1971 1972 #ifdef CONFIG_GPIOLIB 1973 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 1974 { 1975 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1976 1977 if (mcasp->num_serializer && offset < mcasp->num_serializer && 1978 mcasp->serial_dir[offset] != INACTIVE_MODE) { 1979 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 1980 return -EBUSY; 1981 } 1982 1983 /* Do not change the PIN yet */ 1984 1985 return pm_runtime_get_sync(mcasp->dev); 1986 } 1987 1988 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 1989 { 1990 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1991 1992 /* Set the direction to input */ 1993 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1994 1995 /* Set the pin as McASP pin */ 1996 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1997 1998 pm_runtime_put_sync(mcasp->dev); 1999 } 2000 2001 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 2002 unsigned offset, int value) 2003 { 2004 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2005 u32 val; 2006 2007 if (value) 2008 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2009 else 2010 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2011 2012 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2013 if (!(val & BIT(offset))) { 2014 /* Set the pin as GPIO pin */ 2015 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2016 2017 /* Set the direction to output */ 2018 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2019 } 2020 2021 return 0; 2022 } 2023 2024 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, 2025 int value) 2026 { 2027 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2028 2029 if (value) 2030 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2031 else 2032 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2033 } 2034 2035 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 2036 unsigned offset) 2037 { 2038 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2039 u32 val; 2040 2041 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2042 if (!(val & BIT(offset))) { 2043 /* Set the direction to input */ 2044 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2045 2046 /* Set the pin as GPIO pin */ 2047 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2048 } 2049 2050 return 0; 2051 } 2052 2053 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 2054 { 2055 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2056 u32 val; 2057 2058 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 2059 if (val & BIT(offset)) 2060 return 1; 2061 2062 return 0; 2063 } 2064 2065 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 2066 unsigned offset) 2067 { 2068 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2069 u32 val; 2070 2071 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 2072 if (val & BIT(offset)) 2073 return 0; 2074 2075 return 1; 2076 } 2077 2078 static const struct gpio_chip davinci_mcasp_template_chip = { 2079 .owner = THIS_MODULE, 2080 .request = davinci_mcasp_gpio_request, 2081 .free = davinci_mcasp_gpio_free, 2082 .direction_output = davinci_mcasp_gpio_direction_out, 2083 .set = davinci_mcasp_gpio_set, 2084 .direction_input = davinci_mcasp_gpio_direction_in, 2085 .get = davinci_mcasp_gpio_get, 2086 .get_direction = davinci_mcasp_gpio_get_direction, 2087 .base = -1, 2088 .ngpio = 32, 2089 }; 2090 2091 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2092 { 2093 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) 2094 return 0; 2095 2096 mcasp->gpio_chip = davinci_mcasp_template_chip; 2097 mcasp->gpio_chip.label = dev_name(mcasp->dev); 2098 mcasp->gpio_chip.parent = mcasp->dev; 2099 #ifdef CONFIG_OF_GPIO 2100 mcasp->gpio_chip.of_node = mcasp->dev->of_node; 2101 #endif 2102 2103 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 2104 } 2105 2106 #else /* CONFIG_GPIOLIB */ 2107 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2108 { 2109 return 0; 2110 } 2111 #endif /* CONFIG_GPIOLIB */ 2112 2113 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp) 2114 { 2115 struct device_node *np = mcasp->dev->of_node; 2116 int ret; 2117 u32 val; 2118 2119 if (!np) 2120 return 0; 2121 2122 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val); 2123 if (ret >= 0) 2124 mcasp->auxclk_fs_ratio = val; 2125 2126 return 0; 2127 } 2128 2129 static int davinci_mcasp_probe(struct platform_device *pdev) 2130 { 2131 struct snd_dmaengine_dai_dma_data *dma_data; 2132 struct resource *mem, *res, *dat; 2133 struct davinci_mcasp_pdata *pdata; 2134 struct davinci_mcasp *mcasp; 2135 char *irq_name; 2136 int *dma; 2137 int irq; 2138 int ret; 2139 2140 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2141 dev_err(&pdev->dev, "No platform data supplied\n"); 2142 return -EINVAL; 2143 } 2144 2145 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2146 GFP_KERNEL); 2147 if (!mcasp) 2148 return -ENOMEM; 2149 2150 pdata = davinci_mcasp_set_pdata_from_of(pdev); 2151 if (!pdata) { 2152 dev_err(&pdev->dev, "no platform data\n"); 2153 return -EINVAL; 2154 } 2155 2156 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2157 if (!mem) { 2158 dev_warn(mcasp->dev, 2159 "\"mpu\" mem resource not found, using index 0\n"); 2160 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2161 if (!mem) { 2162 dev_err(&pdev->dev, "no mem resource?\n"); 2163 return -ENODEV; 2164 } 2165 } 2166 2167 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2168 if (IS_ERR(mcasp->base)) 2169 return PTR_ERR(mcasp->base); 2170 2171 pm_runtime_enable(&pdev->dev); 2172 2173 mcasp->op_mode = pdata->op_mode; 2174 /* sanity check for tdm slots parameter */ 2175 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2176 if (pdata->tdm_slots < 2) { 2177 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2178 pdata->tdm_slots); 2179 mcasp->tdm_slots = 2; 2180 } else if (pdata->tdm_slots > 32) { 2181 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2182 pdata->tdm_slots); 2183 mcasp->tdm_slots = 32; 2184 } else { 2185 mcasp->tdm_slots = pdata->tdm_slots; 2186 } 2187 } 2188 2189 mcasp->num_serializer = pdata->num_serializer; 2190 #ifdef CONFIG_PM 2191 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2192 mcasp->num_serializer, sizeof(u32), 2193 GFP_KERNEL); 2194 if (!mcasp->context.xrsr_regs) { 2195 ret = -ENOMEM; 2196 goto err; 2197 } 2198 #endif 2199 mcasp->serial_dir = pdata->serial_dir; 2200 mcasp->version = pdata->version; 2201 mcasp->txnumevt = pdata->txnumevt; 2202 mcasp->rxnumevt = pdata->rxnumevt; 2203 mcasp->dismod = pdata->dismod; 2204 2205 mcasp->dev = &pdev->dev; 2206 2207 irq = platform_get_irq_byname(pdev, "common"); 2208 if (irq >= 0) { 2209 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2210 dev_name(&pdev->dev)); 2211 if (!irq_name) { 2212 ret = -ENOMEM; 2213 goto err; 2214 } 2215 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2216 davinci_mcasp_common_irq_handler, 2217 IRQF_ONESHOT | IRQF_SHARED, 2218 irq_name, mcasp); 2219 if (ret) { 2220 dev_err(&pdev->dev, "common IRQ request failed\n"); 2221 goto err; 2222 } 2223 2224 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2225 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2226 } 2227 2228 irq = platform_get_irq_byname(pdev, "rx"); 2229 if (irq >= 0) { 2230 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2231 dev_name(&pdev->dev)); 2232 if (!irq_name) { 2233 ret = -ENOMEM; 2234 goto err; 2235 } 2236 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2237 davinci_mcasp_rx_irq_handler, 2238 IRQF_ONESHOT, irq_name, mcasp); 2239 if (ret) { 2240 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2241 goto err; 2242 } 2243 2244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2245 } 2246 2247 irq = platform_get_irq_byname(pdev, "tx"); 2248 if (irq >= 0) { 2249 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2250 dev_name(&pdev->dev)); 2251 if (!irq_name) { 2252 ret = -ENOMEM; 2253 goto err; 2254 } 2255 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2256 davinci_mcasp_tx_irq_handler, 2257 IRQF_ONESHOT, irq_name, mcasp); 2258 if (ret) { 2259 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2260 goto err; 2261 } 2262 2263 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2264 } 2265 2266 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2267 if (dat) 2268 mcasp->dat_port = true; 2269 2270 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2271 if (dat) 2272 dma_data->addr = dat->start; 2273 else 2274 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); 2275 2276 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; 2277 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 2278 if (res) 2279 *dma = res->start; 2280 else 2281 *dma = pdata->tx_dma_channel; 2282 2283 /* dmaengine filter data for DT and non-DT boot */ 2284 if (pdev->dev.of_node) 2285 dma_data->filter_data = "tx"; 2286 else 2287 dma_data->filter_data = dma; 2288 2289 /* RX is not valid in DIT mode */ 2290 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2291 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2292 if (dat) 2293 dma_data->addr = dat->start; 2294 else 2295 dma_data->addr = 2296 mem->start + davinci_mcasp_rxdma_offset(pdata); 2297 2298 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; 2299 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 2300 if (res) 2301 *dma = res->start; 2302 else 2303 *dma = pdata->rx_dma_channel; 2304 2305 /* dmaengine filter data for DT and non-DT boot */ 2306 if (pdev->dev.of_node) 2307 dma_data->filter_data = "rx"; 2308 else 2309 dma_data->filter_data = dma; 2310 } 2311 2312 if (mcasp->version < MCASP_VERSION_3) { 2313 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2314 /* dma_params->dma_addr is pointing to the data port address */ 2315 mcasp->dat_port = true; 2316 } else { 2317 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2318 } 2319 2320 /* Allocate memory for long enough list for all possible 2321 * scenarios. Maximum number tdm slots is 32 and there cannot 2322 * be more serializers than given in the configuration. The 2323 * serializer directions could be taken into account, but it 2324 * would make code much more complex and save only couple of 2325 * bytes. 2326 */ 2327 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2328 devm_kcalloc(mcasp->dev, 2329 32 + mcasp->num_serializer - 1, 2330 sizeof(unsigned int), 2331 GFP_KERNEL); 2332 2333 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2334 devm_kcalloc(mcasp->dev, 2335 32 + mcasp->num_serializer - 1, 2336 sizeof(unsigned int), 2337 GFP_KERNEL); 2338 2339 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2340 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2341 ret = -ENOMEM; 2342 goto err; 2343 } 2344 2345 ret = davinci_mcasp_set_ch_constraints(mcasp); 2346 if (ret) 2347 goto err; 2348 2349 dev_set_drvdata(&pdev->dev, mcasp); 2350 2351 mcasp_reparent_fck(pdev); 2352 2353 /* All PINS as McASP */ 2354 pm_runtime_get_sync(mcasp->dev); 2355 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2356 pm_runtime_put(mcasp->dev); 2357 2358 ret = davinci_mcasp_init_gpiochip(mcasp); 2359 if (ret) 2360 goto err; 2361 2362 ret = davinci_mcasp_get_dt_params(mcasp); 2363 if (ret) 2364 return -EINVAL; 2365 2366 ret = devm_snd_soc_register_component(&pdev->dev, 2367 &davinci_mcasp_component, 2368 &davinci_mcasp_dai[pdata->op_mode], 1); 2369 2370 if (ret != 0) 2371 goto err; 2372 2373 ret = davinci_mcasp_get_dma_type(mcasp); 2374 switch (ret) { 2375 case PCM_EDMA: 2376 ret = edma_pcm_platform_register(&pdev->dev); 2377 break; 2378 case PCM_SDMA: 2379 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2380 break; 2381 case PCM_UDMA: 2382 ret = udma_pcm_platform_register(&pdev->dev); 2383 break; 2384 default: 2385 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2386 case -EPROBE_DEFER: 2387 goto err; 2388 break; 2389 } 2390 2391 if (ret) { 2392 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2393 goto err; 2394 } 2395 2396 return 0; 2397 2398 err: 2399 pm_runtime_disable(&pdev->dev); 2400 return ret; 2401 } 2402 2403 static int davinci_mcasp_remove(struct platform_device *pdev) 2404 { 2405 pm_runtime_disable(&pdev->dev); 2406 2407 return 0; 2408 } 2409 2410 #ifdef CONFIG_PM 2411 static int davinci_mcasp_runtime_suspend(struct device *dev) 2412 { 2413 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2414 struct davinci_mcasp_context *context = &mcasp->context; 2415 u32 reg; 2416 int i; 2417 2418 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2419 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2420 2421 if (mcasp->txnumevt) { 2422 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2423 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2424 } 2425 if (mcasp->rxnumevt) { 2426 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2427 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2428 } 2429 2430 for (i = 0; i < mcasp->num_serializer; i++) 2431 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2432 DAVINCI_MCASP_XRSRCTL_REG(i)); 2433 2434 return 0; 2435 } 2436 2437 static int davinci_mcasp_runtime_resume(struct device *dev) 2438 { 2439 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2440 struct davinci_mcasp_context *context = &mcasp->context; 2441 u32 reg; 2442 int i; 2443 2444 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2445 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2446 2447 if (mcasp->txnumevt) { 2448 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2449 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2450 } 2451 if (mcasp->rxnumevt) { 2452 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2453 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2454 } 2455 2456 for (i = 0; i < mcasp->num_serializer; i++) 2457 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2458 context->xrsr_regs[i]); 2459 2460 return 0; 2461 } 2462 2463 #endif 2464 2465 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2466 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2467 davinci_mcasp_runtime_resume, 2468 NULL) 2469 }; 2470 2471 static struct platform_driver davinci_mcasp_driver = { 2472 .probe = davinci_mcasp_probe, 2473 .remove = davinci_mcasp_remove, 2474 .driver = { 2475 .name = "davinci-mcasp", 2476 .pm = &davinci_mcasp_pm_ops, 2477 .of_match_table = mcasp_dt_ids, 2478 }, 2479 }; 2480 2481 module_platform_driver(davinci_mcasp_driver); 2482 2483 MODULE_AUTHOR("Steve Chen"); 2484 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2485 MODULE_LICENSE("GPL"); 2486