1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_data/davinci_asp.h> 27 #include <linux/math64.h> 28 #include <linux/bitmap.h> 29 #include <linux/gpio/driver.h> 30 31 #include <sound/asoundef.h> 32 #include <sound/core.h> 33 #include <sound/pcm.h> 34 #include <sound/pcm_params.h> 35 #include <sound/initval.h> 36 #include <sound/soc.h> 37 #include <sound/dmaengine_pcm.h> 38 39 #include "edma-pcm.h" 40 #include "sdma-pcm.h" 41 #include "davinci-mcasp.h" 42 43 #define MCASP_MAX_AFIFO_DEPTH 64 44 45 #ifdef CONFIG_PM 46 static u32 context_regs[] = { 47 DAVINCI_MCASP_TXFMCTL_REG, 48 DAVINCI_MCASP_RXFMCTL_REG, 49 DAVINCI_MCASP_TXFMT_REG, 50 DAVINCI_MCASP_RXFMT_REG, 51 DAVINCI_MCASP_ACLKXCTL_REG, 52 DAVINCI_MCASP_ACLKRCTL_REG, 53 DAVINCI_MCASP_AHCLKXCTL_REG, 54 DAVINCI_MCASP_AHCLKRCTL_REG, 55 DAVINCI_MCASP_PDIR_REG, 56 DAVINCI_MCASP_PFUNC_REG, 57 DAVINCI_MCASP_RXMASK_REG, 58 DAVINCI_MCASP_TXMASK_REG, 59 DAVINCI_MCASP_RXTDM_REG, 60 DAVINCI_MCASP_TXTDM_REG, 61 }; 62 63 struct davinci_mcasp_context { 64 u32 config_regs[ARRAY_SIZE(context_regs)]; 65 u32 afifo_regs[2]; /* for read/write fifo control registers */ 66 u32 *xrsr_regs; /* for serializer configuration */ 67 bool pm_state; 68 }; 69 #endif 70 71 struct davinci_mcasp_ruledata { 72 struct davinci_mcasp *mcasp; 73 int serializers; 74 }; 75 76 struct davinci_mcasp { 77 struct snd_dmaengine_dai_dma_data dma_data[2]; 78 void __iomem *base; 79 u32 fifo_base; 80 struct device *dev; 81 struct snd_pcm_substream *substreams[2]; 82 unsigned int dai_fmt; 83 84 /* McASP specific data */ 85 int tdm_slots; 86 u32 tdm_mask[2]; 87 int slot_width; 88 u8 op_mode; 89 u8 dismod; 90 u8 num_serializer; 91 u8 *serial_dir; 92 u8 version; 93 u8 bclk_div; 94 int streams; 95 u32 irq_request[2]; 96 int dma_request[2]; 97 98 int sysclk_freq; 99 bool bclk_master; 100 u32 auxclk_fs_ratio; 101 102 unsigned long pdir; /* Pin direction bitfield */ 103 104 /* McASP FIFO related */ 105 u8 txnumevt; 106 u8 rxnumevt; 107 108 bool dat_port; 109 110 /* Used for comstraint setting on the second stream */ 111 u32 channels; 112 113 #ifdef CONFIG_GPIOLIB 114 struct gpio_chip gpio_chip; 115 #endif 116 117 #ifdef CONFIG_PM 118 struct davinci_mcasp_context context; 119 #endif 120 121 struct davinci_mcasp_ruledata ruledata[2]; 122 struct snd_pcm_hw_constraint_list chconstr[2]; 123 }; 124 125 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 126 u32 val) 127 { 128 void __iomem *reg = mcasp->base + offset; 129 __raw_writel(__raw_readl(reg) | val, reg); 130 } 131 132 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 133 u32 val) 134 { 135 void __iomem *reg = mcasp->base + offset; 136 __raw_writel((__raw_readl(reg) & ~(val)), reg); 137 } 138 139 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 140 u32 val, u32 mask) 141 { 142 void __iomem *reg = mcasp->base + offset; 143 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 144 } 145 146 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 147 u32 val) 148 { 149 __raw_writel(val, mcasp->base + offset); 150 } 151 152 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 153 { 154 return (u32)__raw_readl(mcasp->base + offset); 155 } 156 157 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 158 { 159 int i = 0; 160 161 mcasp_set_bits(mcasp, ctl_reg, val); 162 163 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 164 /* loop count is to avoid the lock-up */ 165 for (i = 0; i < 1000; i++) { 166 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 167 break; 168 } 169 170 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 171 printk(KERN_ERR "GBLCTL write error\n"); 172 } 173 174 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 175 { 176 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 177 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 178 179 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 180 } 181 182 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 183 { 184 u32 bit = PIN_BIT_AMUTE; 185 186 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 187 if (enable) 188 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 189 else 190 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 191 } 192 } 193 194 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 195 { 196 u32 bit; 197 198 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) { 199 if (enable) 200 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 201 else 202 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 203 } 204 } 205 206 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 207 { 208 if (mcasp->rxnumevt) { /* enable FIFO */ 209 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 210 211 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 212 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 213 } 214 215 /* Start clocks */ 216 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 218 /* 219 * When ASYNC == 0 the transmit and receive sections operate 220 * synchronously from the transmit clock and frame sync. We need to make 221 * sure that the TX signlas are enabled when starting reception. 222 */ 223 if (mcasp_is_synchronous(mcasp)) { 224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 226 } 227 228 /* Activate serializer(s) */ 229 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 231 /* Release RX state machine */ 232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 233 /* Release Frame Sync generator */ 234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 235 if (mcasp_is_synchronous(mcasp)) 236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 237 238 /* enable receive IRQs */ 239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 240 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 241 } 242 243 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 244 { 245 u32 cnt; 246 247 if (mcasp->txnumevt) { /* enable FIFO */ 248 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 249 250 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 251 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 252 } 253 254 /* Start clocks */ 255 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 256 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 257 mcasp_set_clk_pdir(mcasp, true); 258 259 /* Activate serializer(s) */ 260 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 261 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 262 263 /* wait for XDATA to be cleared */ 264 cnt = 0; 265 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 266 (cnt < 100000)) 267 cnt++; 268 269 mcasp_set_axr_pdir(mcasp, true); 270 271 /* Release TX state machine */ 272 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 273 /* Release Frame Sync generator */ 274 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 275 276 /* enable transmit IRQs */ 277 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 278 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 279 } 280 281 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 282 { 283 mcasp->streams++; 284 285 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 286 mcasp_start_tx(mcasp); 287 else 288 mcasp_start_rx(mcasp); 289 } 290 291 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 292 { 293 /* disable IRQ sources */ 294 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 295 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 296 297 /* 298 * In synchronous mode stop the TX clocks if no other stream is 299 * running 300 */ 301 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 302 mcasp_set_clk_pdir(mcasp, false); 303 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 304 } 305 306 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 307 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 308 309 if (mcasp->rxnumevt) { /* disable FIFO */ 310 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 311 312 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 313 } 314 } 315 316 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 317 { 318 u32 val = 0; 319 320 /* disable IRQ sources */ 321 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 322 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 323 324 /* 325 * In synchronous mode keep TX clocks running if the capture stream is 326 * still running. 327 */ 328 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 329 val = TXHCLKRST | TXCLKRST | TXFSRST; 330 else 331 mcasp_set_clk_pdir(mcasp, false); 332 333 334 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 335 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 336 337 if (mcasp->txnumevt) { /* disable FIFO */ 338 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 339 340 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 341 } 342 343 mcasp_set_axr_pdir(mcasp, false); 344 } 345 346 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 347 { 348 mcasp->streams--; 349 350 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 351 mcasp_stop_tx(mcasp); 352 else 353 mcasp_stop_rx(mcasp); 354 } 355 356 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 357 { 358 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 359 struct snd_pcm_substream *substream; 360 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 361 u32 handled_mask = 0; 362 u32 stat; 363 364 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 365 if (stat & XUNDRN & irq_mask) { 366 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 367 handled_mask |= XUNDRN; 368 369 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 370 if (substream) 371 snd_pcm_stop_xrun(substream); 372 } 373 374 if (!handled_mask) 375 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 376 stat); 377 378 if (stat & XRERR) 379 handled_mask |= XRERR; 380 381 /* Ack the handled event only */ 382 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 383 384 return IRQ_RETVAL(handled_mask); 385 } 386 387 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 388 { 389 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 390 struct snd_pcm_substream *substream; 391 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 392 u32 handled_mask = 0; 393 u32 stat; 394 395 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 396 if (stat & ROVRN & irq_mask) { 397 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 398 handled_mask |= ROVRN; 399 400 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 401 if (substream) 402 snd_pcm_stop_xrun(substream); 403 } 404 405 if (!handled_mask) 406 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 407 stat); 408 409 if (stat & XRERR) 410 handled_mask |= XRERR; 411 412 /* Ack the handled event only */ 413 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 414 415 return IRQ_RETVAL(handled_mask); 416 } 417 418 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 419 { 420 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 421 irqreturn_t ret = IRQ_NONE; 422 423 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 424 ret = davinci_mcasp_tx_irq_handler(irq, data); 425 426 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 427 ret |= davinci_mcasp_rx_irq_handler(irq, data); 428 429 return ret; 430 } 431 432 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 433 unsigned int fmt) 434 { 435 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 436 int ret = 0; 437 u32 data_delay; 438 bool fs_pol_rising; 439 bool inv_fs = false; 440 441 if (!fmt) 442 return 0; 443 444 pm_runtime_get_sync(mcasp->dev); 445 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 446 case SND_SOC_DAIFMT_DSP_A: 447 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 449 /* 1st data bit occur one ACLK cycle after the frame sync */ 450 data_delay = 1; 451 break; 452 case SND_SOC_DAIFMT_DSP_B: 453 case SND_SOC_DAIFMT_AC97: 454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 456 /* No delay after FS */ 457 data_delay = 0; 458 break; 459 case SND_SOC_DAIFMT_I2S: 460 /* configure a full-word SYNC pulse (LRCLK) */ 461 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 462 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 463 /* 1st data bit occur one ACLK cycle after the frame sync */ 464 data_delay = 1; 465 /* FS need to be inverted */ 466 inv_fs = true; 467 break; 468 case SND_SOC_DAIFMT_LEFT_J: 469 /* configure a full-word SYNC pulse (LRCLK) */ 470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 472 /* No delay after FS */ 473 data_delay = 0; 474 break; 475 default: 476 ret = -EINVAL; 477 goto out; 478 } 479 480 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 481 FSXDLY(3)); 482 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 483 FSRDLY(3)); 484 485 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 486 case SND_SOC_DAIFMT_CBS_CFS: 487 /* codec is clock and frame slave */ 488 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 489 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 490 491 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 492 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 493 494 /* BCLK */ 495 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 496 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 497 /* Frame Sync */ 498 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 499 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 500 501 mcasp->bclk_master = 1; 502 break; 503 case SND_SOC_DAIFMT_CBS_CFM: 504 /* codec is clock slave and frame master */ 505 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 507 508 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 509 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 510 511 /* BCLK */ 512 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 513 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 514 /* Frame Sync */ 515 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 516 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 517 518 mcasp->bclk_master = 1; 519 break; 520 case SND_SOC_DAIFMT_CBM_CFS: 521 /* codec is clock master and frame slave */ 522 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 523 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 524 525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 526 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 527 528 /* BCLK */ 529 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 530 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 531 /* Frame Sync */ 532 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 533 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 534 535 mcasp->bclk_master = 0; 536 break; 537 case SND_SOC_DAIFMT_CBM_CFM: 538 /* codec is clock and frame master */ 539 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 540 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 541 542 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 543 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 544 545 /* BCLK */ 546 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 547 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 548 /* Frame Sync */ 549 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 550 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 551 552 mcasp->bclk_master = 0; 553 break; 554 default: 555 ret = -EINVAL; 556 goto out; 557 } 558 559 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 560 case SND_SOC_DAIFMT_IB_NF: 561 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 562 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 563 fs_pol_rising = true; 564 break; 565 case SND_SOC_DAIFMT_NB_IF: 566 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 567 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 568 fs_pol_rising = false; 569 break; 570 case SND_SOC_DAIFMT_IB_IF: 571 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 572 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 573 fs_pol_rising = false; 574 break; 575 case SND_SOC_DAIFMT_NB_NF: 576 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 577 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 578 fs_pol_rising = true; 579 break; 580 default: 581 ret = -EINVAL; 582 goto out; 583 } 584 585 if (inv_fs) 586 fs_pol_rising = !fs_pol_rising; 587 588 if (fs_pol_rising) { 589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 591 } else { 592 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 593 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 594 } 595 596 mcasp->dai_fmt = fmt; 597 out: 598 pm_runtime_put(mcasp->dev); 599 return ret; 600 } 601 602 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 603 int div, bool explicit) 604 { 605 pm_runtime_get_sync(mcasp->dev); 606 switch (div_id) { 607 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 608 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 609 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 610 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 611 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 612 break; 613 614 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 616 ACLKXDIV(div - 1), ACLKXDIV_MASK); 617 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 618 ACLKRDIV(div - 1), ACLKRDIV_MASK); 619 if (explicit) 620 mcasp->bclk_div = div; 621 break; 622 623 case MCASP_CLKDIV_BCLK_FS_RATIO: 624 /* 625 * BCLK/LRCLK ratio descries how many bit-clock cycles 626 * fit into one frame. The clock ratio is given for a 627 * full period of data (for I2S format both left and 628 * right channels), so it has to be divided by number 629 * of tdm-slots (for I2S - divided by 2). 630 * Instead of storing this ratio, we calculate a new 631 * tdm_slot width by dividing the the ratio by the 632 * number of configured tdm slots. 633 */ 634 mcasp->slot_width = div / mcasp->tdm_slots; 635 if (div % mcasp->tdm_slots) 636 dev_warn(mcasp->dev, 637 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 638 __func__, div, mcasp->tdm_slots); 639 break; 640 641 default: 642 return -EINVAL; 643 } 644 645 pm_runtime_put(mcasp->dev); 646 return 0; 647 } 648 649 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 650 int div) 651 { 652 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 653 654 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 655 } 656 657 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 658 unsigned int freq, int dir) 659 { 660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 661 662 pm_runtime_get_sync(mcasp->dev); 663 if (dir == SND_SOC_CLOCK_OUT) { 664 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 665 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 666 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 667 } else { 668 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 669 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 670 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 671 } 672 673 mcasp->sysclk_freq = freq; 674 675 pm_runtime_put(mcasp->dev); 676 return 0; 677 } 678 679 /* All serializers must have equal number of channels */ 680 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 681 int serializers) 682 { 683 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 684 unsigned int *list = (unsigned int *) cl->list; 685 int slots = mcasp->tdm_slots; 686 int i, count = 0; 687 688 if (mcasp->tdm_mask[stream]) 689 slots = hweight32(mcasp->tdm_mask[stream]); 690 691 for (i = 1; i <= slots; i++) 692 list[count++] = i; 693 694 for (i = 2; i <= serializers; i++) 695 list[count++] = i*slots; 696 697 cl->count = count; 698 699 return 0; 700 } 701 702 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 703 { 704 int rx_serializers = 0, tx_serializers = 0, ret, i; 705 706 for (i = 0; i < mcasp->num_serializer; i++) 707 if (mcasp->serial_dir[i] == TX_MODE) 708 tx_serializers++; 709 else if (mcasp->serial_dir[i] == RX_MODE) 710 rx_serializers++; 711 712 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 713 tx_serializers); 714 if (ret) 715 return ret; 716 717 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 718 rx_serializers); 719 720 return ret; 721 } 722 723 724 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 725 unsigned int tx_mask, 726 unsigned int rx_mask, 727 int slots, int slot_width) 728 { 729 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 730 731 dev_dbg(mcasp->dev, 732 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 733 __func__, tx_mask, rx_mask, slots, slot_width); 734 735 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 736 dev_err(mcasp->dev, 737 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 738 tx_mask, rx_mask, slots); 739 return -EINVAL; 740 } 741 742 if (slot_width && 743 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 744 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 745 __func__, slot_width); 746 return -EINVAL; 747 } 748 749 mcasp->tdm_slots = slots; 750 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 751 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 752 mcasp->slot_width = slot_width; 753 754 return davinci_mcasp_set_ch_constraints(mcasp); 755 } 756 757 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 758 int sample_width) 759 { 760 u32 fmt; 761 u32 tx_rotate = (sample_width / 4) & 0x7; 762 u32 mask = (1ULL << sample_width) - 1; 763 u32 slot_width = sample_width; 764 765 /* 766 * For captured data we should not rotate, inversion and masking is 767 * enoguh to get the data to the right position: 768 * Format data from bus after reverse (XRBUF) 769 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| 770 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 771 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 772 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| 773 */ 774 u32 rx_rotate = 0; 775 776 /* 777 * Setting the tdm slot width either with set_clkdiv() or 778 * set_tdm_slot() allows us to for example send 32 bits per 779 * channel to the codec, while only 16 of them carry audio 780 * payload. 781 */ 782 if (mcasp->slot_width) { 783 /* 784 * When we have more bclk then it is needed for the 785 * data, we need to use the rotation to move the 786 * received samples to have correct alignment. 787 */ 788 slot_width = mcasp->slot_width; 789 rx_rotate = (slot_width - sample_width) / 4; 790 } 791 792 /* mapping of the XSSZ bit-field as described in the datasheet */ 793 fmt = (slot_width >> 1) - 1; 794 795 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 796 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 797 RXSSZ(0x0F)); 798 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 799 TXSSZ(0x0F)); 800 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 801 TXROT(7)); 802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 803 RXROT(7)); 804 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 805 } 806 807 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 808 809 return 0; 810 } 811 812 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 813 int period_words, int channels) 814 { 815 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 816 int i; 817 u8 tx_ser = 0; 818 u8 rx_ser = 0; 819 u8 slots = mcasp->tdm_slots; 820 u8 max_active_serializers = (channels + slots - 1) / slots; 821 int active_serializers, numevt; 822 u32 reg; 823 /* Default configuration */ 824 if (mcasp->version < MCASP_VERSION_3) 825 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 826 827 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 828 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 830 } else { 831 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 832 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 833 } 834 835 for (i = 0; i < mcasp->num_serializer; i++) { 836 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 837 mcasp->serial_dir[i]); 838 if (mcasp->serial_dir[i] == TX_MODE && 839 tx_ser < max_active_serializers) { 840 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 841 mcasp->dismod, DISMOD_MASK); 842 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 843 tx_ser++; 844 } else if (mcasp->serial_dir[i] == RX_MODE && 845 rx_ser < max_active_serializers) { 846 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 847 rx_ser++; 848 } else { 849 /* Inactive or unused pin, set it to inactive */ 850 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 851 SRMOD_INACTIVE, SRMOD_MASK); 852 /* If unused, set DISMOD for the pin */ 853 if (mcasp->serial_dir[i] != INACTIVE_MODE) 854 mcasp_mod_bits(mcasp, 855 DAVINCI_MCASP_XRSRCTL_REG(i), 856 mcasp->dismod, DISMOD_MASK); 857 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 858 } 859 } 860 861 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 862 active_serializers = tx_ser; 863 numevt = mcasp->txnumevt; 864 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 865 } else { 866 active_serializers = rx_ser; 867 numevt = mcasp->rxnumevt; 868 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 869 } 870 871 if (active_serializers < max_active_serializers) { 872 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 873 "enabled in mcasp (%d)\n", channels, 874 active_serializers * slots); 875 return -EINVAL; 876 } 877 878 /* AFIFO is not in use */ 879 if (!numevt) { 880 /* Configure the burst size for platform drivers */ 881 if (active_serializers > 1) { 882 /* 883 * If more than one serializers are in use we have one 884 * DMA request to provide data for all serializers. 885 * For example if three serializers are enabled the DMA 886 * need to transfer three words per DMA request. 887 */ 888 dma_data->maxburst = active_serializers; 889 } else { 890 dma_data->maxburst = 0; 891 } 892 return 0; 893 } 894 895 if (period_words % active_serializers) { 896 dev_err(mcasp->dev, "Invalid combination of period words and " 897 "active serializers: %d, %d\n", period_words, 898 active_serializers); 899 return -EINVAL; 900 } 901 902 /* 903 * Calculate the optimal AFIFO depth for platform side: 904 * The number of words for numevt need to be in steps of active 905 * serializers. 906 */ 907 numevt = (numevt / active_serializers) * active_serializers; 908 909 while (period_words % numevt && numevt > 0) 910 numevt -= active_serializers; 911 if (numevt <= 0) 912 numevt = active_serializers; 913 914 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 915 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 916 917 /* Configure the burst size for platform drivers */ 918 if (numevt == 1) 919 numevt = 0; 920 dma_data->maxburst = numevt; 921 922 return 0; 923 } 924 925 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 926 int channels) 927 { 928 int i, active_slots; 929 int total_slots; 930 int active_serializers; 931 u32 mask = 0; 932 u32 busel = 0; 933 934 total_slots = mcasp->tdm_slots; 935 936 /* 937 * If more than one serializer is needed, then use them with 938 * all the specified tdm_slots. Otherwise, one serializer can 939 * cope with the transaction using just as many slots as there 940 * are channels in the stream. 941 */ 942 if (mcasp->tdm_mask[stream]) { 943 active_slots = hweight32(mcasp->tdm_mask[stream]); 944 active_serializers = (channels + active_slots - 1) / 945 active_slots; 946 if (active_serializers == 1) 947 active_slots = channels; 948 for (i = 0; i < total_slots; i++) { 949 if ((1 << i) & mcasp->tdm_mask[stream]) { 950 mask |= (1 << i); 951 if (--active_slots <= 0) 952 break; 953 } 954 } 955 } else { 956 active_serializers = (channels + total_slots - 1) / total_slots; 957 if (active_serializers == 1) 958 active_slots = channels; 959 else 960 active_slots = total_slots; 961 962 for (i = 0; i < active_slots; i++) 963 mask |= (1 << i); 964 } 965 966 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 967 968 if (!mcasp->dat_port) 969 busel = TXSEL; 970 971 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 972 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 973 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 974 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 975 FSXMOD(total_slots), FSXMOD(0x1FF)); 976 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 977 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 978 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 979 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 980 FSRMOD(total_slots), FSRMOD(0x1FF)); 981 /* 982 * If McASP is set to be TX/RX synchronous and the playback is 983 * not running already we need to configure the TX slots in 984 * order to have correct FSX on the bus 985 */ 986 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 987 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 988 FSXMOD(total_slots), FSXMOD(0x1FF)); 989 } 990 991 return 0; 992 } 993 994 /* S/PDIF */ 995 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 996 unsigned int rate) 997 { 998 u32 cs_value = 0; 999 u8 *cs_bytes = (u8*) &cs_value; 1000 1001 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 1002 and LSB first */ 1003 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); 1004 1005 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1006 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1007 1008 /* Set the TX tdm : for all the slots */ 1009 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1010 1011 /* Set the TX clock controls : div = 1 and internal */ 1012 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1013 1014 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1015 1016 /* Only 44100 and 48000 are valid, both have the same setting */ 1017 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 1018 1019 /* Enable the DIT */ 1020 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1021 1022 /* Set S/PDIF channel status bits */ 1023 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 1024 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; 1025 1026 switch (rate) { 1027 case 22050: 1028 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1029 break; 1030 case 24000: 1031 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1032 break; 1033 case 32000: 1034 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1035 break; 1036 case 44100: 1037 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1038 break; 1039 case 48000: 1040 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1041 break; 1042 case 88200: 1043 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1044 break; 1045 case 96000: 1046 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1047 break; 1048 case 176400: 1049 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1050 break; 1051 case 192000: 1052 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1053 break; 1054 default: 1055 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); 1056 return -EINVAL; 1057 } 1058 1059 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); 1060 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); 1061 1062 return 0; 1063 } 1064 1065 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1066 unsigned int sysclk_freq, 1067 unsigned int bclk_freq, bool set) 1068 { 1069 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1070 int div = sysclk_freq / bclk_freq; 1071 int rem = sysclk_freq % bclk_freq; 1072 int error_ppm; 1073 int aux_div = 1; 1074 1075 if (div > (ACLKXDIV_MASK + 1)) { 1076 if (reg & AHCLKXE) { 1077 aux_div = div / (ACLKXDIV_MASK + 1); 1078 if (div % (ACLKXDIV_MASK + 1)) 1079 aux_div++; 1080 1081 sysclk_freq /= aux_div; 1082 div = sysclk_freq / bclk_freq; 1083 rem = sysclk_freq % bclk_freq; 1084 } else if (set) { 1085 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1086 sysclk_freq); 1087 } 1088 } 1089 1090 if (rem != 0) { 1091 if (div == 0 || 1092 ((sysclk_freq / div) - bclk_freq) > 1093 (bclk_freq - (sysclk_freq / (div+1)))) { 1094 div++; 1095 rem = rem - bclk_freq; 1096 } 1097 } 1098 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1099 (int)bclk_freq)) / div - 1000000; 1100 1101 if (set) { 1102 if (error_ppm) 1103 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1104 error_ppm); 1105 1106 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1107 if (reg & AHCLKXE) 1108 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1109 aux_div, 0); 1110 } 1111 1112 return error_ppm; 1113 } 1114 1115 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1116 { 1117 if (!mcasp->txnumevt) 1118 return 0; 1119 1120 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1121 } 1122 1123 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1124 { 1125 if (!mcasp->rxnumevt) 1126 return 0; 1127 1128 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1129 } 1130 1131 static snd_pcm_sframes_t davinci_mcasp_delay( 1132 struct snd_pcm_substream *substream, 1133 struct snd_soc_dai *cpu_dai) 1134 { 1135 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1136 u32 fifo_use; 1137 1138 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1139 fifo_use = davinci_mcasp_tx_delay(mcasp); 1140 else 1141 fifo_use = davinci_mcasp_rx_delay(mcasp); 1142 1143 /* 1144 * Divide the used locations with the channel count to get the 1145 * FIFO usage in samples (don't care about partial samples in the 1146 * buffer). 1147 */ 1148 return fifo_use / substream->runtime->channels; 1149 } 1150 1151 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1152 struct snd_pcm_hw_params *params, 1153 struct snd_soc_dai *cpu_dai) 1154 { 1155 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1156 int word_length; 1157 int channels = params_channels(params); 1158 int period_size = params_period_size(params); 1159 int ret; 1160 1161 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1162 if (ret) 1163 return ret; 1164 1165 /* 1166 * If mcasp is BCLK master, and a BCLK divider was not provided by 1167 * the machine driver, we need to calculate the ratio. 1168 */ 1169 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1170 int slots = mcasp->tdm_slots; 1171 int rate = params_rate(params); 1172 int sbits = params_width(params); 1173 1174 if (mcasp->slot_width) 1175 sbits = mcasp->slot_width; 1176 1177 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq, 1178 rate * sbits * slots, true); 1179 } 1180 1181 ret = mcasp_common_hw_param(mcasp, substream->stream, 1182 period_size * channels, channels); 1183 if (ret) 1184 return ret; 1185 1186 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1187 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1188 else 1189 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1190 channels); 1191 1192 if (ret) 1193 return ret; 1194 1195 switch (params_format(params)) { 1196 case SNDRV_PCM_FORMAT_U8: 1197 case SNDRV_PCM_FORMAT_S8: 1198 word_length = 8; 1199 break; 1200 1201 case SNDRV_PCM_FORMAT_U16_LE: 1202 case SNDRV_PCM_FORMAT_S16_LE: 1203 word_length = 16; 1204 break; 1205 1206 case SNDRV_PCM_FORMAT_U24_3LE: 1207 case SNDRV_PCM_FORMAT_S24_3LE: 1208 word_length = 24; 1209 break; 1210 1211 case SNDRV_PCM_FORMAT_U24_LE: 1212 case SNDRV_PCM_FORMAT_S24_LE: 1213 word_length = 24; 1214 break; 1215 1216 case SNDRV_PCM_FORMAT_U32_LE: 1217 case SNDRV_PCM_FORMAT_S32_LE: 1218 word_length = 32; 1219 break; 1220 1221 default: 1222 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1223 return -EINVAL; 1224 } 1225 1226 davinci_config_channel_size(mcasp, word_length); 1227 1228 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1229 mcasp->channels = channels; 1230 1231 return 0; 1232 } 1233 1234 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1235 int cmd, struct snd_soc_dai *cpu_dai) 1236 { 1237 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1238 int ret = 0; 1239 1240 switch (cmd) { 1241 case SNDRV_PCM_TRIGGER_RESUME: 1242 case SNDRV_PCM_TRIGGER_START: 1243 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1244 davinci_mcasp_start(mcasp, substream->stream); 1245 break; 1246 case SNDRV_PCM_TRIGGER_SUSPEND: 1247 case SNDRV_PCM_TRIGGER_STOP: 1248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1249 davinci_mcasp_stop(mcasp, substream->stream); 1250 break; 1251 1252 default: 1253 ret = -EINVAL; 1254 } 1255 1256 return ret; 1257 } 1258 1259 static const unsigned int davinci_mcasp_dai_rates[] = { 1260 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1261 88200, 96000, 176400, 192000, 1262 }; 1263 1264 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1265 1266 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1267 struct snd_pcm_hw_rule *rule) 1268 { 1269 struct davinci_mcasp_ruledata *rd = rule->private; 1270 struct snd_interval *ri = 1271 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1272 int sbits = params_width(params); 1273 int slots = rd->mcasp->tdm_slots; 1274 struct snd_interval range; 1275 int i; 1276 1277 if (rd->mcasp->slot_width) 1278 sbits = rd->mcasp->slot_width; 1279 1280 snd_interval_any(&range); 1281 range.empty = 1; 1282 1283 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1284 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1285 uint bclk_freq = sbits * slots * 1286 davinci_mcasp_dai_rates[i]; 1287 unsigned int sysclk_freq; 1288 int ppm; 1289 1290 if (rd->mcasp->auxclk_fs_ratio) 1291 sysclk_freq = davinci_mcasp_dai_rates[i] * 1292 rd->mcasp->auxclk_fs_ratio; 1293 else 1294 sysclk_freq = rd->mcasp->sysclk_freq; 1295 1296 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1297 bclk_freq, false); 1298 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1299 if (range.empty) { 1300 range.min = davinci_mcasp_dai_rates[i]; 1301 range.empty = 0; 1302 } 1303 range.max = davinci_mcasp_dai_rates[i]; 1304 } 1305 } 1306 } 1307 1308 dev_dbg(rd->mcasp->dev, 1309 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1310 ri->min, ri->max, range.min, range.max, sbits, slots); 1311 1312 return snd_interval_refine(hw_param_interval(params, rule->var), 1313 &range); 1314 } 1315 1316 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1317 struct snd_pcm_hw_rule *rule) 1318 { 1319 struct davinci_mcasp_ruledata *rd = rule->private; 1320 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1321 struct snd_mask nfmt; 1322 int rate = params_rate(params); 1323 int slots = rd->mcasp->tdm_slots; 1324 int i, count = 0; 1325 1326 snd_mask_none(&nfmt); 1327 1328 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1329 if (snd_mask_test(fmt, i)) { 1330 uint sbits = snd_pcm_format_width(i); 1331 unsigned int sysclk_freq; 1332 int ppm; 1333 1334 if (rd->mcasp->auxclk_fs_ratio) 1335 sysclk_freq = rate * 1336 rd->mcasp->auxclk_fs_ratio; 1337 else 1338 sysclk_freq = rd->mcasp->sysclk_freq; 1339 1340 if (rd->mcasp->slot_width) 1341 sbits = rd->mcasp->slot_width; 1342 1343 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1344 sbits * slots * rate, 1345 false); 1346 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1347 snd_mask_set(&nfmt, i); 1348 count++; 1349 } 1350 } 1351 } 1352 dev_dbg(rd->mcasp->dev, 1353 "%d possible sample format for %d Hz and %d tdm slots\n", 1354 count, rate, slots); 1355 1356 return snd_mask_refine(fmt, &nfmt); 1357 } 1358 1359 static int davinci_mcasp_hw_rule_min_periodsize( 1360 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1361 { 1362 struct snd_interval *period_size = hw_param_interval(params, 1363 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1364 struct snd_interval frames; 1365 1366 snd_interval_any(&frames); 1367 frames.min = 64; 1368 frames.integer = 1; 1369 1370 return snd_interval_refine(period_size, &frames); 1371 } 1372 1373 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1374 struct snd_soc_dai *cpu_dai) 1375 { 1376 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1377 struct davinci_mcasp_ruledata *ruledata = 1378 &mcasp->ruledata[substream->stream]; 1379 u32 max_channels = 0; 1380 int i, dir; 1381 int tdm_slots = mcasp->tdm_slots; 1382 1383 /* Do not allow more then one stream per direction */ 1384 if (mcasp->substreams[substream->stream]) 1385 return -EBUSY; 1386 1387 mcasp->substreams[substream->stream] = substream; 1388 1389 if (mcasp->tdm_mask[substream->stream]) 1390 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1391 1392 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1393 return 0; 1394 1395 /* 1396 * Limit the maximum allowed channels for the first stream: 1397 * number of serializers for the direction * tdm slots per serializer 1398 */ 1399 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1400 dir = TX_MODE; 1401 else 1402 dir = RX_MODE; 1403 1404 for (i = 0; i < mcasp->num_serializer; i++) { 1405 if (mcasp->serial_dir[i] == dir) 1406 max_channels++; 1407 } 1408 ruledata->serializers = max_channels; 1409 max_channels *= tdm_slots; 1410 /* 1411 * If the already active stream has less channels than the calculated 1412 * limnit based on the seirializers * tdm_slots, we need to use that as 1413 * a constraint for the second stream. 1414 * Otherwise (first stream or less allowed channels) we use the 1415 * calculated constraint. 1416 */ 1417 if (mcasp->channels && mcasp->channels < max_channels) 1418 max_channels = mcasp->channels; 1419 /* 1420 * But we can always allow channels upto the amount of 1421 * the available tdm_slots. 1422 */ 1423 if (max_channels < tdm_slots) 1424 max_channels = tdm_slots; 1425 1426 snd_pcm_hw_constraint_minmax(substream->runtime, 1427 SNDRV_PCM_HW_PARAM_CHANNELS, 1428 0, max_channels); 1429 1430 snd_pcm_hw_constraint_list(substream->runtime, 1431 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1432 &mcasp->chconstr[substream->stream]); 1433 1434 if (mcasp->slot_width) 1435 snd_pcm_hw_constraint_minmax(substream->runtime, 1436 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1437 8, mcasp->slot_width); 1438 1439 /* 1440 * If we rely on implicit BCLK divider setting we should 1441 * set constraints based on what we can provide. 1442 */ 1443 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1444 int ret; 1445 1446 ruledata->mcasp = mcasp; 1447 1448 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1449 SNDRV_PCM_HW_PARAM_RATE, 1450 davinci_mcasp_hw_rule_rate, 1451 ruledata, 1452 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1453 if (ret) 1454 return ret; 1455 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1456 SNDRV_PCM_HW_PARAM_FORMAT, 1457 davinci_mcasp_hw_rule_format, 1458 ruledata, 1459 SNDRV_PCM_HW_PARAM_RATE, -1); 1460 if (ret) 1461 return ret; 1462 } 1463 1464 snd_pcm_hw_rule_add(substream->runtime, 0, 1465 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1466 davinci_mcasp_hw_rule_min_periodsize, NULL, 1467 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1468 1469 return 0; 1470 } 1471 1472 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1473 struct snd_soc_dai *cpu_dai) 1474 { 1475 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1476 1477 mcasp->substreams[substream->stream] = NULL; 1478 1479 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1480 return; 1481 1482 if (!cpu_dai->active) 1483 mcasp->channels = 0; 1484 } 1485 1486 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1487 .startup = davinci_mcasp_startup, 1488 .shutdown = davinci_mcasp_shutdown, 1489 .trigger = davinci_mcasp_trigger, 1490 .delay = davinci_mcasp_delay, 1491 .hw_params = davinci_mcasp_hw_params, 1492 .set_fmt = davinci_mcasp_set_dai_fmt, 1493 .set_clkdiv = davinci_mcasp_set_clkdiv, 1494 .set_sysclk = davinci_mcasp_set_sysclk, 1495 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1496 }; 1497 1498 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1499 { 1500 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1501 1502 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1503 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 1504 1505 return 0; 1506 } 1507 1508 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1509 1510 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1511 SNDRV_PCM_FMTBIT_U8 | \ 1512 SNDRV_PCM_FMTBIT_S16_LE | \ 1513 SNDRV_PCM_FMTBIT_U16_LE | \ 1514 SNDRV_PCM_FMTBIT_S24_LE | \ 1515 SNDRV_PCM_FMTBIT_U24_LE | \ 1516 SNDRV_PCM_FMTBIT_S24_3LE | \ 1517 SNDRV_PCM_FMTBIT_U24_3LE | \ 1518 SNDRV_PCM_FMTBIT_S32_LE | \ 1519 SNDRV_PCM_FMTBIT_U32_LE) 1520 1521 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1522 { 1523 .name = "davinci-mcasp.0", 1524 .probe = davinci_mcasp_dai_probe, 1525 .playback = { 1526 .channels_min = 1, 1527 .channels_max = 32 * 16, 1528 .rates = DAVINCI_MCASP_RATES, 1529 .formats = DAVINCI_MCASP_PCM_FMTS, 1530 }, 1531 .capture = { 1532 .channels_min = 1, 1533 .channels_max = 32 * 16, 1534 .rates = DAVINCI_MCASP_RATES, 1535 .formats = DAVINCI_MCASP_PCM_FMTS, 1536 }, 1537 .ops = &davinci_mcasp_dai_ops, 1538 1539 .symmetric_samplebits = 1, 1540 .symmetric_rates = 1, 1541 }, 1542 { 1543 .name = "davinci-mcasp.1", 1544 .probe = davinci_mcasp_dai_probe, 1545 .playback = { 1546 .channels_min = 1, 1547 .channels_max = 384, 1548 .rates = DAVINCI_MCASP_RATES, 1549 .formats = DAVINCI_MCASP_PCM_FMTS, 1550 }, 1551 .ops = &davinci_mcasp_dai_ops, 1552 }, 1553 1554 }; 1555 1556 static const struct snd_soc_component_driver davinci_mcasp_component = { 1557 .name = "davinci-mcasp", 1558 }; 1559 1560 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1561 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1562 .tx_dma_offset = 0x400, 1563 .rx_dma_offset = 0x400, 1564 .version = MCASP_VERSION_1, 1565 }; 1566 1567 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1568 .tx_dma_offset = 0x2000, 1569 .rx_dma_offset = 0x2000, 1570 .version = MCASP_VERSION_2, 1571 }; 1572 1573 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1574 .tx_dma_offset = 0, 1575 .rx_dma_offset = 0, 1576 .version = MCASP_VERSION_3, 1577 }; 1578 1579 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1580 /* The CFG port offset will be calculated if it is needed */ 1581 .tx_dma_offset = 0, 1582 .rx_dma_offset = 0, 1583 .version = MCASP_VERSION_4, 1584 }; 1585 1586 static const struct of_device_id mcasp_dt_ids[] = { 1587 { 1588 .compatible = "ti,dm646x-mcasp-audio", 1589 .data = &dm646x_mcasp_pdata, 1590 }, 1591 { 1592 .compatible = "ti,da830-mcasp-audio", 1593 .data = &da830_mcasp_pdata, 1594 }, 1595 { 1596 .compatible = "ti,am33xx-mcasp-audio", 1597 .data = &am33xx_mcasp_pdata, 1598 }, 1599 { 1600 .compatible = "ti,dra7-mcasp-audio", 1601 .data = &dra7_mcasp_pdata, 1602 }, 1603 { /* sentinel */ } 1604 }; 1605 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1606 1607 static int mcasp_reparent_fck(struct platform_device *pdev) 1608 { 1609 struct device_node *node = pdev->dev.of_node; 1610 struct clk *gfclk, *parent_clk; 1611 const char *parent_name; 1612 int ret; 1613 1614 if (!node) 1615 return 0; 1616 1617 parent_name = of_get_property(node, "fck_parent", NULL); 1618 if (!parent_name) 1619 return 0; 1620 1621 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1622 1623 gfclk = clk_get(&pdev->dev, "fck"); 1624 if (IS_ERR(gfclk)) { 1625 dev_err(&pdev->dev, "failed to get fck\n"); 1626 return PTR_ERR(gfclk); 1627 } 1628 1629 parent_clk = clk_get(NULL, parent_name); 1630 if (IS_ERR(parent_clk)) { 1631 dev_err(&pdev->dev, "failed to get parent clock\n"); 1632 ret = PTR_ERR(parent_clk); 1633 goto err1; 1634 } 1635 1636 ret = clk_set_parent(gfclk, parent_clk); 1637 if (ret) { 1638 dev_err(&pdev->dev, "failed to reparent fck\n"); 1639 goto err2; 1640 } 1641 1642 err2: 1643 clk_put(parent_clk); 1644 err1: 1645 clk_put(gfclk); 1646 return ret; 1647 } 1648 1649 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( 1650 struct platform_device *pdev) 1651 { 1652 struct device_node *np = pdev->dev.of_node; 1653 struct davinci_mcasp_pdata *pdata = NULL; 1654 const struct of_device_id *match = 1655 of_match_device(mcasp_dt_ids, &pdev->dev); 1656 struct of_phandle_args dma_spec; 1657 1658 const u32 *of_serial_dir32; 1659 u32 val; 1660 int i, ret = 0; 1661 1662 if (pdev->dev.platform_data) { 1663 pdata = pdev->dev.platform_data; 1664 pdata->dismod = DISMOD_LOW; 1665 return pdata; 1666 } else if (match) { 1667 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), 1668 GFP_KERNEL); 1669 if (!pdata) { 1670 ret = -ENOMEM; 1671 return pdata; 1672 } 1673 } else { 1674 /* control shouldn't reach here. something is wrong */ 1675 ret = -EINVAL; 1676 goto nodata; 1677 } 1678 1679 ret = of_property_read_u32(np, "op-mode", &val); 1680 if (ret >= 0) 1681 pdata->op_mode = val; 1682 1683 ret = of_property_read_u32(np, "tdm-slots", &val); 1684 if (ret >= 0) { 1685 if (val < 2 || val > 32) { 1686 dev_err(&pdev->dev, 1687 "tdm-slots must be in rage [2-32]\n"); 1688 ret = -EINVAL; 1689 goto nodata; 1690 } 1691 1692 pdata->tdm_slots = val; 1693 } 1694 1695 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1696 val /= sizeof(u32); 1697 if (of_serial_dir32) { 1698 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1699 (sizeof(*of_serial_dir) * val), 1700 GFP_KERNEL); 1701 if (!of_serial_dir) { 1702 ret = -ENOMEM; 1703 goto nodata; 1704 } 1705 1706 for (i = 0; i < val; i++) 1707 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1708 1709 pdata->num_serializer = val; 1710 pdata->serial_dir = of_serial_dir; 1711 } 1712 1713 ret = of_property_match_string(np, "dma-names", "tx"); 1714 if (ret < 0) 1715 goto nodata; 1716 1717 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1718 &dma_spec); 1719 if (ret < 0) 1720 goto nodata; 1721 1722 pdata->tx_dma_channel = dma_spec.args[0]; 1723 1724 /* RX is not valid in DIT mode */ 1725 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { 1726 ret = of_property_match_string(np, "dma-names", "rx"); 1727 if (ret < 0) 1728 goto nodata; 1729 1730 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1731 &dma_spec); 1732 if (ret < 0) 1733 goto nodata; 1734 1735 pdata->rx_dma_channel = dma_spec.args[0]; 1736 } 1737 1738 ret = of_property_read_u32(np, "tx-num-evt", &val); 1739 if (ret >= 0) 1740 pdata->txnumevt = val; 1741 1742 ret = of_property_read_u32(np, "rx-num-evt", &val); 1743 if (ret >= 0) 1744 pdata->rxnumevt = val; 1745 1746 ret = of_property_read_u32(np, "sram-size-playback", &val); 1747 if (ret >= 0) 1748 pdata->sram_size_playback = val; 1749 1750 ret = of_property_read_u32(np, "sram-size-capture", &val); 1751 if (ret >= 0) 1752 pdata->sram_size_capture = val; 1753 1754 ret = of_property_read_u32(np, "dismod", &val); 1755 if (ret >= 0) { 1756 if (val == 0 || val == 2 || val == 3) { 1757 pdata->dismod = DISMOD_VAL(val); 1758 } else { 1759 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1760 pdata->dismod = DISMOD_LOW; 1761 } 1762 } else { 1763 pdata->dismod = DISMOD_LOW; 1764 } 1765 1766 return pdata; 1767 1768 nodata: 1769 if (ret < 0) { 1770 dev_err(&pdev->dev, "Error populating platform data, err %d\n", 1771 ret); 1772 pdata = NULL; 1773 } 1774 return pdata; 1775 } 1776 1777 enum { 1778 PCM_EDMA, 1779 PCM_SDMA, 1780 }; 1781 static const char *sdma_prefix = "ti,omap"; 1782 1783 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 1784 { 1785 struct dma_chan *chan; 1786 const char *tmp; 1787 int ret = PCM_EDMA; 1788 1789 if (!mcasp->dev->of_node) 1790 return PCM_EDMA; 1791 1792 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 1793 chan = dma_request_slave_channel_reason(mcasp->dev, tmp); 1794 if (IS_ERR(chan)) { 1795 if (PTR_ERR(chan) != -EPROBE_DEFER) 1796 dev_err(mcasp->dev, 1797 "Can't verify DMA configuration (%ld)\n", 1798 PTR_ERR(chan)); 1799 return PTR_ERR(chan); 1800 } 1801 if (WARN_ON(!chan->device || !chan->device->dev)) 1802 return -EINVAL; 1803 1804 if (chan->device->dev->of_node) 1805 ret = of_property_read_string(chan->device->dev->of_node, 1806 "compatible", &tmp); 1807 else 1808 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 1809 1810 dma_release_channel(chan); 1811 if (ret) 1812 return ret; 1813 1814 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 1815 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 1816 return PCM_SDMA; 1817 1818 return PCM_EDMA; 1819 } 1820 1821 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 1822 { 1823 int i; 1824 u32 offset = 0; 1825 1826 if (pdata->version != MCASP_VERSION_4) 1827 return pdata->tx_dma_offset; 1828 1829 for (i = 0; i < pdata->num_serializer; i++) { 1830 if (pdata->serial_dir[i] == TX_MODE) { 1831 if (!offset) { 1832 offset = DAVINCI_MCASP_TXBUF_REG(i); 1833 } else { 1834 pr_err("%s: Only one serializer allowed!\n", 1835 __func__); 1836 break; 1837 } 1838 } 1839 } 1840 1841 return offset; 1842 } 1843 1844 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 1845 { 1846 int i; 1847 u32 offset = 0; 1848 1849 if (pdata->version != MCASP_VERSION_4) 1850 return pdata->rx_dma_offset; 1851 1852 for (i = 0; i < pdata->num_serializer; i++) { 1853 if (pdata->serial_dir[i] == RX_MODE) { 1854 if (!offset) { 1855 offset = DAVINCI_MCASP_RXBUF_REG(i); 1856 } else { 1857 pr_err("%s: Only one serializer allowed!\n", 1858 __func__); 1859 break; 1860 } 1861 } 1862 } 1863 1864 return offset; 1865 } 1866 1867 #ifdef CONFIG_GPIOLIB 1868 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 1869 { 1870 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1871 1872 if (mcasp->num_serializer && offset < mcasp->num_serializer && 1873 mcasp->serial_dir[offset] != INACTIVE_MODE) { 1874 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 1875 return -EBUSY; 1876 } 1877 1878 /* Do not change the PIN yet */ 1879 1880 return pm_runtime_get_sync(mcasp->dev); 1881 } 1882 1883 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 1884 { 1885 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1886 1887 /* Set the direction to input */ 1888 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1889 1890 /* Set the pin as McASP pin */ 1891 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1892 1893 pm_runtime_put_sync(mcasp->dev); 1894 } 1895 1896 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 1897 unsigned offset, int value) 1898 { 1899 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1900 u32 val; 1901 1902 if (value) 1903 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1904 else 1905 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1906 1907 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 1908 if (!(val & BIT(offset))) { 1909 /* Set the pin as GPIO pin */ 1910 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1911 1912 /* Set the direction to output */ 1913 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1914 } 1915 1916 return 0; 1917 } 1918 1919 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, 1920 int value) 1921 { 1922 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1923 1924 if (value) 1925 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1926 else 1927 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1928 } 1929 1930 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 1931 unsigned offset) 1932 { 1933 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1934 u32 val; 1935 1936 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 1937 if (!(val & BIT(offset))) { 1938 /* Set the direction to input */ 1939 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1940 1941 /* Set the pin as GPIO pin */ 1942 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1943 } 1944 1945 return 0; 1946 } 1947 1948 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 1949 { 1950 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1951 u32 val; 1952 1953 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 1954 if (val & BIT(offset)) 1955 return 1; 1956 1957 return 0; 1958 } 1959 1960 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 1961 unsigned offset) 1962 { 1963 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1964 u32 val; 1965 1966 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 1967 if (val & BIT(offset)) 1968 return 0; 1969 1970 return 1; 1971 } 1972 1973 static const struct gpio_chip davinci_mcasp_template_chip = { 1974 .owner = THIS_MODULE, 1975 .request = davinci_mcasp_gpio_request, 1976 .free = davinci_mcasp_gpio_free, 1977 .direction_output = davinci_mcasp_gpio_direction_out, 1978 .set = davinci_mcasp_gpio_set, 1979 .direction_input = davinci_mcasp_gpio_direction_in, 1980 .get = davinci_mcasp_gpio_get, 1981 .get_direction = davinci_mcasp_gpio_get_direction, 1982 .base = -1, 1983 .ngpio = 32, 1984 }; 1985 1986 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 1987 { 1988 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) 1989 return 0; 1990 1991 mcasp->gpio_chip = davinci_mcasp_template_chip; 1992 mcasp->gpio_chip.label = dev_name(mcasp->dev); 1993 mcasp->gpio_chip.parent = mcasp->dev; 1994 #ifdef CONFIG_OF_GPIO 1995 mcasp->gpio_chip.of_node = mcasp->dev->of_node; 1996 #endif 1997 1998 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 1999 } 2000 2001 #else /* CONFIG_GPIOLIB */ 2002 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2003 { 2004 return 0; 2005 } 2006 #endif /* CONFIG_GPIOLIB */ 2007 2008 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp) 2009 { 2010 struct device_node *np = mcasp->dev->of_node; 2011 int ret; 2012 u32 val; 2013 2014 if (!np) 2015 return 0; 2016 2017 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val); 2018 if (ret >= 0) 2019 mcasp->auxclk_fs_ratio = val; 2020 2021 return 0; 2022 } 2023 2024 static int davinci_mcasp_probe(struct platform_device *pdev) 2025 { 2026 struct snd_dmaengine_dai_dma_data *dma_data; 2027 struct resource *mem, *res, *dat; 2028 struct davinci_mcasp_pdata *pdata; 2029 struct davinci_mcasp *mcasp; 2030 char *irq_name; 2031 int *dma; 2032 int irq; 2033 int ret; 2034 2035 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2036 dev_err(&pdev->dev, "No platform data supplied\n"); 2037 return -EINVAL; 2038 } 2039 2040 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2041 GFP_KERNEL); 2042 if (!mcasp) 2043 return -ENOMEM; 2044 2045 pdata = davinci_mcasp_set_pdata_from_of(pdev); 2046 if (!pdata) { 2047 dev_err(&pdev->dev, "no platform data\n"); 2048 return -EINVAL; 2049 } 2050 2051 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2052 if (!mem) { 2053 dev_warn(mcasp->dev, 2054 "\"mpu\" mem resource not found, using index 0\n"); 2055 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2056 if (!mem) { 2057 dev_err(&pdev->dev, "no mem resource?\n"); 2058 return -ENODEV; 2059 } 2060 } 2061 2062 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2063 if (IS_ERR(mcasp->base)) 2064 return PTR_ERR(mcasp->base); 2065 2066 pm_runtime_enable(&pdev->dev); 2067 2068 mcasp->op_mode = pdata->op_mode; 2069 /* sanity check for tdm slots parameter */ 2070 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2071 if (pdata->tdm_slots < 2) { 2072 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2073 pdata->tdm_slots); 2074 mcasp->tdm_slots = 2; 2075 } else if (pdata->tdm_slots > 32) { 2076 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2077 pdata->tdm_slots); 2078 mcasp->tdm_slots = 32; 2079 } else { 2080 mcasp->tdm_slots = pdata->tdm_slots; 2081 } 2082 } 2083 2084 mcasp->num_serializer = pdata->num_serializer; 2085 #ifdef CONFIG_PM 2086 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2087 mcasp->num_serializer, sizeof(u32), 2088 GFP_KERNEL); 2089 if (!mcasp->context.xrsr_regs) { 2090 ret = -ENOMEM; 2091 goto err; 2092 } 2093 #endif 2094 mcasp->serial_dir = pdata->serial_dir; 2095 mcasp->version = pdata->version; 2096 mcasp->txnumevt = pdata->txnumevt; 2097 mcasp->rxnumevt = pdata->rxnumevt; 2098 mcasp->dismod = pdata->dismod; 2099 2100 mcasp->dev = &pdev->dev; 2101 2102 irq = platform_get_irq_byname(pdev, "common"); 2103 if (irq >= 0) { 2104 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2105 dev_name(&pdev->dev)); 2106 if (!irq_name) { 2107 ret = -ENOMEM; 2108 goto err; 2109 } 2110 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2111 davinci_mcasp_common_irq_handler, 2112 IRQF_ONESHOT | IRQF_SHARED, 2113 irq_name, mcasp); 2114 if (ret) { 2115 dev_err(&pdev->dev, "common IRQ request failed\n"); 2116 goto err; 2117 } 2118 2119 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2120 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2121 } 2122 2123 irq = platform_get_irq_byname(pdev, "rx"); 2124 if (irq >= 0) { 2125 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2126 dev_name(&pdev->dev)); 2127 if (!irq_name) { 2128 ret = -ENOMEM; 2129 goto err; 2130 } 2131 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2132 davinci_mcasp_rx_irq_handler, 2133 IRQF_ONESHOT, irq_name, mcasp); 2134 if (ret) { 2135 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2136 goto err; 2137 } 2138 2139 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2140 } 2141 2142 irq = platform_get_irq_byname(pdev, "tx"); 2143 if (irq >= 0) { 2144 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2145 dev_name(&pdev->dev)); 2146 if (!irq_name) { 2147 ret = -ENOMEM; 2148 goto err; 2149 } 2150 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2151 davinci_mcasp_tx_irq_handler, 2152 IRQF_ONESHOT, irq_name, mcasp); 2153 if (ret) { 2154 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2155 goto err; 2156 } 2157 2158 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2159 } 2160 2161 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2162 if (dat) 2163 mcasp->dat_port = true; 2164 2165 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2166 if (dat) 2167 dma_data->addr = dat->start; 2168 else 2169 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); 2170 2171 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; 2172 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 2173 if (res) 2174 *dma = res->start; 2175 else 2176 *dma = pdata->tx_dma_channel; 2177 2178 /* dmaengine filter data for DT and non-DT boot */ 2179 if (pdev->dev.of_node) 2180 dma_data->filter_data = "tx"; 2181 else 2182 dma_data->filter_data = dma; 2183 2184 /* RX is not valid in DIT mode */ 2185 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2186 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2187 if (dat) 2188 dma_data->addr = dat->start; 2189 else 2190 dma_data->addr = 2191 mem->start + davinci_mcasp_rxdma_offset(pdata); 2192 2193 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; 2194 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 2195 if (res) 2196 *dma = res->start; 2197 else 2198 *dma = pdata->rx_dma_channel; 2199 2200 /* dmaengine filter data for DT and non-DT boot */ 2201 if (pdev->dev.of_node) 2202 dma_data->filter_data = "rx"; 2203 else 2204 dma_data->filter_data = dma; 2205 } 2206 2207 if (mcasp->version < MCASP_VERSION_3) { 2208 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2209 /* dma_params->dma_addr is pointing to the data port address */ 2210 mcasp->dat_port = true; 2211 } else { 2212 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2213 } 2214 2215 /* Allocate memory for long enough list for all possible 2216 * scenarios. Maximum number tdm slots is 32 and there cannot 2217 * be more serializers than given in the configuration. The 2218 * serializer directions could be taken into account, but it 2219 * would make code much more complex and save only couple of 2220 * bytes. 2221 */ 2222 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2223 devm_kcalloc(mcasp->dev, 2224 32 + mcasp->num_serializer - 1, 2225 sizeof(unsigned int), 2226 GFP_KERNEL); 2227 2228 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2229 devm_kcalloc(mcasp->dev, 2230 32 + mcasp->num_serializer - 1, 2231 sizeof(unsigned int), 2232 GFP_KERNEL); 2233 2234 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2235 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2236 ret = -ENOMEM; 2237 goto err; 2238 } 2239 2240 ret = davinci_mcasp_set_ch_constraints(mcasp); 2241 if (ret) 2242 goto err; 2243 2244 dev_set_drvdata(&pdev->dev, mcasp); 2245 2246 mcasp_reparent_fck(pdev); 2247 2248 /* All PINS as McASP */ 2249 pm_runtime_get_sync(mcasp->dev); 2250 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2251 pm_runtime_put(mcasp->dev); 2252 2253 ret = davinci_mcasp_init_gpiochip(mcasp); 2254 if (ret) 2255 goto err; 2256 2257 ret = davinci_mcasp_get_dt_params(mcasp); 2258 if (ret) 2259 return -EINVAL; 2260 2261 ret = devm_snd_soc_register_component(&pdev->dev, 2262 &davinci_mcasp_component, 2263 &davinci_mcasp_dai[pdata->op_mode], 1); 2264 2265 if (ret != 0) 2266 goto err; 2267 2268 ret = davinci_mcasp_get_dma_type(mcasp); 2269 switch (ret) { 2270 case PCM_EDMA: 2271 ret = edma_pcm_platform_register(&pdev->dev); 2272 break; 2273 case PCM_SDMA: 2274 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2275 break; 2276 default: 2277 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2278 case -EPROBE_DEFER: 2279 goto err; 2280 break; 2281 } 2282 2283 if (ret) { 2284 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2285 goto err; 2286 } 2287 2288 return 0; 2289 2290 err: 2291 pm_runtime_disable(&pdev->dev); 2292 return ret; 2293 } 2294 2295 static int davinci_mcasp_remove(struct platform_device *pdev) 2296 { 2297 pm_runtime_disable(&pdev->dev); 2298 2299 return 0; 2300 } 2301 2302 #ifdef CONFIG_PM 2303 static int davinci_mcasp_runtime_suspend(struct device *dev) 2304 { 2305 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2306 struct davinci_mcasp_context *context = &mcasp->context; 2307 u32 reg; 2308 int i; 2309 2310 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2311 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2312 2313 if (mcasp->txnumevt) { 2314 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2315 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2316 } 2317 if (mcasp->rxnumevt) { 2318 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2319 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2320 } 2321 2322 for (i = 0; i < mcasp->num_serializer; i++) 2323 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2324 DAVINCI_MCASP_XRSRCTL_REG(i)); 2325 2326 return 0; 2327 } 2328 2329 static int davinci_mcasp_runtime_resume(struct device *dev) 2330 { 2331 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2332 struct davinci_mcasp_context *context = &mcasp->context; 2333 u32 reg; 2334 int i; 2335 2336 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2337 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2338 2339 if (mcasp->txnumevt) { 2340 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2341 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2342 } 2343 if (mcasp->rxnumevt) { 2344 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2345 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2346 } 2347 2348 for (i = 0; i < mcasp->num_serializer; i++) 2349 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2350 context->xrsr_regs[i]); 2351 2352 return 0; 2353 } 2354 2355 #endif 2356 2357 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2358 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2359 davinci_mcasp_runtime_resume, 2360 NULL) 2361 }; 2362 2363 static struct platform_driver davinci_mcasp_driver = { 2364 .probe = davinci_mcasp_probe, 2365 .remove = davinci_mcasp_remove, 2366 .driver = { 2367 .name = "davinci-mcasp", 2368 .pm = &davinci_mcasp_pm_ops, 2369 .of_match_table = mcasp_dt_ids, 2370 }, 2371 }; 2372 2373 module_platform_driver(davinci_mcasp_driver); 2374 2375 MODULE_AUTHOR("Steve Chen"); 2376 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2377 MODULE_LICENSE("GPL"); 2378