xref: /openbmc/linux/sound/soc/ti/davinci-i2s.c (revision b8d312aa)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4  *
5  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
6  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7  *
8  * DT support	(c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
9  *		based on davinci-mcasp.c DT support
10  *
11  * TODO:
12  * on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
13  */
14 
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/clk.h>
22 #include <linux/platform_data/davinci_asp.h>
23 
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/initval.h>
28 #include <sound/soc.h>
29 #include <sound/dmaengine_pcm.h>
30 
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
33 
34 #define DRV_NAME "davinci-i2s"
35 
36 /*
37  * NOTE:  terminology here is confusing.
38  *
39  *  - This driver supports the "Audio Serial Port" (ASP),
40  *    found on dm6446, dm355, and other DaVinci chips.
41  *
42  *  - But it labels it a "Multi-channel Buffered Serial Port"
43  *    (McBSP) as on older chips like the dm642 ... which was
44  *    backward-compatible, possibly explaining that confusion.
45  *
46  *  - OMAP chips have a controller called McBSP, which is
47  *    incompatible with the DaVinci flavor of McBSP.
48  *
49  *  - Newer DaVinci chips have a controller called McASP,
50  *    incompatible with ASP and with either McBSP.
51  *
52  * In short:  this uses ASP to implement I2S, not McBSP.
53  * And it won't be the only DaVinci implemention of I2S.
54  */
55 #define DAVINCI_MCBSP_DRR_REG	0x00
56 #define DAVINCI_MCBSP_DXR_REG	0x04
57 #define DAVINCI_MCBSP_SPCR_REG	0x08
58 #define DAVINCI_MCBSP_RCR_REG	0x0c
59 #define DAVINCI_MCBSP_XCR_REG	0x10
60 #define DAVINCI_MCBSP_SRGR_REG	0x14
61 #define DAVINCI_MCBSP_PCR_REG	0x24
62 
63 #define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
64 #define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
65 #define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
66 #define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
67 #define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
68 #define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
69 #define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)
70 
71 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
72 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
73 #define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
74 #define DAVINCI_MCBSP_RCR_RFIG		(1 << 18)
75 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)
76 #define DAVINCI_MCBSP_RCR_RFRLEN2(v)	((v) << 24)
77 #define DAVINCI_MCBSP_RCR_RPHASE	BIT(31)
78 
79 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
80 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
81 #define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
82 #define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
83 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)
84 #define DAVINCI_MCBSP_XCR_XFRLEN2(v)	((v) << 24)
85 #define DAVINCI_MCBSP_XCR_XPHASE	BIT(31)
86 
87 #define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
88 #define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
89 #define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)
90 #define DAVINCI_MCBSP_SRGR_CLKSM	BIT(29)
91 
92 #define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
93 #define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
94 #define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
95 #define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
96 #define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
97 #define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
98 #define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
99 #define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
100 #define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)
101 
102 enum {
103 	DAVINCI_MCBSP_WORD_8 = 0,
104 	DAVINCI_MCBSP_WORD_12,
105 	DAVINCI_MCBSP_WORD_16,
106 	DAVINCI_MCBSP_WORD_20,
107 	DAVINCI_MCBSP_WORD_24,
108 	DAVINCI_MCBSP_WORD_32,
109 };
110 
111 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
112 	[SNDRV_PCM_FORMAT_S8]		= 1,
113 	[SNDRV_PCM_FORMAT_S16_LE]	= 2,
114 	[SNDRV_PCM_FORMAT_S32_LE]	= 4,
115 };
116 
117 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
118 	[SNDRV_PCM_FORMAT_S8]		= DAVINCI_MCBSP_WORD_8,
119 	[SNDRV_PCM_FORMAT_S16_LE]	= DAVINCI_MCBSP_WORD_16,
120 	[SNDRV_PCM_FORMAT_S32_LE]	= DAVINCI_MCBSP_WORD_32,
121 };
122 
123 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
124 	[SNDRV_PCM_FORMAT_S8]		= SNDRV_PCM_FORMAT_S16_LE,
125 	[SNDRV_PCM_FORMAT_S16_LE]	= SNDRV_PCM_FORMAT_S32_LE,
126 };
127 
128 struct davinci_mcbsp_dev {
129 	struct device *dev;
130 	struct snd_dmaengine_dai_dma_data dma_data[2];
131 	int dma_request[2];
132 	void __iomem			*base;
133 #define MOD_DSP_A	0
134 #define MOD_DSP_B	1
135 	int				mode;
136 	u32				pcr;
137 	struct clk			*clk;
138 	/*
139 	 * Combining both channels into 1 element will at least double the
140 	 * amount of time between servicing the dma channel, increase
141 	 * effiency, and reduce the chance of overrun/underrun. But,
142 	 * it will result in the left & right channels being swapped.
143 	 *
144 	 * If relabeling the left and right channels is not possible,
145 	 * you may want to let the codec know to swap them back.
146 	 *
147 	 * It may allow x10 the amount of time to service dma requests,
148 	 * if the codec is master and is using an unnecessarily fast bit clock
149 	 * (ie. tlvaic23b), independent of the sample rate. So, having an
150 	 * entire frame at once means it can be serviced at the sample rate
151 	 * instead of the bit clock rate.
152 	 *
153 	 * In the now unlikely case that an underrun still
154 	 * occurs, both the left and right samples will be repeated
155 	 * so that no pops are heard, and the left and right channels
156 	 * won't end up being swapped because of the underrun.
157 	 */
158 	unsigned enable_channel_combine:1;
159 
160 	unsigned int fmt;
161 	int clk_div;
162 	int clk_input_pin;
163 	bool i2s_accurate_sck;
164 };
165 
166 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
167 					   int reg, u32 val)
168 {
169 	__raw_writel(val, dev->base + reg);
170 }
171 
172 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
173 {
174 	return __raw_readl(dev->base + reg);
175 }
176 
177 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
178 {
179 	u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
180 	/* The clock needs to toggle to complete reset.
181 	 * So, fake it by toggling the clk polarity.
182 	 */
183 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
184 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
185 }
186 
187 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
188 		struct snd_pcm_substream *substream)
189 {
190 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
191 	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
192 	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
193 	u32 spcr;
194 	u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
195 	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
196 	if (spcr & mask) {
197 		/* start off disabled */
198 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
199 				spcr & ~mask);
200 		toggle_clock(dev, playback);
201 	}
202 	if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
203 			DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
204 		/* Start the sample generator */
205 		spcr |= DAVINCI_MCBSP_SPCR_GRST;
206 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
207 	}
208 
209 	if (playback) {
210 		/* Stop the DMA to avoid data loss */
211 		/* while the transmitter is out of reset to handle XSYNCERR */
212 		if (component->driver->ops->trigger) {
213 			int ret = component->driver->ops->trigger(substream,
214 				SNDRV_PCM_TRIGGER_STOP);
215 			if (ret < 0)
216 				printk(KERN_DEBUG "Playback DMA stop failed\n");
217 		}
218 
219 		/* Enable the transmitter */
220 		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
221 		spcr |= DAVINCI_MCBSP_SPCR_XRST;
222 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
223 
224 		/* wait for any unexpected frame sync error to occur */
225 		udelay(100);
226 
227 		/* Disable the transmitter to clear any outstanding XSYNCERR */
228 		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
229 		spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
230 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
231 		toggle_clock(dev, playback);
232 
233 		/* Restart the DMA */
234 		if (component->driver->ops->trigger) {
235 			int ret = component->driver->ops->trigger(substream,
236 				SNDRV_PCM_TRIGGER_START);
237 			if (ret < 0)
238 				printk(KERN_DEBUG "Playback DMA start failed\n");
239 		}
240 	}
241 
242 	/* Enable transmitter or receiver */
243 	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
244 	spcr |= mask;
245 
246 	if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
247 		/* Start frame sync */
248 		spcr |= DAVINCI_MCBSP_SPCR_FRST;
249 	}
250 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
251 }
252 
253 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
254 {
255 	u32 spcr;
256 
257 	/* Reset transmitter/receiver and sample rate/frame sync generators */
258 	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
259 	spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
260 	spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
261 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
262 	toggle_clock(dev, playback);
263 }
264 
265 #define DEFAULT_BITPERSAMPLE	16
266 
267 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
268 				   unsigned int fmt)
269 {
270 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
271 	unsigned int pcr;
272 	unsigned int srgr;
273 	bool inv_fs = false;
274 	/* Attention srgr is updated by hw_params! */
275 	srgr = DAVINCI_MCBSP_SRGR_FSGM |
276 		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
277 		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
278 
279 	dev->fmt = fmt;
280 	/* set master/slave audio interface */
281 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
282 	case SND_SOC_DAIFMT_CBS_CFS:
283 		/* cpu is master */
284 		pcr = DAVINCI_MCBSP_PCR_FSXM |
285 			DAVINCI_MCBSP_PCR_FSRM |
286 			DAVINCI_MCBSP_PCR_CLKXM |
287 			DAVINCI_MCBSP_PCR_CLKRM;
288 		break;
289 	case SND_SOC_DAIFMT_CBM_CFS:
290 		pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
291 		/*
292 		 * Selection of the clock input pin that is the
293 		 * input for the Sample Rate Generator.
294 		 * McBSP FSR and FSX are driven by the Sample Rate
295 		 * Generator.
296 		 */
297 		switch (dev->clk_input_pin) {
298 		case MCBSP_CLKS:
299 			pcr |= DAVINCI_MCBSP_PCR_CLKXM |
300 				DAVINCI_MCBSP_PCR_CLKRM;
301 			break;
302 		case MCBSP_CLKR:
303 			pcr |= DAVINCI_MCBSP_PCR_SCLKME;
304 			break;
305 		default:
306 			dev_err(dev->dev, "bad clk_input_pin\n");
307 			return -EINVAL;
308 		}
309 
310 		break;
311 	case SND_SOC_DAIFMT_CBM_CFM:
312 		/* codec is master */
313 		pcr = 0;
314 		break;
315 	default:
316 		printk(KERN_ERR "%s:bad master\n", __func__);
317 		return -EINVAL;
318 	}
319 
320 	/* interface format */
321 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
322 	case SND_SOC_DAIFMT_I2S:
323 		/* Davinci doesn't support TRUE I2S, but some codecs will have
324 		 * the left and right channels contiguous. This allows
325 		 * dsp_a mode to be used with an inverted normal frame clk.
326 		 * If your codec is master and does not have contiguous
327 		 * channels, then you will have sound on only one channel.
328 		 * Try using a different mode, or codec as slave.
329 		 *
330 		 * The TLV320AIC33 is an example of a codec where this works.
331 		 * It has a variable bit clock frequency allowing it to have
332 		 * valid data on every bit clock.
333 		 *
334 		 * The TLV320AIC23 is an example of a codec where this does not
335 		 * work. It has a fixed bit clock frequency with progressively
336 		 * more empty bit clock slots between channels as the sample
337 		 * rate is lowered.
338 		 */
339 		inv_fs = true;
340 		/* fall through */
341 	case SND_SOC_DAIFMT_DSP_A:
342 		dev->mode = MOD_DSP_A;
343 		break;
344 	case SND_SOC_DAIFMT_DSP_B:
345 		dev->mode = MOD_DSP_B;
346 		break;
347 	default:
348 		printk(KERN_ERR "%s:bad format\n", __func__);
349 		return -EINVAL;
350 	}
351 
352 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
353 	case SND_SOC_DAIFMT_NB_NF:
354 		/* CLKRP Receive clock polarity,
355 		 *	1 - sampled on rising edge of CLKR
356 		 *	valid on rising edge
357 		 * CLKXP Transmit clock polarity,
358 		 *	1 - clocked on falling edge of CLKX
359 		 *	valid on rising edge
360 		 * FSRP  Receive frame sync pol, 0 - active high
361 		 * FSXP  Transmit frame sync pol, 0 - active high
362 		 */
363 		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
364 		break;
365 	case SND_SOC_DAIFMT_IB_IF:
366 		/* CLKRP Receive clock polarity,
367 		 *	0 - sampled on falling edge of CLKR
368 		 *	valid on falling edge
369 		 * CLKXP Transmit clock polarity,
370 		 *	0 - clocked on rising edge of CLKX
371 		 *	valid on falling edge
372 		 * FSRP  Receive frame sync pol, 1 - active low
373 		 * FSXP  Transmit frame sync pol, 1 - active low
374 		 */
375 		pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
376 		break;
377 	case SND_SOC_DAIFMT_NB_IF:
378 		/* CLKRP Receive clock polarity,
379 		 *	1 - sampled on rising edge of CLKR
380 		 *	valid on rising edge
381 		 * CLKXP Transmit clock polarity,
382 		 *	1 - clocked on falling edge of CLKX
383 		 *	valid on rising edge
384 		 * FSRP  Receive frame sync pol, 1 - active low
385 		 * FSXP  Transmit frame sync pol, 1 - active low
386 		 */
387 		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
388 			DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
389 		break;
390 	case SND_SOC_DAIFMT_IB_NF:
391 		/* CLKRP Receive clock polarity,
392 		 *	0 - sampled on falling edge of CLKR
393 		 *	valid on falling edge
394 		 * CLKXP Transmit clock polarity,
395 		 *	0 - clocked on rising edge of CLKX
396 		 *	valid on falling edge
397 		 * FSRP  Receive frame sync pol, 0 - active high
398 		 * FSXP  Transmit frame sync pol, 0 - active high
399 		 */
400 		break;
401 	default:
402 		return -EINVAL;
403 	}
404 	if (inv_fs == true)
405 		pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
406 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
407 	dev->pcr = pcr;
408 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
409 	return 0;
410 }
411 
412 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
413 				int div_id, int div)
414 {
415 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
416 
417 	if (div_id != DAVINCI_MCBSP_CLKGDV)
418 		return -ENODEV;
419 
420 	dev->clk_div = div;
421 	return 0;
422 }
423 
424 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
425 				 struct snd_pcm_hw_params *params,
426 				 struct snd_soc_dai *dai)
427 {
428 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
429 	struct snd_interval *i = NULL;
430 	int mcbsp_word_length, master;
431 	unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
432 	u32 spcr;
433 	snd_pcm_format_t fmt;
434 	unsigned element_cnt = 1;
435 
436 	/* general line settings */
437 	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
438 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
439 		spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
440 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
441 	} else {
442 		spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
443 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
444 	}
445 
446 	master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
447 	fmt = params_format(params);
448 	mcbsp_word_length = asp_word_length[fmt];
449 
450 	switch (master) {
451 	case SND_SOC_DAIFMT_CBS_CFS:
452 		freq = clk_get_rate(dev->clk);
453 		srgr = DAVINCI_MCBSP_SRGR_FSGM |
454 		       DAVINCI_MCBSP_SRGR_CLKSM;
455 		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
456 						8 - 1);
457 		if (dev->i2s_accurate_sck) {
458 			clk_div = 256;
459 			do {
460 				framesize = (freq / (--clk_div)) /
461 				params->rate_num *
462 					params->rate_den;
463 			} while (((framesize < 33) || (framesize > 4095)) &&
464 				 (clk_div));
465 			clk_div--;
466 			srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
467 		} else {
468 			/* symmetric waveforms */
469 			clk_div = freq / (mcbsp_word_length * 16) /
470 				  params->rate_num * params->rate_den;
471 			srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
472 							16 - 1);
473 		}
474 		clk_div &= 0xFF;
475 		srgr |= clk_div;
476 		break;
477 	case SND_SOC_DAIFMT_CBM_CFS:
478 		srgr = DAVINCI_MCBSP_SRGR_FSGM;
479 		clk_div = dev->clk_div - 1;
480 		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
481 		srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
482 		clk_div &= 0xFF;
483 		srgr |= clk_div;
484 		break;
485 	case SND_SOC_DAIFMT_CBM_CFM:
486 		/* Clock and frame sync given from external sources */
487 		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
488 		srgr = DAVINCI_MCBSP_SRGR_FSGM;
489 		srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
490 		pr_debug("%s - %d  FWID set: re-read srgr = %X\n",
491 			__func__, __LINE__, snd_interval_value(i) - 1);
492 
493 		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
494 		srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
495 		break;
496 	default:
497 		return -EINVAL;
498 	}
499 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
500 
501 	rcr = DAVINCI_MCBSP_RCR_RFIG;
502 	xcr = DAVINCI_MCBSP_XCR_XFIG;
503 	if (dev->mode == MOD_DSP_B) {
504 		rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
505 		xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
506 	} else {
507 		rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
508 		xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
509 	}
510 	/* Determine xfer data type */
511 	fmt = params_format(params);
512 	if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
513 		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
514 		return -EINVAL;
515 	}
516 
517 	if (params_channels(params) == 2) {
518 		element_cnt = 2;
519 		if (double_fmt[fmt] && dev->enable_channel_combine) {
520 			element_cnt = 1;
521 			fmt = double_fmt[fmt];
522 		}
523 		switch (master) {
524 		case SND_SOC_DAIFMT_CBS_CFS:
525 		case SND_SOC_DAIFMT_CBS_CFM:
526 			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
527 			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
528 			rcr |= DAVINCI_MCBSP_RCR_RPHASE;
529 			xcr |= DAVINCI_MCBSP_XCR_XPHASE;
530 			break;
531 		case SND_SOC_DAIFMT_CBM_CFM:
532 		case SND_SOC_DAIFMT_CBM_CFS:
533 			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
534 			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
535 			break;
536 		default:
537 			return -EINVAL;
538 		}
539 	}
540 	mcbsp_word_length = asp_word_length[fmt];
541 
542 	switch (master) {
543 	case SND_SOC_DAIFMT_CBS_CFS:
544 	case SND_SOC_DAIFMT_CBS_CFM:
545 		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
546 		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
547 		break;
548 	case SND_SOC_DAIFMT_CBM_CFM:
549 	case SND_SOC_DAIFMT_CBM_CFS:
550 		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
551 		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
552 		break;
553 	default:
554 		return -EINVAL;
555 	}
556 
557 	rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
558 		DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
559 	xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
560 		DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
561 
562 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
563 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
564 	else
565 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
566 
567 	pr_debug("%s - %d  srgr=%X\n", __func__, __LINE__, srgr);
568 	pr_debug("%s - %d  xcr=%X\n", __func__, __LINE__, xcr);
569 	pr_debug("%s - %d  rcr=%X\n", __func__, __LINE__, rcr);
570 	return 0;
571 }
572 
573 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
574 		struct snd_soc_dai *dai)
575 {
576 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
577 	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
578 	davinci_mcbsp_stop(dev, playback);
579 	return 0;
580 }
581 
582 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
583 			       struct snd_soc_dai *dai)
584 {
585 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
586 	int ret = 0;
587 	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
588 
589 	switch (cmd) {
590 	case SNDRV_PCM_TRIGGER_START:
591 	case SNDRV_PCM_TRIGGER_RESUME:
592 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
593 		davinci_mcbsp_start(dev, substream);
594 		break;
595 	case SNDRV_PCM_TRIGGER_STOP:
596 	case SNDRV_PCM_TRIGGER_SUSPEND:
597 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
598 		davinci_mcbsp_stop(dev, playback);
599 		break;
600 	default:
601 		ret = -EINVAL;
602 	}
603 	return ret;
604 }
605 
606 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
607 		struct snd_soc_dai *dai)
608 {
609 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
610 	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
611 	davinci_mcbsp_stop(dev, playback);
612 }
613 
614 #define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000
615 
616 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
617 	.shutdown	= davinci_i2s_shutdown,
618 	.prepare	= davinci_i2s_prepare,
619 	.trigger	= davinci_i2s_trigger,
620 	.hw_params	= davinci_i2s_hw_params,
621 	.set_fmt	= davinci_i2s_set_dai_fmt,
622 	.set_clkdiv	= davinci_i2s_dai_set_clkdiv,
623 
624 };
625 
626 static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
627 {
628 	struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
629 
630 	dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
631 	dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
632 
633 	return 0;
634 }
635 
636 static struct snd_soc_dai_driver davinci_i2s_dai = {
637 	.probe = davinci_i2s_dai_probe,
638 	.playback = {
639 		.channels_min = 2,
640 		.channels_max = 2,
641 		.rates = DAVINCI_I2S_RATES,
642 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
643 	.capture = {
644 		.channels_min = 2,
645 		.channels_max = 2,
646 		.rates = DAVINCI_I2S_RATES,
647 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
648 	.ops = &davinci_i2s_dai_ops,
649 
650 };
651 
652 static const struct snd_soc_component_driver davinci_i2s_component = {
653 	.name		= DRV_NAME,
654 };
655 
656 static int davinci_i2s_probe(struct platform_device *pdev)
657 {
658 	struct snd_dmaengine_dai_dma_data *dma_data;
659 	struct davinci_mcbsp_dev *dev;
660 	struct resource *mem, *res;
661 	void __iomem *io_base;
662 	int *dma;
663 	int ret;
664 
665 	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
666 	if (!mem) {
667 		dev_warn(&pdev->dev,
668 			 "\"mpu\" mem resource not found, using index 0\n");
669 		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
670 		if (!mem) {
671 			dev_err(&pdev->dev, "no mem resource?\n");
672 			return -ENODEV;
673 		}
674 	}
675 
676 	io_base = devm_ioremap_resource(&pdev->dev, mem);
677 	if (IS_ERR(io_base))
678 		return PTR_ERR(io_base);
679 
680 	dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
681 			   GFP_KERNEL);
682 	if (!dev)
683 		return -ENOMEM;
684 
685 	dev->base = io_base;
686 
687 	/* setup DMA, first TX, then RX */
688 	dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
689 	dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
690 
691 	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
692 	if (res) {
693 		dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
694 		*dma = res->start;
695 		dma_data->filter_data = dma;
696 	} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
697 		dma_data->filter_data = "tx";
698 	} else {
699 		dev_err(&pdev->dev, "Missing DMA tx resource\n");
700 		return -ENODEV;
701 	}
702 
703 	dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
704 	dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
705 
706 	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
707 	if (res) {
708 		dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
709 		*dma = res->start;
710 		dma_data->filter_data = dma;
711 	} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
712 		dma_data->filter_data = "rx";
713 	} else {
714 		dev_err(&pdev->dev, "Missing DMA rx resource\n");
715 		return -ENODEV;
716 	}
717 
718 	dev->clk = clk_get(&pdev->dev, NULL);
719 	if (IS_ERR(dev->clk))
720 		return -ENODEV;
721 	clk_enable(dev->clk);
722 
723 	dev->dev = &pdev->dev;
724 	dev_set_drvdata(&pdev->dev, dev);
725 
726 	ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
727 					 &davinci_i2s_dai, 1);
728 	if (ret != 0)
729 		goto err_release_clk;
730 
731 	ret = edma_pcm_platform_register(&pdev->dev);
732 	if (ret) {
733 		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
734 		goto err_unregister_component;
735 	}
736 
737 	return 0;
738 
739 err_unregister_component:
740 	snd_soc_unregister_component(&pdev->dev);
741 err_release_clk:
742 	clk_disable(dev->clk);
743 	clk_put(dev->clk);
744 	return ret;
745 }
746 
747 static int davinci_i2s_remove(struct platform_device *pdev)
748 {
749 	struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
750 
751 	snd_soc_unregister_component(&pdev->dev);
752 
753 	clk_disable(dev->clk);
754 	clk_put(dev->clk);
755 	dev->clk = NULL;
756 
757 	return 0;
758 }
759 
760 static const struct of_device_id davinci_i2s_match[] = {
761 	{ .compatible = "ti,da850-mcbsp" },
762 	{},
763 };
764 MODULE_DEVICE_TABLE(of, davinci_i2s_match);
765 
766 static struct platform_driver davinci_mcbsp_driver = {
767 	.probe		= davinci_i2s_probe,
768 	.remove		= davinci_i2s_remove,
769 	.driver		= {
770 		.name	= "davinci-mcbsp",
771 		.of_match_table = of_match_ptr(davinci_i2s_match),
772 	},
773 };
774 
775 module_platform_driver(davinci_mcbsp_driver);
776 
777 MODULE_AUTHOR("Vladimir Barinov");
778 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
779 MODULE_LICENSE("GPL");
780