1 /* 2 * tegra30_i2s.h - Definitions for Tegra30 I2S driver 3 * 4 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __TEGRA30_I2S_H__ 20 #define __TEGRA30_I2S_H__ 21 22 #include "tegra_pcm.h" 23 24 /* Register offsets from TEGRA30_I2S*_BASE */ 25 26 #define TEGRA30_I2S_CTRL 0x0 27 #define TEGRA30_I2S_TIMING 0x4 28 #define TEGRA30_I2S_OFFSET 0x08 29 #define TEGRA30_I2S_CH_CTRL 0x0c 30 #define TEGRA30_I2S_SLOT_CTRL 0x10 31 #define TEGRA30_I2S_CIF_RX_CTRL 0x14 32 #define TEGRA30_I2S_CIF_TX_CTRL 0x18 33 #define TEGRA30_I2S_FLOWCTL 0x1c 34 #define TEGRA30_I2S_TX_STEP 0x20 35 #define TEGRA30_I2S_FLOW_STATUS 0x24 36 #define TEGRA30_I2S_FLOW_TOTAL 0x28 37 #define TEGRA30_I2S_FLOW_OVER 0x2c 38 #define TEGRA30_I2S_FLOW_UNDER 0x30 39 #define TEGRA30_I2S_LCOEF_1_4_0 0x34 40 #define TEGRA30_I2S_LCOEF_1_4_1 0x38 41 #define TEGRA30_I2S_LCOEF_1_4_2 0x3c 42 #define TEGRA30_I2S_LCOEF_1_4_3 0x40 43 #define TEGRA30_I2S_LCOEF_1_4_4 0x44 44 #define TEGRA30_I2S_LCOEF_1_4_5 0x48 45 #define TEGRA30_I2S_LCOEF_2_4_0 0x4c 46 #define TEGRA30_I2S_LCOEF_2_4_1 0x50 47 #define TEGRA30_I2S_LCOEF_2_4_2 0x54 48 49 /* Fields in TEGRA30_I2S_CTRL */ 50 51 #define TEGRA30_I2S_CTRL_XFER_EN_TX (1 << 31) 52 #define TEGRA30_I2S_CTRL_XFER_EN_RX (1 << 30) 53 #define TEGRA30_I2S_CTRL_CG_EN (1 << 29) 54 #define TEGRA30_I2S_CTRL_SOFT_RESET (1 << 28) 55 #define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN (1 << 27) 56 57 #define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT 24 58 #define TEGRA30_I2S_CTRL_OBS_SEL_MASK (7 << TEGRA30_I2S_CTRL_OBS_SEL_SHIFT) 59 60 #define TEGRA30_I2S_FRAME_FORMAT_LRCK 0 61 #define TEGRA30_I2S_FRAME_FORMAT_FSYNC 1 62 63 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT 12 64 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT) 65 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK (TEGRA30_I2S_FRAME_FORMAT_LRCK << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT) 66 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC (TEGRA30_I2S_FRAME_FORMAT_FSYNC << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT) 67 68 #define TEGRA30_I2S_CTRL_MASTER_ENABLE (1 << 10) 69 70 #define TEGRA30_I2S_LRCK_LEFT_LOW 0 71 #define TEGRA30_I2S_LRCK_RIGHT_LOW 1 72 73 #define TEGRA30_I2S_CTRL_LRCK_SHIFT 9 74 #define TEGRA30_I2S_CTRL_LRCK_MASK (1 << TEGRA30_I2S_CTRL_LRCK_SHIFT) 75 #define TEGRA30_I2S_CTRL_LRCK_L_LOW (TEGRA30_I2S_LRCK_LEFT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT) 76 #define TEGRA30_I2S_CTRL_LRCK_R_LOW (TEGRA30_I2S_LRCK_RIGHT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT) 77 78 #define TEGRA30_I2S_CTRL_LPBK_ENABLE (1 << 8) 79 80 #define TEGRA30_I2S_BIT_CODE_LINEAR 0 81 #define TEGRA30_I2S_BIT_CODE_ULAW 1 82 #define TEGRA30_I2S_BIT_CODE_ALAW 2 83 84 #define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT 4 85 #define TEGRA30_I2S_CTRL_BIT_CODE_MASK (3 << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) 86 #define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR (TEGRA30_I2S_BIT_CODE_LINEAR << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) 87 #define TEGRA30_I2S_CTRL_BIT_CODE_ULAW (TEGRA30_I2S_BIT_CODE_ULAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) 88 #define TEGRA30_I2S_CTRL_BIT_CODE_ALAW (TEGRA30_I2S_BIT_CODE_ALAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) 89 90 #define TEGRA30_I2S_BITS_8 1 91 #define TEGRA30_I2S_BITS_12 2 92 #define TEGRA30_I2S_BITS_16 3 93 #define TEGRA30_I2S_BITS_20 4 94 #define TEGRA30_I2S_BITS_24 5 95 #define TEGRA30_I2S_BITS_28 6 96 #define TEGRA30_I2S_BITS_32 7 97 98 /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */ 99 #define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT 0 100 #define TEGRA30_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 101 #define TEGRA30_I2S_CTRL_BIT_SIZE_8 (TEGRA30_I2S_BITS_8 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 102 #define TEGRA30_I2S_CTRL_BIT_SIZE_12 (TEGRA30_I2S_BITS_12 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 103 #define TEGRA30_I2S_CTRL_BIT_SIZE_16 (TEGRA30_I2S_BITS_16 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 104 #define TEGRA30_I2S_CTRL_BIT_SIZE_20 (TEGRA30_I2S_BITS_20 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 105 #define TEGRA30_I2S_CTRL_BIT_SIZE_24 (TEGRA30_I2S_BITS_24 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 106 #define TEGRA30_I2S_CTRL_BIT_SIZE_28 (TEGRA30_I2S_BITS_28 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 107 #define TEGRA30_I2S_CTRL_BIT_SIZE_32 (TEGRA30_I2S_BITS_32 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) 108 109 /* Fields in TEGRA30_I2S_TIMING */ 110 111 #define TEGRA30_I2S_TIMING_NON_SYM_ENABLE (1 << 12) 112 #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0 113 #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff 114 #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT) 115 116 /* Fields in TEGRA30_I2S_OFFSET */ 117 118 #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT 16 119 #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US 0x7ff 120 #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) 121 #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT 0 122 #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US 0x7ff 123 #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT) 124 125 /* Fields in TEGRA30_I2S_CH_CTRL */ 126 127 /* (FSYNC width - 1) in bit clocks */ 128 #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT 24 129 #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US 0xff 130 #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK (TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT) 131 132 #define TEGRA30_I2S_HIGHZ_NO 0 133 #define TEGRA30_I2S_HIGHZ_YES 1 134 #define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK 2 135 136 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT 12 137 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) 138 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO (TEGRA30_I2S_HIGHZ_NO << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) 139 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES (TEGRA30_I2S_HIGHZ_YES << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) 140 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK (TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) 141 142 #define TEGRA30_I2S_MSB_FIRST 0 143 #define TEGRA30_I2S_LSB_FIRST 1 144 145 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT 10 146 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT) 147 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT) 148 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT) 149 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT 9 150 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT) 151 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT) 152 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT) 153 154 #define TEGRA30_I2S_POS_EDGE 0 155 #define TEGRA30_I2S_NEG_EDGE 1 156 157 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT 8 158 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK (1 << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT) 159 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE (TEGRA30_I2S_POS_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT) 160 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE (TEGRA30_I2S_NEG_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT) 161 162 /* Sample size is # bits from BIT_SIZE minus this field */ 163 #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT 4 164 #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US 7 165 #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT) 166 167 #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT 0 168 #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US 7 169 #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT) 170 171 /* Fields in TEGRA30_I2S_SLOT_CTRL */ 172 173 /* Number of slots in frame, minus 1 */ 174 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16 175 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7 176 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_SHIFT) 177 178 /* TDM mode slot enable bitmask */ 179 #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8 180 #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) 181 182 #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT 0 183 #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) 184 185 /* Fields in TEGRA30_I2S_CIF_RX_CTRL */ 186 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */ 187 188 /* Fields in TEGRA30_I2S_CIF_TX_CTRL */ 189 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */ 190 191 /* Fields in TEGRA30_I2S_FLOWCTL */ 192 193 #define TEGRA30_I2S_FILTER_LINEAR 0 194 #define TEGRA30_I2S_FILTER_QUAD 1 195 196 #define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT 31 197 #define TEGRA30_I2S_FLOWCTL_FILTER_MASK (1 << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT) 198 #define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR (TEGRA30_I2S_FILTER_LINEAR << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT) 199 #define TEGRA30_I2S_FLOWCTL_FILTER_QUAD (TEGRA30_I2S_FILTER_QUAD << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT) 200 201 /* Fields in TEGRA30_I2S_TX_STEP */ 202 203 #define TEGRA30_I2S_TX_STEP_SHIFT 0 204 #define TEGRA30_I2S_TX_STEP_MASK_US 0xffff 205 #define TEGRA30_I2S_TX_STEP_MASK (TEGRA30_I2S_TX_STEP_MASK_US << TEGRA30_I2S_TX_STEP_SHIFT) 206 207 /* Fields in TEGRA30_I2S_FLOW_STATUS */ 208 209 #define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW (1 << 31) 210 #define TEGRA30_I2S_FLOW_STATUS_OVERFLOW (1 << 30) 211 #define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN (1 << 4) 212 #define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR (1 << 3) 213 #define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR (1 << 2) 214 #define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN (1 << 1) 215 #define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN (1 << 0) 216 217 /* 218 * There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER, 219 * TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register. 220 */ 221 222 /* Fields in TEGRA30_I2S_LCOEF_* */ 223 224 #define TEGRA30_I2S_LCOEF_COEF_SHIFT 0 225 #define TEGRA30_I2S_LCOEF_COEF_MASK_US 0xffff 226 #define TEGRA30_I2S_LCOEF_COEF_MASK (TEGRA30_I2S_LCOEF_COEF_MASK_US << TEGRA30_I2S_LCOEF_COEF_SHIFT) 227 228 struct tegra30_i2s_soc_data { 229 void (*set_audio_cif)(struct regmap *regmap, 230 unsigned int reg, 231 struct tegra30_ahub_cif_conf *conf); 232 }; 233 234 struct tegra30_i2s { 235 const struct tegra30_i2s_soc_data *soc_data; 236 struct snd_soc_dai_driver dai; 237 int cif_id; 238 struct clk *clk_i2s; 239 enum tegra30_ahub_txcif capture_i2s_cif; 240 enum tegra30_ahub_rxcif capture_fifo_cif; 241 char capture_dma_chan[8]; 242 struct snd_dmaengine_dai_dma_data capture_dma_data; 243 enum tegra30_ahub_rxcif playback_i2s_cif; 244 enum tegra30_ahub_txcif playback_fifo_cif; 245 char playback_dma_chan[8]; 246 struct snd_dmaengine_dai_dma_data playback_dma_data; 247 struct regmap *regmap; 248 struct snd_dmaengine_pcm_config dma_config; 249 }; 250 251 #endif 252