1 /* 2 * tegra30_i2s.c - Tegra30 I2S driver 3 * 4 * Author: Stephen Warren <swarren@nvidia.com> 5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Based on code copyright/by: 8 * 9 * Copyright (c) 2009-2010, NVIDIA Corporation. 10 * Scott Peterson <speterson@nvidia.com> 11 * 12 * Copyright (C) 2010 Google, Inc. 13 * Iliyan Malchev <malchev@google.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms and conditions of the GNU General Public License, 17 * version 2, as published by the Free Software Foundation. 18 * 19 * This program is distributed in the hope it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 22 * more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/device.h> 30 #include <linux/io.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/regmap.h> 36 #include <linux/slab.h> 37 #include <sound/core.h> 38 #include <sound/pcm.h> 39 #include <sound/pcm_params.h> 40 #include <sound/soc.h> 41 #include <sound/dmaengine_pcm.h> 42 43 #include "tegra30_ahub.h" 44 #include "tegra30_i2s.h" 45 46 #define DRV_NAME "tegra30-i2s" 47 48 static int tegra30_i2s_runtime_suspend(struct device *dev) 49 { 50 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 51 52 regcache_cache_only(i2s->regmap, true); 53 54 clk_disable_unprepare(i2s->clk_i2s); 55 56 return 0; 57 } 58 59 static int tegra30_i2s_runtime_resume(struct device *dev) 60 { 61 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 62 int ret; 63 64 ret = clk_prepare_enable(i2s->clk_i2s); 65 if (ret) { 66 dev_err(dev, "clk_enable failed: %d\n", ret); 67 return ret; 68 } 69 70 regcache_cache_only(i2s->regmap, false); 71 72 return 0; 73 } 74 75 static int tegra30_i2s_startup(struct snd_pcm_substream *substream, 76 struct snd_soc_dai *dai) 77 { 78 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 79 int ret; 80 81 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 82 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, 83 &i2s->playback_dma_data.addr, 84 &i2s->playback_dma_data.slave_id); 85 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 86 i2s->playback_dma_data.maxburst = 4; 87 tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, 88 i2s->playback_fifo_cif); 89 } else { 90 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, 91 &i2s->capture_dma_data.addr, 92 &i2s->capture_dma_data.slave_id); 93 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 94 i2s->capture_dma_data.maxburst = 4; 95 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, 96 i2s->capture_i2s_cif); 97 } 98 99 return ret; 100 } 101 102 static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream, 103 struct snd_soc_dai *dai) 104 { 105 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 106 107 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 108 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); 109 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); 110 } else { 111 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); 112 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); 113 } 114 } 115 116 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai, 117 unsigned int fmt) 118 { 119 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 120 unsigned int mask, val; 121 122 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 123 case SND_SOC_DAIFMT_NB_NF: 124 break; 125 default: 126 return -EINVAL; 127 } 128 129 mask = TEGRA30_I2S_CTRL_MASTER_ENABLE; 130 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 131 case SND_SOC_DAIFMT_CBS_CFS: 132 val = TEGRA30_I2S_CTRL_MASTER_ENABLE; 133 break; 134 case SND_SOC_DAIFMT_CBM_CFM: 135 break; 136 default: 137 return -EINVAL; 138 } 139 140 mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK | 141 TEGRA30_I2S_CTRL_LRCK_MASK; 142 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 143 case SND_SOC_DAIFMT_DSP_A: 144 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; 145 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 146 break; 147 case SND_SOC_DAIFMT_DSP_B: 148 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; 149 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW; 150 break; 151 case SND_SOC_DAIFMT_I2S: 152 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; 153 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 154 break; 155 case SND_SOC_DAIFMT_RIGHT_J: 156 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; 157 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 158 break; 159 case SND_SOC_DAIFMT_LEFT_J: 160 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; 161 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 162 break; 163 default: 164 return -EINVAL; 165 } 166 167 pm_runtime_get_sync(dai->dev); 168 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); 169 pm_runtime_put(dai->dev); 170 171 return 0; 172 } 173 174 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream, 175 struct snd_pcm_hw_params *params, 176 struct snd_soc_dai *dai) 177 { 178 struct device *dev = dai->dev; 179 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 180 unsigned int mask, val, reg; 181 int ret, sample_size, srate, i2sclock, bitcnt; 182 183 if (params_channels(params) != 2) 184 return -EINVAL; 185 186 mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK; 187 switch (params_format(params)) { 188 case SNDRV_PCM_FORMAT_S16_LE: 189 val = TEGRA30_I2S_CTRL_BIT_SIZE_16; 190 sample_size = 16; 191 break; 192 default: 193 return -EINVAL; 194 } 195 196 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); 197 198 srate = params_rate(params); 199 200 /* Final "* 2" required by Tegra hardware */ 201 i2sclock = srate * params_channels(params) * sample_size * 2; 202 203 bitcnt = (i2sclock / (2 * srate)) - 1; 204 if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) 205 return -EINVAL; 206 207 ret = clk_set_rate(i2s->clk_i2s, i2sclock); 208 if (ret) { 209 dev_err(dev, "Can't set I2S clock rate: %d\n", ret); 210 return ret; 211 } 212 213 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; 214 215 if (i2sclock % (2 * srate)) 216 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE; 217 218 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val); 219 220 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 221 (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 222 (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 223 TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 | 224 TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16; 225 226 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 227 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX; 228 reg = TEGRA30_I2S_CIF_RX_CTRL; 229 } else { 230 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX; 231 reg = TEGRA30_I2S_CIF_TX_CTRL; 232 } 233 234 regmap_write(i2s->regmap, reg, val); 235 236 val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) | 237 (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT); 238 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val); 239 240 return 0; 241 } 242 243 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s) 244 { 245 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif); 246 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 247 TEGRA30_I2S_CTRL_XFER_EN_TX, 248 TEGRA30_I2S_CTRL_XFER_EN_TX); 249 } 250 251 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s) 252 { 253 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif); 254 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 255 TEGRA30_I2S_CTRL_XFER_EN_TX, 0); 256 } 257 258 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s) 259 { 260 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif); 261 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 262 TEGRA30_I2S_CTRL_XFER_EN_RX, 263 TEGRA30_I2S_CTRL_XFER_EN_RX); 264 } 265 266 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s) 267 { 268 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif); 269 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 270 TEGRA30_I2S_CTRL_XFER_EN_RX, 0); 271 } 272 273 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 274 struct snd_soc_dai *dai) 275 { 276 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 277 278 switch (cmd) { 279 case SNDRV_PCM_TRIGGER_START: 280 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 281 case SNDRV_PCM_TRIGGER_RESUME: 282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 283 tegra30_i2s_start_playback(i2s); 284 else 285 tegra30_i2s_start_capture(i2s); 286 break; 287 case SNDRV_PCM_TRIGGER_STOP: 288 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 289 case SNDRV_PCM_TRIGGER_SUSPEND: 290 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 291 tegra30_i2s_stop_playback(i2s); 292 else 293 tegra30_i2s_stop_capture(i2s); 294 break; 295 default: 296 return -EINVAL; 297 } 298 299 return 0; 300 } 301 302 static int tegra30_i2s_probe(struct snd_soc_dai *dai) 303 { 304 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 305 306 dai->capture_dma_data = &i2s->capture_dma_data; 307 dai->playback_dma_data = &i2s->playback_dma_data; 308 309 return 0; 310 } 311 312 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = { 313 .startup = tegra30_i2s_startup, 314 .shutdown = tegra30_i2s_shutdown, 315 .set_fmt = tegra30_i2s_set_fmt, 316 .hw_params = tegra30_i2s_hw_params, 317 .trigger = tegra30_i2s_trigger, 318 }; 319 320 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = { 321 .probe = tegra30_i2s_probe, 322 .playback = { 323 .stream_name = "Playback", 324 .channels_min = 2, 325 .channels_max = 2, 326 .rates = SNDRV_PCM_RATE_8000_96000, 327 .formats = SNDRV_PCM_FMTBIT_S16_LE, 328 }, 329 .capture = { 330 .stream_name = "Capture", 331 .channels_min = 2, 332 .channels_max = 2, 333 .rates = SNDRV_PCM_RATE_8000_96000, 334 .formats = SNDRV_PCM_FMTBIT_S16_LE, 335 }, 336 .ops = &tegra30_i2s_dai_ops, 337 .symmetric_rates = 1, 338 }; 339 340 static const struct snd_soc_component_driver tegra30_i2s_component = { 341 .name = DRV_NAME, 342 }; 343 344 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg) 345 { 346 switch (reg) { 347 case TEGRA30_I2S_CTRL: 348 case TEGRA30_I2S_TIMING: 349 case TEGRA30_I2S_OFFSET: 350 case TEGRA30_I2S_CH_CTRL: 351 case TEGRA30_I2S_SLOT_CTRL: 352 case TEGRA30_I2S_CIF_RX_CTRL: 353 case TEGRA30_I2S_CIF_TX_CTRL: 354 case TEGRA30_I2S_FLOWCTL: 355 case TEGRA30_I2S_TX_STEP: 356 case TEGRA30_I2S_FLOW_STATUS: 357 case TEGRA30_I2S_FLOW_TOTAL: 358 case TEGRA30_I2S_FLOW_OVER: 359 case TEGRA30_I2S_FLOW_UNDER: 360 case TEGRA30_I2S_LCOEF_1_4_0: 361 case TEGRA30_I2S_LCOEF_1_4_1: 362 case TEGRA30_I2S_LCOEF_1_4_2: 363 case TEGRA30_I2S_LCOEF_1_4_3: 364 case TEGRA30_I2S_LCOEF_1_4_4: 365 case TEGRA30_I2S_LCOEF_1_4_5: 366 case TEGRA30_I2S_LCOEF_2_4_0: 367 case TEGRA30_I2S_LCOEF_2_4_1: 368 case TEGRA30_I2S_LCOEF_2_4_2: 369 return true; 370 default: 371 return false; 372 }; 373 } 374 375 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg) 376 { 377 switch (reg) { 378 case TEGRA30_I2S_FLOW_STATUS: 379 case TEGRA30_I2S_FLOW_TOTAL: 380 case TEGRA30_I2S_FLOW_OVER: 381 case TEGRA30_I2S_FLOW_UNDER: 382 return true; 383 default: 384 return false; 385 }; 386 } 387 388 static const struct regmap_config tegra30_i2s_regmap_config = { 389 .reg_bits = 32, 390 .reg_stride = 4, 391 .val_bits = 32, 392 .max_register = TEGRA30_I2S_LCOEF_2_4_2, 393 .writeable_reg = tegra30_i2s_wr_rd_reg, 394 .readable_reg = tegra30_i2s_wr_rd_reg, 395 .volatile_reg = tegra30_i2s_volatile_reg, 396 .cache_type = REGCACHE_RBTREE, 397 }; 398 399 static int tegra30_i2s_platform_probe(struct platform_device *pdev) 400 { 401 struct tegra30_i2s *i2s; 402 u32 cif_ids[2]; 403 struct resource *mem, *memregion; 404 void __iomem *regs; 405 int ret; 406 407 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL); 408 if (!i2s) { 409 dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n"); 410 ret = -ENOMEM; 411 goto err; 412 } 413 dev_set_drvdata(&pdev->dev, i2s); 414 415 i2s->dai = tegra30_i2s_dai_template; 416 i2s->dai.name = dev_name(&pdev->dev); 417 418 ret = of_property_read_u32_array(pdev->dev.of_node, 419 "nvidia,ahub-cif-ids", cif_ids, 420 ARRAY_SIZE(cif_ids)); 421 if (ret < 0) 422 goto err; 423 424 i2s->playback_i2s_cif = cif_ids[0]; 425 i2s->capture_i2s_cif = cif_ids[1]; 426 427 i2s->clk_i2s = clk_get(&pdev->dev, NULL); 428 if (IS_ERR(i2s->clk_i2s)) { 429 dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); 430 ret = PTR_ERR(i2s->clk_i2s); 431 goto err; 432 } 433 434 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 435 if (!mem) { 436 dev_err(&pdev->dev, "No memory resource\n"); 437 ret = -ENODEV; 438 goto err_clk_put; 439 } 440 441 memregion = devm_request_mem_region(&pdev->dev, mem->start, 442 resource_size(mem), DRV_NAME); 443 if (!memregion) { 444 dev_err(&pdev->dev, "Memory region already claimed\n"); 445 ret = -EBUSY; 446 goto err_clk_put; 447 } 448 449 regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 450 if (!regs) { 451 dev_err(&pdev->dev, "ioremap failed\n"); 452 ret = -ENOMEM; 453 goto err_clk_put; 454 } 455 456 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 457 &tegra30_i2s_regmap_config); 458 if (IS_ERR(i2s->regmap)) { 459 dev_err(&pdev->dev, "regmap init failed\n"); 460 ret = PTR_ERR(i2s->regmap); 461 goto err_clk_put; 462 } 463 regcache_cache_only(i2s->regmap, true); 464 465 pm_runtime_enable(&pdev->dev); 466 if (!pm_runtime_enabled(&pdev->dev)) { 467 ret = tegra30_i2s_runtime_resume(&pdev->dev); 468 if (ret) 469 goto err_pm_disable; 470 } 471 472 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component, 473 &i2s->dai, 1); 474 if (ret) { 475 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); 476 ret = -ENOMEM; 477 goto err_suspend; 478 } 479 480 ret = tegra_pcm_platform_register(&pdev->dev); 481 if (ret) { 482 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); 483 goto err_unregister_component; 484 } 485 486 return 0; 487 488 err_unregister_component: 489 snd_soc_unregister_component(&pdev->dev); 490 err_suspend: 491 if (!pm_runtime_status_suspended(&pdev->dev)) 492 tegra30_i2s_runtime_suspend(&pdev->dev); 493 err_pm_disable: 494 pm_runtime_disable(&pdev->dev); 495 err_clk_put: 496 clk_put(i2s->clk_i2s); 497 err: 498 return ret; 499 } 500 501 static int tegra30_i2s_platform_remove(struct platform_device *pdev) 502 { 503 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev); 504 505 pm_runtime_disable(&pdev->dev); 506 if (!pm_runtime_status_suspended(&pdev->dev)) 507 tegra30_i2s_runtime_suspend(&pdev->dev); 508 509 tegra_pcm_platform_unregister(&pdev->dev); 510 snd_soc_unregister_component(&pdev->dev); 511 512 clk_put(i2s->clk_i2s); 513 514 return 0; 515 } 516 517 #ifdef CONFIG_PM_SLEEP 518 static int tegra30_i2s_suspend(struct device *dev) 519 { 520 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 521 522 regcache_mark_dirty(i2s->regmap); 523 524 return 0; 525 } 526 527 static int tegra30_i2s_resume(struct device *dev) 528 { 529 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 530 int ret; 531 532 ret = pm_runtime_get_sync(dev); 533 if (ret < 0) 534 return ret; 535 ret = regcache_sync(i2s->regmap); 536 pm_runtime_put(dev); 537 538 return ret; 539 } 540 #endif 541 542 static const struct of_device_id tegra30_i2s_of_match[] = { 543 { .compatible = "nvidia,tegra30-i2s", }, 544 {}, 545 }; 546 547 static const struct dev_pm_ops tegra30_i2s_pm_ops = { 548 SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend, 549 tegra30_i2s_runtime_resume, NULL) 550 SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume) 551 }; 552 553 static struct platform_driver tegra30_i2s_driver = { 554 .driver = { 555 .name = DRV_NAME, 556 .owner = THIS_MODULE, 557 .of_match_table = tegra30_i2s_of_match, 558 .pm = &tegra30_i2s_pm_ops, 559 }, 560 .probe = tegra30_i2s_platform_probe, 561 .remove = tegra30_i2s_platform_remove, 562 }; 563 module_platform_driver(tegra30_i2s_driver); 564 565 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 566 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver"); 567 MODULE_LICENSE("GPL"); 568 MODULE_ALIAS("platform:" DRV_NAME); 569 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match); 570