1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tegra30_i2s.c - Tegra30 I2S driver 4 * 5 * Author: Stephen Warren <swarren@nvidia.com> 6 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Based on code copyright/by: 9 * 10 * Copyright (c) 2009-2010, NVIDIA Corporation. 11 * Scott Peterson <speterson@nvidia.com> 12 * 13 * Copyright (C) 2010 Google, Inc. 14 * Iliyan Malchev <malchev@google.com> 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/device.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/dmaengine_pcm.h> 32 33 #include "tegra30_ahub.h" 34 #include "tegra30_i2s.h" 35 36 #define DRV_NAME "tegra30-i2s" 37 38 static int tegra30_i2s_runtime_suspend(struct device *dev) 39 { 40 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 41 42 regcache_cache_only(i2s->regmap, true); 43 44 clk_disable_unprepare(i2s->clk_i2s); 45 46 return 0; 47 } 48 49 static int tegra30_i2s_runtime_resume(struct device *dev) 50 { 51 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 52 int ret; 53 54 ret = clk_prepare_enable(i2s->clk_i2s); 55 if (ret) { 56 dev_err(dev, "clk_enable failed: %d\n", ret); 57 return ret; 58 } 59 60 regcache_cache_only(i2s->regmap, false); 61 62 return 0; 63 } 64 65 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai, 66 unsigned int fmt) 67 { 68 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 69 unsigned int mask = 0, val = 0; 70 71 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 72 case SND_SOC_DAIFMT_NB_NF: 73 break; 74 default: 75 return -EINVAL; 76 } 77 78 mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE; 79 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 80 case SND_SOC_DAIFMT_CBS_CFS: 81 val |= TEGRA30_I2S_CTRL_MASTER_ENABLE; 82 break; 83 case SND_SOC_DAIFMT_CBM_CFM: 84 break; 85 default: 86 return -EINVAL; 87 } 88 89 mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK | 90 TEGRA30_I2S_CTRL_LRCK_MASK; 91 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 92 case SND_SOC_DAIFMT_DSP_A: 93 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; 94 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 95 break; 96 case SND_SOC_DAIFMT_DSP_B: 97 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; 98 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW; 99 break; 100 case SND_SOC_DAIFMT_I2S: 101 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; 102 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 103 break; 104 case SND_SOC_DAIFMT_RIGHT_J: 105 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; 106 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 107 break; 108 case SND_SOC_DAIFMT_LEFT_J: 109 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK; 110 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW; 111 break; 112 default: 113 return -EINVAL; 114 } 115 116 pm_runtime_get_sync(dai->dev); 117 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); 118 pm_runtime_put(dai->dev); 119 120 return 0; 121 } 122 123 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream, 124 struct snd_pcm_hw_params *params, 125 struct snd_soc_dai *dai) 126 { 127 struct device *dev = dai->dev; 128 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 129 unsigned int mask, val, reg; 130 int ret, sample_size, srate, i2sclock, bitcnt, audio_bits; 131 struct tegra30_ahub_cif_conf cif_conf; 132 133 if (params_channels(params) != 2) 134 return -EINVAL; 135 136 mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK; 137 switch (params_format(params)) { 138 case SNDRV_PCM_FORMAT_S16_LE: 139 val = TEGRA30_I2S_CTRL_BIT_SIZE_16; 140 audio_bits = TEGRA30_AUDIOCIF_BITS_16; 141 sample_size = 16; 142 break; 143 case SNDRV_PCM_FORMAT_S24_LE: 144 val = TEGRA30_I2S_CTRL_BIT_SIZE_24; 145 audio_bits = TEGRA30_AUDIOCIF_BITS_24; 146 sample_size = 24; 147 break; 148 case SNDRV_PCM_FORMAT_S32_LE: 149 val = TEGRA30_I2S_CTRL_BIT_SIZE_32; 150 audio_bits = TEGRA30_AUDIOCIF_BITS_32; 151 sample_size = 32; 152 break; 153 default: 154 return -EINVAL; 155 } 156 157 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); 158 159 srate = params_rate(params); 160 161 /* Final "* 2" required by Tegra hardware */ 162 i2sclock = srate * params_channels(params) * sample_size * 2; 163 164 bitcnt = (i2sclock / (2 * srate)) - 1; 165 if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) 166 return -EINVAL; 167 168 ret = clk_set_rate(i2s->clk_i2s, i2sclock); 169 if (ret) { 170 dev_err(dev, "Can't set I2S clock rate: %d\n", ret); 171 return ret; 172 } 173 174 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; 175 176 if (i2sclock % (2 * srate)) 177 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE; 178 179 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val); 180 181 cif_conf.threshold = 0; 182 cif_conf.audio_channels = 2; 183 cif_conf.client_channels = 2; 184 cif_conf.audio_bits = audio_bits; 185 cif_conf.client_bits = audio_bits; 186 cif_conf.expand = 0; 187 cif_conf.stereo_conv = 0; 188 cif_conf.replicate = 0; 189 cif_conf.truncate = 0; 190 cif_conf.mono_conv = 0; 191 192 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 193 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX; 194 reg = TEGRA30_I2S_CIF_RX_CTRL; 195 } else { 196 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX; 197 reg = TEGRA30_I2S_CIF_TX_CTRL; 198 } 199 200 i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf); 201 202 val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) | 203 (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT); 204 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val); 205 206 return 0; 207 } 208 209 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s) 210 { 211 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif); 212 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 213 TEGRA30_I2S_CTRL_XFER_EN_TX, 214 TEGRA30_I2S_CTRL_XFER_EN_TX); 215 } 216 217 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s) 218 { 219 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif); 220 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 221 TEGRA30_I2S_CTRL_XFER_EN_TX, 0); 222 } 223 224 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s) 225 { 226 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif); 227 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 228 TEGRA30_I2S_CTRL_XFER_EN_RX, 229 TEGRA30_I2S_CTRL_XFER_EN_RX); 230 } 231 232 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s) 233 { 234 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, 235 TEGRA30_I2S_CTRL_XFER_EN_RX, 0); 236 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif); 237 } 238 239 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 240 struct snd_soc_dai *dai) 241 { 242 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 243 244 switch (cmd) { 245 case SNDRV_PCM_TRIGGER_START: 246 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 247 case SNDRV_PCM_TRIGGER_RESUME: 248 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 249 tegra30_i2s_start_playback(i2s); 250 else 251 tegra30_i2s_start_capture(i2s); 252 break; 253 case SNDRV_PCM_TRIGGER_STOP: 254 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 255 case SNDRV_PCM_TRIGGER_SUSPEND: 256 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 257 tegra30_i2s_stop_playback(i2s); 258 else 259 tegra30_i2s_stop_capture(i2s); 260 break; 261 default: 262 return -EINVAL; 263 } 264 265 return 0; 266 } 267 268 static int tegra30_i2s_set_tdm(struct snd_soc_dai *dai, 269 unsigned int tx_mask, unsigned int rx_mask, 270 int slots, int slot_width) 271 { 272 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 273 unsigned int mask, val; 274 275 dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n", 276 __func__, tx_mask, rx_mask, slots, slot_width); 277 278 mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK | 279 TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK | 280 TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK; 281 282 val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) | 283 (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) | 284 ((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT); 285 286 pm_runtime_get_sync(dai->dev); 287 regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val); 288 /* set the fsync width to minimum of 1 clock width */ 289 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL, 290 TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK, 0x0); 291 pm_runtime_put(dai->dev); 292 293 return 0; 294 } 295 296 static int tegra30_i2s_probe(struct snd_soc_dai *dai) 297 { 298 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai); 299 300 dai->capture_dma_data = &i2s->capture_dma_data; 301 dai->playback_dma_data = &i2s->playback_dma_data; 302 303 return 0; 304 } 305 306 static const struct snd_soc_dai_ops tegra30_i2s_dai_ops = { 307 .set_fmt = tegra30_i2s_set_fmt, 308 .hw_params = tegra30_i2s_hw_params, 309 .trigger = tegra30_i2s_trigger, 310 .set_tdm_slot = tegra30_i2s_set_tdm, 311 }; 312 313 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = { 314 .probe = tegra30_i2s_probe, 315 .playback = { 316 .stream_name = "Playback", 317 .channels_min = 2, 318 .channels_max = 2, 319 .rates = SNDRV_PCM_RATE_8000_96000, 320 .formats = SNDRV_PCM_FMTBIT_S32_LE | 321 SNDRV_PCM_FMTBIT_S24_LE | 322 SNDRV_PCM_FMTBIT_S16_LE, 323 }, 324 .capture = { 325 .stream_name = "Capture", 326 .channels_min = 2, 327 .channels_max = 2, 328 .rates = SNDRV_PCM_RATE_8000_96000, 329 .formats = SNDRV_PCM_FMTBIT_S32_LE | 330 SNDRV_PCM_FMTBIT_S24_LE | 331 SNDRV_PCM_FMTBIT_S16_LE, 332 }, 333 .ops = &tegra30_i2s_dai_ops, 334 .symmetric_rates = 1, 335 }; 336 337 static const struct snd_soc_component_driver tegra30_i2s_component = { 338 .name = DRV_NAME, 339 }; 340 341 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg) 342 { 343 switch (reg) { 344 case TEGRA30_I2S_CTRL: 345 case TEGRA30_I2S_TIMING: 346 case TEGRA30_I2S_OFFSET: 347 case TEGRA30_I2S_CH_CTRL: 348 case TEGRA30_I2S_SLOT_CTRL: 349 case TEGRA30_I2S_CIF_RX_CTRL: 350 case TEGRA30_I2S_CIF_TX_CTRL: 351 case TEGRA30_I2S_FLOWCTL: 352 case TEGRA30_I2S_TX_STEP: 353 case TEGRA30_I2S_FLOW_STATUS: 354 case TEGRA30_I2S_FLOW_TOTAL: 355 case TEGRA30_I2S_FLOW_OVER: 356 case TEGRA30_I2S_FLOW_UNDER: 357 case TEGRA30_I2S_LCOEF_1_4_0: 358 case TEGRA30_I2S_LCOEF_1_4_1: 359 case TEGRA30_I2S_LCOEF_1_4_2: 360 case TEGRA30_I2S_LCOEF_1_4_3: 361 case TEGRA30_I2S_LCOEF_1_4_4: 362 case TEGRA30_I2S_LCOEF_1_4_5: 363 case TEGRA30_I2S_LCOEF_2_4_0: 364 case TEGRA30_I2S_LCOEF_2_4_1: 365 case TEGRA30_I2S_LCOEF_2_4_2: 366 return true; 367 default: 368 return false; 369 } 370 } 371 372 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg) 373 { 374 switch (reg) { 375 case TEGRA30_I2S_FLOW_STATUS: 376 case TEGRA30_I2S_FLOW_TOTAL: 377 case TEGRA30_I2S_FLOW_OVER: 378 case TEGRA30_I2S_FLOW_UNDER: 379 return true; 380 default: 381 return false; 382 } 383 } 384 385 static const struct regmap_config tegra30_i2s_regmap_config = { 386 .reg_bits = 32, 387 .reg_stride = 4, 388 .val_bits = 32, 389 .max_register = TEGRA30_I2S_LCOEF_2_4_2, 390 .writeable_reg = tegra30_i2s_wr_rd_reg, 391 .readable_reg = tegra30_i2s_wr_rd_reg, 392 .volatile_reg = tegra30_i2s_volatile_reg, 393 .cache_type = REGCACHE_FLAT, 394 }; 395 396 static const struct tegra30_i2s_soc_data tegra30_i2s_config = { 397 .set_audio_cif = tegra30_ahub_set_cif, 398 }; 399 400 static const struct tegra30_i2s_soc_data tegra124_i2s_config = { 401 .set_audio_cif = tegra124_ahub_set_cif, 402 }; 403 404 static const struct of_device_id tegra30_i2s_of_match[] = { 405 { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config }, 406 { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config }, 407 {}, 408 }; 409 410 static int tegra30_i2s_platform_probe(struct platform_device *pdev) 411 { 412 struct tegra30_i2s *i2s; 413 const struct of_device_id *match; 414 u32 cif_ids[2]; 415 void __iomem *regs; 416 int ret; 417 418 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL); 419 if (!i2s) { 420 ret = -ENOMEM; 421 goto err; 422 } 423 dev_set_drvdata(&pdev->dev, i2s); 424 425 match = of_match_device(tegra30_i2s_of_match, &pdev->dev); 426 if (!match) { 427 dev_err(&pdev->dev, "Error: No device match found\n"); 428 ret = -ENODEV; 429 goto err; 430 } 431 i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data; 432 433 i2s->dai = tegra30_i2s_dai_template; 434 i2s->dai.name = dev_name(&pdev->dev); 435 436 ret = of_property_read_u32_array(pdev->dev.of_node, 437 "nvidia,ahub-cif-ids", cif_ids, 438 ARRAY_SIZE(cif_ids)); 439 if (ret < 0) 440 goto err; 441 442 i2s->playback_i2s_cif = cif_ids[0]; 443 i2s->capture_i2s_cif = cif_ids[1]; 444 445 i2s->clk_i2s = clk_get(&pdev->dev, NULL); 446 if (IS_ERR(i2s->clk_i2s)) { 447 dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); 448 ret = PTR_ERR(i2s->clk_i2s); 449 goto err; 450 } 451 452 regs = devm_platform_ioremap_resource(pdev, 0); 453 if (IS_ERR(regs)) { 454 ret = PTR_ERR(regs); 455 goto err_clk_put; 456 } 457 458 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 459 &tegra30_i2s_regmap_config); 460 if (IS_ERR(i2s->regmap)) { 461 dev_err(&pdev->dev, "regmap init failed\n"); 462 ret = PTR_ERR(i2s->regmap); 463 goto err_clk_put; 464 } 465 regcache_cache_only(i2s->regmap, true); 466 467 pm_runtime_enable(&pdev->dev); 468 if (!pm_runtime_enabled(&pdev->dev)) { 469 ret = tegra30_i2s_runtime_resume(&pdev->dev); 470 if (ret) 471 goto err_pm_disable; 472 } 473 474 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 475 i2s->playback_dma_data.maxburst = 4; 476 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, 477 i2s->playback_dma_chan, 478 sizeof(i2s->playback_dma_chan), 479 &i2s->playback_dma_data.addr); 480 if (ret) { 481 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); 482 goto err_suspend; 483 } 484 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, 485 i2s->playback_fifo_cif); 486 if (ret) { 487 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret); 488 goto err_free_tx_fifo; 489 } 490 491 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 492 i2s->capture_dma_data.maxburst = 4; 493 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, 494 i2s->capture_dma_chan, 495 sizeof(i2s->capture_dma_chan), 496 &i2s->capture_dma_data.addr); 497 if (ret) { 498 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); 499 goto err_unroute_tx_fifo; 500 } 501 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, 502 i2s->capture_i2s_cif); 503 if (ret) { 504 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret); 505 goto err_free_rx_fifo; 506 } 507 508 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component, 509 &i2s->dai, 1); 510 if (ret) { 511 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); 512 ret = -ENOMEM; 513 goto err_unroute_rx_fifo; 514 } 515 516 ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev, 517 &i2s->dma_config, i2s->playback_dma_chan, 518 i2s->capture_dma_chan); 519 if (ret) { 520 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); 521 goto err_unregister_component; 522 } 523 524 return 0; 525 526 err_unregister_component: 527 snd_soc_unregister_component(&pdev->dev); 528 err_unroute_rx_fifo: 529 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); 530 err_free_rx_fifo: 531 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); 532 err_unroute_tx_fifo: 533 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); 534 err_free_tx_fifo: 535 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); 536 err_suspend: 537 if (!pm_runtime_status_suspended(&pdev->dev)) 538 tegra30_i2s_runtime_suspend(&pdev->dev); 539 err_pm_disable: 540 pm_runtime_disable(&pdev->dev); 541 err_clk_put: 542 clk_put(i2s->clk_i2s); 543 err: 544 return ret; 545 } 546 547 static int tegra30_i2s_platform_remove(struct platform_device *pdev) 548 { 549 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev); 550 551 pm_runtime_disable(&pdev->dev); 552 if (!pm_runtime_status_suspended(&pdev->dev)) 553 tegra30_i2s_runtime_suspend(&pdev->dev); 554 555 tegra_pcm_platform_unregister(&pdev->dev); 556 snd_soc_unregister_component(&pdev->dev); 557 558 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif); 559 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif); 560 561 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif); 562 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif); 563 564 clk_put(i2s->clk_i2s); 565 566 return 0; 567 } 568 569 #ifdef CONFIG_PM_SLEEP 570 static int tegra30_i2s_suspend(struct device *dev) 571 { 572 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 573 574 regcache_mark_dirty(i2s->regmap); 575 576 return 0; 577 } 578 579 static int tegra30_i2s_resume(struct device *dev) 580 { 581 struct tegra30_i2s *i2s = dev_get_drvdata(dev); 582 int ret; 583 584 ret = pm_runtime_get_sync(dev); 585 if (ret < 0) 586 return ret; 587 ret = regcache_sync(i2s->regmap); 588 pm_runtime_put(dev); 589 590 return ret; 591 } 592 #endif 593 594 static const struct dev_pm_ops tegra30_i2s_pm_ops = { 595 SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend, 596 tegra30_i2s_runtime_resume, NULL) 597 SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume) 598 }; 599 600 static struct platform_driver tegra30_i2s_driver = { 601 .driver = { 602 .name = DRV_NAME, 603 .of_match_table = tegra30_i2s_of_match, 604 .pm = &tegra30_i2s_pm_ops, 605 }, 606 .probe = tegra30_i2s_platform_probe, 607 .remove = tegra30_i2s_platform_remove, 608 }; 609 module_platform_driver(tegra30_i2s_driver); 610 611 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 612 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver"); 613 MODULE_LICENSE("GPL"); 614 MODULE_ALIAS("platform:" DRV_NAME); 615 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match); 616