1be944d42SStephen Warren /* 2be944d42SStephen Warren * tegra30_ahub.h - Definitions for Tegra30 AHUB driver 3be944d42SStephen Warren * 4be944d42SStephen Warren * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 5be944d42SStephen Warren * 6be944d42SStephen Warren * This program is free software; you can redistribute it and/or modify it 7be944d42SStephen Warren * under the terms and conditions of the GNU General Public License, 8be944d42SStephen Warren * version 2, as published by the Free Software Foundation. 9be944d42SStephen Warren * 10be944d42SStephen Warren * This program is distributed in the hope it will be useful, but WITHOUT 11be944d42SStephen Warren * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12be944d42SStephen Warren * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13be944d42SStephen Warren * more details. 14be944d42SStephen Warren * 15be944d42SStephen Warren * You should have received a copy of the GNU General Public License 16be944d42SStephen Warren * along with this program. If not, see <http://www.gnu.org/licenses/>. 17be944d42SStephen Warren */ 18be944d42SStephen Warren 19be944d42SStephen Warren #ifndef __TEGRA30_AHUB_H__ 20be944d42SStephen Warren #define __TEGRA30_AHUB_H__ 21be944d42SStephen Warren 22be944d42SStephen Warren /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ 23be944d42SStephen Warren 24be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 25be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf 26be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) 27be944d42SStephen Warren 28be944d42SStephen Warren /* Channel count minus 1 */ 29be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 30be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 31be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) 32be944d42SStephen Warren 33be944d42SStephen Warren /* Channel count minus 1 */ 34be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 35be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 36be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) 37be944d42SStephen Warren 38be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_4 0 39be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_8 1 40be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_12 2 41be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_16 3 42be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_20 4 43be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_24 5 44be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_28 6 45be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_32 7 46be944d42SStephen Warren 47be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 48be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 49be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 50be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 51be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 52be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 53be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 54be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 55be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 56be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 57be944d42SStephen Warren 58be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 59be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 60be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 61be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 62be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 63be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 64be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 65be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 66be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 67be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 68be944d42SStephen Warren 69be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 70be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 71be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2 72be944d42SStephen Warren 73be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6 74be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 75be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 76be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 77be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 78be944d42SStephen Warren 79be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0 80be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1 81be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2 82be944d42SStephen Warren 83be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 84be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 85be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 86be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 87be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 88be944d42SStephen Warren 89be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_REPLICATE 3 90be944d42SStephen Warren 91be944d42SStephen Warren #define TEGRA30_AUDIOCIF_DIRECTION_TX 0 92be944d42SStephen Warren #define TEGRA30_AUDIOCIF_DIRECTION_RX 1 93be944d42SStephen Warren 94be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2 95be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 96be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 97be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 98be944d42SStephen Warren 99be944d42SStephen Warren #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0 100be944d42SStephen Warren #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1 101be944d42SStephen Warren 102be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 103be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 104be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 105be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 106be944d42SStephen Warren 107be944d42SStephen Warren #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0 108be944d42SStephen Warren #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1 109be944d42SStephen Warren 110be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 111be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 112be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 113be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 114be944d42SStephen Warren 115be944d42SStephen Warren /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ 116be944d42SStephen Warren 117be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_CTRL */ 118be944d42SStephen Warren 119be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL 0x0 120be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20 121be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4 122be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31) 123be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30) 124be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29) 125be944d42SStephen Warren 126be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16 127be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff 128be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) 129be944d42SStephen Warren 130be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8 131be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff 132be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) 133be944d42SStephen Warren 134be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6) 135be944d42SStephen Warren 136be944d42SStephen Warren #define TEGRA30_PACK_8_4 2 137be944d42SStephen Warren #define TEGRA30_PACK_16 3 138be944d42SStephen Warren 139be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4 140be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3 141be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 142be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 143be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 144be944d42SStephen Warren 145be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2) 146be944d42SStephen Warren 147be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0 148be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3 149be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 150be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 151be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 152be944d42SStephen Warren 153be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_CLEAR */ 154be944d42SStephen Warren 155be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4 156be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20 157be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4 158be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31) 159be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30) 160be944d42SStephen Warren 161be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_STATUS */ 162be944d42SStephen Warren 163be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS 0x8 164be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20 165be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4 166be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24 167be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff 168be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT) 169be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16 170be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff 171be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT) 172be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1) 173be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0) 174be944d42SStephen Warren 175be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_TXFIFO */ 176be944d42SStephen Warren 177be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc 178be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20 179be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4 180be944d42SStephen Warren 181be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_RXFIFO */ 182be944d42SStephen Warren 183be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10 184be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20 185be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4 186be944d42SStephen Warren 187be944d42SStephen Warren /* TEGRA30_AHUB_CIF_TX_CTRL */ 188be944d42SStephen Warren 189be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL 0x14 190be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20 191be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4 192be944d42SStephen Warren /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ 193be944d42SStephen Warren 194be944d42SStephen Warren /* TEGRA30_AHUB_CIF_RX_CTRL */ 195be944d42SStephen Warren 196be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL 0x18 197be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20 198be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4 199be944d42SStephen Warren /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ 200be944d42SStephen Warren 201be944d42SStephen Warren /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ 202be944d42SStephen Warren 203be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80 204be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28 205be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf 206be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT) 207be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16 208be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff 209be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT) 210be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4 211be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff 212be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT) 213be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2) 214be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1) 215be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0) 216be944d42SStephen Warren 217be944d42SStephen Warren /* TEGRA30_AHUB_MISC_CTRL */ 218be944d42SStephen Warren 219be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL 0x84 220be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31) 221be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8) 222be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0 223be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT) 224be944d42SStephen Warren 225be944d42SStephen Warren /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ 226be944d42SStephen Warren 227be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88 228be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31) 229be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30) 230be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29) 231be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28) 232be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27) 233be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26) 234be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25) 235be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24) 236be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23) 237be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22) 238be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21) 239be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20) 240be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19) 241be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18) 242be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17) 243be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16) 244be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15) 245be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14) 246be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13) 247be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12) 248be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11) 249be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10) 250be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9) 251be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8) 252be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7) 253be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6) 254be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5) 255be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4) 256be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3) 257be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2) 258be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1) 259be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0) 260be944d42SStephen Warren 261be944d42SStephen Warren /* TEGRA30_AHUB_I2S_LIVE_STATUS */ 262be944d42SStephen Warren 263be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c 264be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29) 265be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28) 266be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27) 267be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26) 268be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25) 269be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24) 270be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23) 271be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22) 272be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21) 273be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20) 274be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19) 275be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18) 276be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17) 277be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16) 278be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15) 279be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14) 280be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13) 281be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12) 282be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11) 283be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10) 284be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9) 285be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8) 286be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7) 287be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6) 288be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5) 289be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4) 290be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3) 291be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2) 292be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1) 293be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0) 294be944d42SStephen Warren 295be944d42SStephen Warren /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ 296be944d42SStephen Warren 297be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90 298be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8 299be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3 300be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26) 301be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25) 302be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24) 303be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15) 304be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9) 305be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8) 306be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7) 307be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1) 308be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0) 309be944d42SStephen Warren 310be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ 311be944d42SStephen Warren 312be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8 313be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11) 314be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) 315be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) 316be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) 317be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) 318be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) 319be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) 320be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) 321be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) 322be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) 323be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) 324be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) 325be944d42SStephen Warren 326be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_MASK */ 327be944d42SStephen Warren 328be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 329be944d42SStephen Warren 330be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_MASK */ 331be944d42SStephen Warren 332be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 333be944d42SStephen Warren 334be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_MASK */ 335be944d42SStephen Warren 336be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc 337be944d42SStephen Warren 338be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_MASK */ 339be944d42SStephen Warren 340be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 341be944d42SStephen Warren 342be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_STATUS */ 343be944d42SStephen Warren 344be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 345be944d42SStephen Warren 346be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_STATUS */ 347be944d42SStephen Warren 348be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc 349be944d42SStephen Warren 350be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_STATUS */ 351be944d42SStephen Warren 352be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 353be944d42SStephen Warren 354be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_STATUS */ 355be944d42SStephen Warren 356be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 357be944d42SStephen Warren 358be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_SOURCE */ 359be944d42SStephen Warren 360be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 361be944d42SStephen Warren 362be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_SOURCE */ 363be944d42SStephen Warren 364be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 365be944d42SStephen Warren 366be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ 367be944d42SStephen Warren 368be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec 369be944d42SStephen Warren 370be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_SOURCE */ 371be944d42SStephen Warren 372be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 373be944d42SStephen Warren 374be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_SET */ 375be944d42SStephen Warren 376be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_SET 0xf8 377be944d42SStephen Warren 378be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_SET */ 379be944d42SStephen Warren 380be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_SET 0xfc 381be944d42SStephen Warren 382be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_SET */ 383be944d42SStephen Warren 384be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 385be944d42SStephen Warren 386be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_SET */ 387be944d42SStephen Warren 388be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_SET 0x104 389be944d42SStephen Warren 390be944d42SStephen Warren /* Registers within TEGRA30_AHUB_BASE */ 391be944d42SStephen Warren 392be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX 0x0 393be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 394be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 395be944d42SStephen Warren /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ 396be944d42SStephen Warren /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ 397be944d42SStephen Warren 398be944d42SStephen Warren /* 399be944d42SStephen Warren * Terminology: 400be944d42SStephen Warren * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, 401be944d42SStephen Warren * I2S controllers, SPDIF controllers, and DAMs. 402be944d42SStephen Warren * XBAR: The core cross-bar component of the AHUB. 403be944d42SStephen Warren * CIF: Client Interface; the HW module connecting an audio device to the 404be944d42SStephen Warren * XBAR. 405be944d42SStephen Warren * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, 406be944d42SStephen Warren * possibly including sample-rate conversion. 407be944d42SStephen Warren * 408be944d42SStephen Warren * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio 409be944d42SStephen Warren * transmitted by a particular TX CIF. 410be944d42SStephen Warren * 411be944d42SStephen Warren * This driver is currently very simplistic; many HW features are not 412be944d42SStephen Warren * exposed; DAMs are not supported, only 16-bit stereo audio is supported, 413be944d42SStephen Warren * etc. 414be944d42SStephen Warren */ 415be944d42SStephen Warren 416be944d42SStephen Warren enum tegra30_ahub_txcif { 417be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX0, 418be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX1, 419be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX2, 420be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX3, 421be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S0_TX0, 422be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S1_TX0, 423be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S2_TX0, 424be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S3_TX0, 425be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S4_TX0, 426be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM0_TX0, 427be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM1_TX0, 428be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM2_TX0, 429be944d42SStephen Warren TEGRA30_AHUB_TXCIF_SPDIF_TX0, 430be944d42SStephen Warren TEGRA30_AHUB_TXCIF_SPDIF_TX1, 431be944d42SStephen Warren }; 432be944d42SStephen Warren 433be944d42SStephen Warren enum tegra30_ahub_rxcif { 434be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX0, 435be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX1, 436be944d42SStephen Warren TEGRA30_AHUB_RXcIF_APBIF_RX2, 437be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX3, 438be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S0_RX0, 439be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S1_RX0, 440be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S2_RX0, 441be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S3_RX0, 442be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S4_RX0, 443be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM0_RX0, 444be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM0_RX1, 445be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM1_RX0, 446be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM2_RX1, 447be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM3_RX0, 448be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM3_RX1, 449be944d42SStephen Warren TEGRA30_AHUB_RXCIF_SPDIF_RX0, 450be944d42SStephen Warren TEGRA30_AHUB_RXCIF_SPDIF_RX1, 451be944d42SStephen Warren }; 452be944d42SStephen Warren 453be944d42SStephen Warren extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 454be944d42SStephen Warren unsigned long *fiforeg, 455be944d42SStephen Warren unsigned long *reqsel); 456be944d42SStephen Warren extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 457be944d42SStephen Warren extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 458be944d42SStephen Warren extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); 459be944d42SStephen Warren 460be944d42SStephen Warren extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 461be944d42SStephen Warren unsigned long *fiforeg, 462be944d42SStephen Warren unsigned long *reqsel); 463be944d42SStephen Warren extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); 464be944d42SStephen Warren extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); 465be944d42SStephen Warren extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); 466be944d42SStephen Warren 467be944d42SStephen Warren extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, 468be944d42SStephen Warren enum tegra30_ahub_txcif txcif); 469be944d42SStephen Warren extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); 470be944d42SStephen Warren 47195d36075SStephen Warren struct tegra30_ahub_soc_data { 47295d36075SStephen Warren u32 clk_list_mask; 47395d36075SStephen Warren /* 47495d36075SStephen Warren * FIXME: There are many more differences in HW, such as: 47595d36075SStephen Warren * - More APBIF channels. 47695d36075SStephen Warren * - Extra separate chunks of register address space to represent 47795d36075SStephen Warren * the extra APBIF channels. 47895d36075SStephen Warren * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif 47995d36075SStephen Warren * need expansion, coupled with there being more defined bits in 48095d36075SStephen Warren * the AHUB routing registers. 48195d36075SStephen Warren * However, the driver doesn't support those new features yet, so we 48295d36075SStephen Warren * don't represent them here yet. 48395d36075SStephen Warren */ 48495d36075SStephen Warren }; 48595d36075SStephen Warren 486be944d42SStephen Warren struct tegra30_ahub { 48795d36075SStephen Warren const struct tegra30_ahub_soc_data *soc_data; 488be944d42SStephen Warren struct device *dev; 489be944d42SStephen Warren struct clk *clk_d_audio; 490be944d42SStephen Warren struct clk *clk_apbif; 491be944d42SStephen Warren int dma_sel; 492be944d42SStephen Warren resource_size_t apbif_addr; 493be944d42SStephen Warren struct regmap *regmap_apbif; 494be944d42SStephen Warren struct regmap *regmap_ahub; 495be944d42SStephen Warren DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 496be944d42SStephen Warren DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 497be944d42SStephen Warren }; 498be944d42SStephen Warren 499be944d42SStephen Warren #endif 500