1be944d42SStephen Warren /* 2be944d42SStephen Warren * tegra30_ahub.h - Definitions for Tegra30 AHUB driver 3be944d42SStephen Warren * 4be944d42SStephen Warren * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 5be944d42SStephen Warren * 6be944d42SStephen Warren * This program is free software; you can redistribute it and/or modify it 7be944d42SStephen Warren * under the terms and conditions of the GNU General Public License, 8be944d42SStephen Warren * version 2, as published by the Free Software Foundation. 9be944d42SStephen Warren * 10be944d42SStephen Warren * This program is distributed in the hope it will be useful, but WITHOUT 11be944d42SStephen Warren * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12be944d42SStephen Warren * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13be944d42SStephen Warren * more details. 14be944d42SStephen Warren * 15be944d42SStephen Warren * You should have received a copy of the GNU General Public License 16be944d42SStephen Warren * along with this program. If not, see <http://www.gnu.org/licenses/>. 17be944d42SStephen Warren */ 18be944d42SStephen Warren 19be944d42SStephen Warren #ifndef __TEGRA30_AHUB_H__ 20be944d42SStephen Warren #define __TEGRA30_AHUB_H__ 21be944d42SStephen Warren 22be944d42SStephen Warren /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ 23be944d42SStephen Warren 24be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 25be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf 26be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) 27be944d42SStephen Warren 285e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24 295e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f 305e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) 315e049fceSStephen Warren 32be944d42SStephen Warren /* Channel count minus 1 */ 33be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 34be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 35be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) 36be944d42SStephen Warren 37be944d42SStephen Warren /* Channel count minus 1 */ 385e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20 395e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf 405e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) 415e049fceSStephen Warren 425e049fceSStephen Warren /* Channel count minus 1 */ 43be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 44be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 45be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) 46be944d42SStephen Warren 475e049fceSStephen Warren /* Channel count minus 1 */ 485e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 495e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf 505e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) 515e049fceSStephen Warren 52be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_4 0 53be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_8 1 54be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_12 2 55be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_16 3 56be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_20 4 57be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_24 5 58be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_28 6 59be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_32 7 60be944d42SStephen Warren 61be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 62be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 63be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 64be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 65be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 66be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 67be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 68be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 69be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 70be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 71be944d42SStephen Warren 72be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 73be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 74be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 75be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 76be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 77be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 78be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 79be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 80be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 81be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 82be944d42SStephen Warren 83be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 84be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 85be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2 86be944d42SStephen Warren 87be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6 88be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 89be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 90be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 91be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 92be944d42SStephen Warren 93be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0 94be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1 95be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2 96be944d42SStephen Warren 97be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 98be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 99be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 100be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 101be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 102be944d42SStephen Warren 1035e049fceSStephen Warren #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT 3 104be944d42SStephen Warren 105be944d42SStephen Warren #define TEGRA30_AUDIOCIF_DIRECTION_TX 0 106be944d42SStephen Warren #define TEGRA30_AUDIOCIF_DIRECTION_RX 1 107be944d42SStephen Warren 108be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2 109be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 110be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 111be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 112be944d42SStephen Warren 113be944d42SStephen Warren #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0 114be944d42SStephen Warren #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1 115be944d42SStephen Warren 116be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 117be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 118be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 119be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 120be944d42SStephen Warren 121be944d42SStephen Warren #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0 122be944d42SStephen Warren #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1 123be944d42SStephen Warren 124be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 125be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 126be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 127be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 128be944d42SStephen Warren 129be944d42SStephen Warren /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ 130be944d42SStephen Warren 131be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_CTRL */ 132be944d42SStephen Warren 133be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL 0x0 134be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20 135be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4 136be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31) 137be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30) 138be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29) 139be944d42SStephen Warren 140be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16 141be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff 142be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) 143be944d42SStephen Warren 144be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8 145be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff 146be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) 147be944d42SStephen Warren 148be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6) 149be944d42SStephen Warren 150be944d42SStephen Warren #define TEGRA30_PACK_8_4 2 151be944d42SStephen Warren #define TEGRA30_PACK_16 3 152be944d42SStephen Warren 153be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4 154be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3 155be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 156be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 157be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 158be944d42SStephen Warren 159be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2) 160be944d42SStephen Warren 161be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0 162be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3 163be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 164be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 165be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 166be944d42SStephen Warren 167be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_CLEAR */ 168be944d42SStephen Warren 169be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4 170be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20 171be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4 172be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31) 173be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30) 174be944d42SStephen Warren 175be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_STATUS */ 176be944d42SStephen Warren 177be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS 0x8 178be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20 179be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4 180be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24 181be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff 182be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT) 183be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16 184be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff 185be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT) 186be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1) 187be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0) 188be944d42SStephen Warren 189be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_TXFIFO */ 190be944d42SStephen Warren 191be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc 192be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20 193be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4 194be944d42SStephen Warren 195be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_RXFIFO */ 196be944d42SStephen Warren 197be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10 198be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20 199be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4 200be944d42SStephen Warren 201be944d42SStephen Warren /* TEGRA30_AHUB_CIF_TX_CTRL */ 202be944d42SStephen Warren 203be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL 0x14 204be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20 205be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4 206be944d42SStephen Warren /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ 207be944d42SStephen Warren 208be944d42SStephen Warren /* TEGRA30_AHUB_CIF_RX_CTRL */ 209be944d42SStephen Warren 210be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL 0x18 211be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20 212be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4 213be944d42SStephen Warren /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ 214be944d42SStephen Warren 215be944d42SStephen Warren /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ 216be944d42SStephen Warren 217be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80 218be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28 219be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf 220be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT) 221be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16 222be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff 223be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT) 224be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4 225be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff 226be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT) 227be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2) 228be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1) 229be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0) 230be944d42SStephen Warren 231be944d42SStephen Warren /* TEGRA30_AHUB_MISC_CTRL */ 232be944d42SStephen Warren 233be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL 0x84 234be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31) 235be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8) 236be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0 237be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT) 238be944d42SStephen Warren 239be944d42SStephen Warren /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ 240be944d42SStephen Warren 241be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88 242be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31) 243be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30) 244be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29) 245be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28) 246be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27) 247be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26) 248be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25) 249be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24) 250be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23) 251be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22) 252be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21) 253be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20) 254be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19) 255be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18) 256be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17) 257be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16) 258be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15) 259be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14) 260be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13) 261be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12) 262be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11) 263be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10) 264be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9) 265be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8) 266be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7) 267be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6) 268be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5) 269be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4) 270be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3) 271be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2) 272be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1) 273be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0) 274be944d42SStephen Warren 275be944d42SStephen Warren /* TEGRA30_AHUB_I2S_LIVE_STATUS */ 276be944d42SStephen Warren 277be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c 278be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29) 279be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28) 280be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27) 281be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26) 282be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25) 283be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24) 284be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23) 285be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22) 286be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21) 287be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20) 288be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19) 289be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18) 290be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17) 291be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16) 292be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15) 293be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14) 294be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13) 295be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12) 296be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11) 297be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10) 298be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9) 299be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8) 300be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7) 301be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6) 302be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5) 303be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4) 304be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3) 305be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2) 306be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1) 307be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0) 308be944d42SStephen Warren 309be944d42SStephen Warren /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ 310be944d42SStephen Warren 311be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90 312be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8 313be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3 314be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26) 315be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25) 316be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24) 317be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15) 318be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9) 319be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8) 320be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7) 321be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1) 322be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0) 323be944d42SStephen Warren 324be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ 325be944d42SStephen Warren 326be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8 327be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11) 328be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) 329be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) 330be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) 331be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) 332be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) 333be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) 334be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) 335be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) 336be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) 337be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) 338be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) 339be944d42SStephen Warren 340be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_MASK */ 341be944d42SStephen Warren 342be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 343be944d42SStephen Warren 344be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_MASK */ 345be944d42SStephen Warren 346be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 347be944d42SStephen Warren 348be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_MASK */ 349be944d42SStephen Warren 350be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc 351be944d42SStephen Warren 352be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_MASK */ 353be944d42SStephen Warren 354be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 355be944d42SStephen Warren 356be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_STATUS */ 357be944d42SStephen Warren 358be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 359be944d42SStephen Warren 360be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_STATUS */ 361be944d42SStephen Warren 362be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc 363be944d42SStephen Warren 364be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_STATUS */ 365be944d42SStephen Warren 366be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 367be944d42SStephen Warren 368be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_STATUS */ 369be944d42SStephen Warren 370be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 371be944d42SStephen Warren 372be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_SOURCE */ 373be944d42SStephen Warren 374be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 375be944d42SStephen Warren 376be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_SOURCE */ 377be944d42SStephen Warren 378be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 379be944d42SStephen Warren 380be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ 381be944d42SStephen Warren 382be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec 383be944d42SStephen Warren 384be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_SOURCE */ 385be944d42SStephen Warren 386be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 387be944d42SStephen Warren 388be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_SET */ 389be944d42SStephen Warren 390be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_SET 0xf8 391be944d42SStephen Warren 392be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_SET */ 393be944d42SStephen Warren 394be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_SET 0xfc 395be944d42SStephen Warren 396be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_SET */ 397be944d42SStephen Warren 398be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 399be944d42SStephen Warren 400be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_SET */ 401be944d42SStephen Warren 402be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_SET 0x104 403be944d42SStephen Warren 404be944d42SStephen Warren /* Registers within TEGRA30_AHUB_BASE */ 405be944d42SStephen Warren 406be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX 0x0 407be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 408be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 409be944d42SStephen Warren /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ 410be944d42SStephen Warren /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ 411be944d42SStephen Warren 412be944d42SStephen Warren /* 413be944d42SStephen Warren * Terminology: 414be944d42SStephen Warren * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, 415be944d42SStephen Warren * I2S controllers, SPDIF controllers, and DAMs. 416be944d42SStephen Warren * XBAR: The core cross-bar component of the AHUB. 417be944d42SStephen Warren * CIF: Client Interface; the HW module connecting an audio device to the 418be944d42SStephen Warren * XBAR. 419be944d42SStephen Warren * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, 420be944d42SStephen Warren * possibly including sample-rate conversion. 421be944d42SStephen Warren * 422be944d42SStephen Warren * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio 423be944d42SStephen Warren * transmitted by a particular TX CIF. 424be944d42SStephen Warren * 425be944d42SStephen Warren * This driver is currently very simplistic; many HW features are not 426be944d42SStephen Warren * exposed; DAMs are not supported, only 16-bit stereo audio is supported, 427be944d42SStephen Warren * etc. 428be944d42SStephen Warren */ 429be944d42SStephen Warren 430be944d42SStephen Warren enum tegra30_ahub_txcif { 431be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX0, 432be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX1, 433be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX2, 434be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX3, 435be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S0_TX0, 436be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S1_TX0, 437be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S2_TX0, 438be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S3_TX0, 439be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S4_TX0, 440be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM0_TX0, 441be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM1_TX0, 442be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM2_TX0, 443be944d42SStephen Warren TEGRA30_AHUB_TXCIF_SPDIF_TX0, 444be944d42SStephen Warren TEGRA30_AHUB_TXCIF_SPDIF_TX1, 445be944d42SStephen Warren }; 446be944d42SStephen Warren 447be944d42SStephen Warren enum tegra30_ahub_rxcif { 448be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX0, 449be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX1, 450be944d42SStephen Warren TEGRA30_AHUB_RXcIF_APBIF_RX2, 451be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX3, 452be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S0_RX0, 453be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S1_RX0, 454be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S2_RX0, 455be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S3_RX0, 456be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S4_RX0, 457be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM0_RX0, 458be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM0_RX1, 459be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM1_RX0, 460be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM2_RX1, 461be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM3_RX0, 462be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM3_RX1, 463be944d42SStephen Warren TEGRA30_AHUB_RXCIF_SPDIF_RX0, 464be944d42SStephen Warren TEGRA30_AHUB_RXCIF_SPDIF_RX1, 465be944d42SStephen Warren }; 466be944d42SStephen Warren 467be944d42SStephen Warren extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 4683489d506SLars-Peter Clausen dma_addr_t *fiforeg, 4693489d506SLars-Peter Clausen unsigned int *reqsel); 470be944d42SStephen Warren extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 471be944d42SStephen Warren extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 472be944d42SStephen Warren extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); 473be944d42SStephen Warren 474be944d42SStephen Warren extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 4753489d506SLars-Peter Clausen dma_addr_t *fiforeg, 4763489d506SLars-Peter Clausen unsigned int *reqsel); 477be944d42SStephen Warren extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); 478be944d42SStephen Warren extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); 479be944d42SStephen Warren extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); 480be944d42SStephen Warren 481be944d42SStephen Warren extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, 482be944d42SStephen Warren enum tegra30_ahub_txcif txcif); 483be944d42SStephen Warren extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); 484be944d42SStephen Warren 4855e049fceSStephen Warren struct tegra30_ahub_cif_conf { 4865e049fceSStephen Warren unsigned int threshold; 4875e049fceSStephen Warren unsigned int audio_channels; 4885e049fceSStephen Warren unsigned int client_channels; 4895e049fceSStephen Warren unsigned int audio_bits; 4905e049fceSStephen Warren unsigned int client_bits; 4915e049fceSStephen Warren unsigned int expand; 4925e049fceSStephen Warren unsigned int stereo_conv; 4935e049fceSStephen Warren unsigned int replicate; 4945e049fceSStephen Warren unsigned int direction; 4955e049fceSStephen Warren unsigned int truncate; 4965e049fceSStephen Warren unsigned int mono_conv; 4975e049fceSStephen Warren }; 4985e049fceSStephen Warren 4995e049fceSStephen Warren void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, 5005e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf); 5015e049fceSStephen Warren void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, 5025e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf); 5035e049fceSStephen Warren 50495d36075SStephen Warren struct tegra30_ahub_soc_data { 50595d36075SStephen Warren u32 clk_list_mask; 5065e049fceSStephen Warren void (*set_audio_cif)(struct regmap *regmap, 5075e049fceSStephen Warren unsigned int reg, 5085e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf); 50995d36075SStephen Warren /* 51095d36075SStephen Warren * FIXME: There are many more differences in HW, such as: 51195d36075SStephen Warren * - More APBIF channels. 51295d36075SStephen Warren * - Extra separate chunks of register address space to represent 51395d36075SStephen Warren * the extra APBIF channels. 51495d36075SStephen Warren * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif 51595d36075SStephen Warren * need expansion, coupled with there being more defined bits in 51695d36075SStephen Warren * the AHUB routing registers. 51795d36075SStephen Warren * However, the driver doesn't support those new features yet, so we 51895d36075SStephen Warren * don't represent them here yet. 51995d36075SStephen Warren */ 52095d36075SStephen Warren }; 52195d36075SStephen Warren 522be944d42SStephen Warren struct tegra30_ahub { 52395d36075SStephen Warren const struct tegra30_ahub_soc_data *soc_data; 524be944d42SStephen Warren struct device *dev; 525be944d42SStephen Warren struct clk *clk_d_audio; 526be944d42SStephen Warren struct clk *clk_apbif; 527be944d42SStephen Warren int dma_sel; 528be944d42SStephen Warren resource_size_t apbif_addr; 529be944d42SStephen Warren struct regmap *regmap_apbif; 530be944d42SStephen Warren struct regmap *regmap_ahub; 531be944d42SStephen Warren DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 532be944d42SStephen Warren DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 533be944d42SStephen Warren }; 534be944d42SStephen Warren 535be944d42SStephen Warren #endif 536