19952f691SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2be944d42SStephen Warren /* 3be944d42SStephen Warren * tegra30_ahub.h - Definitions for Tegra30 AHUB driver 4be944d42SStephen Warren * 5be944d42SStephen Warren * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 6be944d42SStephen Warren */ 7be944d42SStephen Warren 8be944d42SStephen Warren #ifndef __TEGRA30_AHUB_H__ 9be944d42SStephen Warren #define __TEGRA30_AHUB_H__ 10be944d42SStephen Warren 11be944d42SStephen Warren /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ 12be944d42SStephen Warren 13be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 14be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf 15be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) 16be944d42SStephen Warren 175e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24 185e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f 195e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) 205e049fceSStephen Warren 21be944d42SStephen Warren /* Channel count minus 1 */ 22be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 23be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 24be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) 25be944d42SStephen Warren 26be944d42SStephen Warren /* Channel count minus 1 */ 275e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20 285e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf 295e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) 305e049fceSStephen Warren 315e049fceSStephen Warren /* Channel count minus 1 */ 32be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 33be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 34be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) 35be944d42SStephen Warren 365e049fceSStephen Warren /* Channel count minus 1 */ 375e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 385e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf 395e049fceSStephen Warren #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) 405e049fceSStephen Warren 41be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_4 0 42be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_8 1 43be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_12 2 44be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_16 3 45be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_20 4 46be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_24 5 47be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_28 6 48be944d42SStephen Warren #define TEGRA30_AUDIOCIF_BITS_32 7 49be944d42SStephen Warren 50be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 51be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 52be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 53be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 54be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 55be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 56be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 57be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 58be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 59be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) 60be944d42SStephen Warren 61be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 62be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 63be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 64be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 65be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 66be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 67be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 68be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 69be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 70be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) 71be944d42SStephen Warren 72be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 73be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 74be944d42SStephen Warren #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2 75be944d42SStephen Warren 76be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6 77be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 78be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 79be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 80be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) 81be944d42SStephen Warren 82be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0 83be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1 84be944d42SStephen Warren #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2 85be944d42SStephen Warren 86be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 87be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 88be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 89be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 90be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) 91be944d42SStephen Warren 925e049fceSStephen Warren #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT 3 93be944d42SStephen Warren 94be944d42SStephen Warren #define TEGRA30_AUDIOCIF_DIRECTION_TX 0 95be944d42SStephen Warren #define TEGRA30_AUDIOCIF_DIRECTION_RX 1 96be944d42SStephen Warren 97be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2 98be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 99be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 100be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) 101be944d42SStephen Warren 102be944d42SStephen Warren #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0 103be944d42SStephen Warren #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1 104be944d42SStephen Warren 105be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 106be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 107be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 108be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) 109be944d42SStephen Warren 110be944d42SStephen Warren #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0 111be944d42SStephen Warren #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1 112be944d42SStephen Warren 113be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 114be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 115be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 116be944d42SStephen Warren #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) 117be944d42SStephen Warren 118be944d42SStephen Warren /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ 119be944d42SStephen Warren 120be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_CTRL */ 121be944d42SStephen Warren 122be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL 0x0 123be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20 124be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4 125be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31) 126be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30) 127be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29) 128be944d42SStephen Warren 129be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16 130be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff 131be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) 132be944d42SStephen Warren 133be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8 134be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff 135be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) 136be944d42SStephen Warren 137be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6) 138be944d42SStephen Warren 139be944d42SStephen Warren #define TEGRA30_PACK_8_4 2 140be944d42SStephen Warren #define TEGRA30_PACK_16 3 141be944d42SStephen Warren 142be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4 143be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3 144be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 145be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 146be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) 147be944d42SStephen Warren 148be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2) 149be944d42SStephen Warren 150be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0 151be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3 152be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 153be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 154be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) 155be944d42SStephen Warren 156be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_CLEAR */ 157be944d42SStephen Warren 158be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4 159be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20 160be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4 161be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31) 162be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30) 163be944d42SStephen Warren 164be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_STATUS */ 165be944d42SStephen Warren 166be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS 0x8 167be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20 168be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4 169be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24 170be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff 171be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT) 172be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16 173be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff 174be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT) 175be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1) 176be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0) 177be944d42SStephen Warren 178be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_TXFIFO */ 179be944d42SStephen Warren 180be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc 181be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20 182be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4 183be944d42SStephen Warren 184be944d42SStephen Warren /* TEGRA30_AHUB_CHANNEL_RXFIFO */ 185be944d42SStephen Warren 186be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10 187be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20 188be944d42SStephen Warren #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4 189be944d42SStephen Warren 190be944d42SStephen Warren /* TEGRA30_AHUB_CIF_TX_CTRL */ 191be944d42SStephen Warren 192be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL 0x14 193be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20 194be944d42SStephen Warren #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4 195be944d42SStephen Warren /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ 196be944d42SStephen Warren 197be944d42SStephen Warren /* TEGRA30_AHUB_CIF_RX_CTRL */ 198be944d42SStephen Warren 199be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL 0x18 200be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20 201be944d42SStephen Warren #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4 202be944d42SStephen Warren /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ 203be944d42SStephen Warren 204be944d42SStephen Warren /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ 205be944d42SStephen Warren 206be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80 207be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28 208be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf 209be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT) 210be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16 211be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff 212be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT) 213be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4 214be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff 215be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT) 216be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2) 217be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1) 218be944d42SStephen Warren #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0) 219be944d42SStephen Warren 220be944d42SStephen Warren /* TEGRA30_AHUB_MISC_CTRL */ 221be944d42SStephen Warren 222be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL 0x84 223be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31) 224be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8) 225be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0 226be944d42SStephen Warren #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT) 227be944d42SStephen Warren 228be944d42SStephen Warren /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ 229be944d42SStephen Warren 230be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88 231be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31) 232be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30) 233be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29) 234be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28) 235be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27) 236be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26) 237be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25) 238be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24) 239be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23) 240be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22) 241be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21) 242be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20) 243be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19) 244be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18) 245be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17) 246be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16) 247be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15) 248be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14) 249be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13) 250be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12) 251be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11) 252be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10) 253be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9) 254be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8) 255be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7) 256be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6) 257be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5) 258be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4) 259be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3) 260be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2) 261be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1) 262be944d42SStephen Warren #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0) 263be944d42SStephen Warren 264be944d42SStephen Warren /* TEGRA30_AHUB_I2S_LIVE_STATUS */ 265be944d42SStephen Warren 266be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c 267be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29) 268be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28) 269be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27) 270be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26) 271be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25) 272be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24) 273be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23) 274be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22) 275be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21) 276be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20) 277be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19) 278be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18) 279be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17) 280be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16) 281be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15) 282be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14) 283be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13) 284be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12) 285be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11) 286be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10) 287be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9) 288be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8) 289be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7) 290be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6) 291be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5) 292be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4) 293be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3) 294be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2) 295be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1) 296be944d42SStephen Warren #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0) 297be944d42SStephen Warren 298be944d42SStephen Warren /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ 299be944d42SStephen Warren 300be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90 301be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8 302be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3 303be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26) 304be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25) 305be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24) 306be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15) 307be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9) 308be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8) 309be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7) 310be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1) 311be944d42SStephen Warren #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0) 312be944d42SStephen Warren 313be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ 314be944d42SStephen Warren 315be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8 316be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11) 317be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) 318be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) 319be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) 320be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) 321be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) 322be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) 323be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) 324be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) 325be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) 326be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) 327be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) 328be944d42SStephen Warren 329be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_MASK */ 330be944d42SStephen Warren 331be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 332be944d42SStephen Warren 333be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_MASK */ 334be944d42SStephen Warren 335be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 336be944d42SStephen Warren 337be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_MASK */ 338be944d42SStephen Warren 339be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc 340be944d42SStephen Warren 341be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_MASK */ 342be944d42SStephen Warren 343be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 344be944d42SStephen Warren 345be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_STATUS */ 346be944d42SStephen Warren 347be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 348be944d42SStephen Warren 349be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_STATUS */ 350be944d42SStephen Warren 351be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc 352be944d42SStephen Warren 353be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_STATUS */ 354be944d42SStephen Warren 355be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 356be944d42SStephen Warren 357be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_STATUS */ 358be944d42SStephen Warren 359be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 360be944d42SStephen Warren 361be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_SOURCE */ 362be944d42SStephen Warren 363be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 364be944d42SStephen Warren 365be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_SOURCE */ 366be944d42SStephen Warren 367be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 368be944d42SStephen Warren 369be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ 370be944d42SStephen Warren 371be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec 372be944d42SStephen Warren 373be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_SOURCE */ 374be944d42SStephen Warren 375be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 376be944d42SStephen Warren 377be944d42SStephen Warren /* TEGRA30_AHUB_I2S_INT_SET */ 378be944d42SStephen Warren 379be944d42SStephen Warren #define TEGRA30_AHUB_I2S_INT_SET 0xf8 380be944d42SStephen Warren 381be944d42SStephen Warren /* TEGRA30_AHUB_DAM_INT_SET */ 382be944d42SStephen Warren 383be944d42SStephen Warren #define TEGRA30_AHUB_DAM_INT_SET 0xfc 384be944d42SStephen Warren 385be944d42SStephen Warren /* TEGRA30_AHUB_SPDIF_INT_SET */ 386be944d42SStephen Warren 387be944d42SStephen Warren #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 388be944d42SStephen Warren 389be944d42SStephen Warren /* TEGRA30_AHUB_APBIF_INT_SET */ 390be944d42SStephen Warren 391be944d42SStephen Warren #define TEGRA30_AHUB_APBIF_INT_SET 0x104 392be944d42SStephen Warren 393be944d42SStephen Warren /* Registers within TEGRA30_AHUB_BASE */ 394be944d42SStephen Warren 395be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX 0x0 396be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 397be944d42SStephen Warren #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 398be944d42SStephen Warren /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ 399be944d42SStephen Warren /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ 400be944d42SStephen Warren 401be944d42SStephen Warren /* 402be944d42SStephen Warren * Terminology: 403be944d42SStephen Warren * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, 404be944d42SStephen Warren * I2S controllers, SPDIF controllers, and DAMs. 405be944d42SStephen Warren * XBAR: The core cross-bar component of the AHUB. 406be944d42SStephen Warren * CIF: Client Interface; the HW module connecting an audio device to the 407be944d42SStephen Warren * XBAR. 408be944d42SStephen Warren * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, 409be944d42SStephen Warren * possibly including sample-rate conversion. 410be944d42SStephen Warren * 411be944d42SStephen Warren * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio 412be944d42SStephen Warren * transmitted by a particular TX CIF. 413be944d42SStephen Warren * 414be944d42SStephen Warren * This driver is currently very simplistic; many HW features are not 415be944d42SStephen Warren * exposed; DAMs are not supported, only 16-bit stereo audio is supported, 416be944d42SStephen Warren * etc. 417be944d42SStephen Warren */ 418be944d42SStephen Warren 419be944d42SStephen Warren enum tegra30_ahub_txcif { 420be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX0, 421be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX1, 422be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX2, 423be944d42SStephen Warren TEGRA30_AHUB_TXCIF_APBIF_TX3, 424be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S0_TX0, 425be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S1_TX0, 426be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S2_TX0, 427be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S3_TX0, 428be944d42SStephen Warren TEGRA30_AHUB_TXCIF_I2S4_TX0, 429be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM0_TX0, 430be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM1_TX0, 431be944d42SStephen Warren TEGRA30_AHUB_TXCIF_DAM2_TX0, 432be944d42SStephen Warren TEGRA30_AHUB_TXCIF_SPDIF_TX0, 433be944d42SStephen Warren TEGRA30_AHUB_TXCIF_SPDIF_TX1, 434be944d42SStephen Warren }; 435be944d42SStephen Warren 436be944d42SStephen Warren enum tegra30_ahub_rxcif { 437be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX0, 438be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX1, 439be944d42SStephen Warren TEGRA30_AHUB_RXcIF_APBIF_RX2, 440be944d42SStephen Warren TEGRA30_AHUB_RXCIF_APBIF_RX3, 441be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S0_RX0, 442be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S1_RX0, 443be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S2_RX0, 444be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S3_RX0, 445be944d42SStephen Warren TEGRA30_AHUB_RXCIF_I2S4_RX0, 446be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM0_RX0, 447be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM0_RX1, 448be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM1_RX0, 449be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM2_RX1, 450be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM3_RX0, 451be944d42SStephen Warren TEGRA30_AHUB_RXCIF_DAM3_RX1, 452be944d42SStephen Warren TEGRA30_AHUB_RXCIF_SPDIF_RX0, 453be944d42SStephen Warren TEGRA30_AHUB_RXCIF_SPDIF_RX1, 454be944d42SStephen Warren }; 455be944d42SStephen Warren 456be944d42SStephen Warren extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 4575608bd3eSStephen Warren char *dmachan, int dmachan_len, 4585608bd3eSStephen Warren dma_addr_t *fiforeg); 459be944d42SStephen Warren extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 460be944d42SStephen Warren extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 461be944d42SStephen Warren extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); 462be944d42SStephen Warren 463be944d42SStephen Warren extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 4645608bd3eSStephen Warren char *dmachan, int dmachan_len, 4655608bd3eSStephen Warren dma_addr_t *fiforeg); 466be944d42SStephen Warren extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); 467be944d42SStephen Warren extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); 468be944d42SStephen Warren extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); 469be944d42SStephen Warren 470be944d42SStephen Warren extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, 471be944d42SStephen Warren enum tegra30_ahub_txcif txcif); 472be944d42SStephen Warren extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); 473be944d42SStephen Warren 4745e049fceSStephen Warren struct tegra30_ahub_cif_conf { 4755e049fceSStephen Warren unsigned int threshold; 4765e049fceSStephen Warren unsigned int audio_channels; 4775e049fceSStephen Warren unsigned int client_channels; 4785e049fceSStephen Warren unsigned int audio_bits; 4795e049fceSStephen Warren unsigned int client_bits; 4805e049fceSStephen Warren unsigned int expand; 4815e049fceSStephen Warren unsigned int stereo_conv; 4825e049fceSStephen Warren unsigned int replicate; 4835e049fceSStephen Warren unsigned int direction; 4845e049fceSStephen Warren unsigned int truncate; 4855e049fceSStephen Warren unsigned int mono_conv; 4865e049fceSStephen Warren }; 4875e049fceSStephen Warren 4885e049fceSStephen Warren void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, 4895e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf); 4905e049fceSStephen Warren void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, 4915e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf); 4925e049fceSStephen Warren 49395d36075SStephen Warren struct tegra30_ahub_soc_data { 494*050086ebSDmitry Osipenko unsigned int num_resets; 4955e049fceSStephen Warren void (*set_audio_cif)(struct regmap *regmap, 4965e049fceSStephen Warren unsigned int reg, 4975e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf); 49895d36075SStephen Warren /* 49995d36075SStephen Warren * FIXME: There are many more differences in HW, such as: 50095d36075SStephen Warren * - More APBIF channels. 50195d36075SStephen Warren * - Extra separate chunks of register address space to represent 50295d36075SStephen Warren * the extra APBIF channels. 50395d36075SStephen Warren * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif 50495d36075SStephen Warren * need expansion, coupled with there being more defined bits in 50595d36075SStephen Warren * the AHUB routing registers. 50695d36075SStephen Warren * However, the driver doesn't support those new features yet, so we 50795d36075SStephen Warren * don't represent them here yet. 50895d36075SStephen Warren */ 50995d36075SStephen Warren }; 51095d36075SStephen Warren 511be944d42SStephen Warren struct tegra30_ahub { 51295d36075SStephen Warren const struct tegra30_ahub_soc_data *soc_data; 513be944d42SStephen Warren struct device *dev; 514*050086ebSDmitry Osipenko struct reset_control_bulk_data resets[21]; 515*050086ebSDmitry Osipenko unsigned int nresets; 5166d8ac9b1SDmitry Osipenko struct clk_bulk_data clocks[2]; 5176d8ac9b1SDmitry Osipenko unsigned int nclocks; 518be944d42SStephen Warren resource_size_t apbif_addr; 519be944d42SStephen Warren struct regmap *regmap_apbif; 520be944d42SStephen Warren struct regmap *regmap_ahub; 521be944d42SStephen Warren DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 522be944d42SStephen Warren DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 523be944d42SStephen Warren }; 524be944d42SStephen Warren 525be944d42SStephen Warren #endif 526