19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2be944d42SStephen Warren /* 3be944d42SStephen Warren * tegra30_ahub.c - Tegra30 AHUB driver 4be944d42SStephen Warren * 5be944d42SStephen Warren * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 6be944d42SStephen Warren */ 7be944d42SStephen Warren 8be944d42SStephen Warren #include <linux/clk.h> 9be944d42SStephen Warren #include <linux/device.h> 10be944d42SStephen Warren #include <linux/io.h> 11be944d42SStephen Warren #include <linux/module.h> 12be944d42SStephen Warren #include <linux/of_platform.h> 13be944d42SStephen Warren #include <linux/platform_device.h> 14be944d42SStephen Warren #include <linux/pm_runtime.h> 15be944d42SStephen Warren #include <linux/regmap.h> 165185e0acSStephen Warren #include <linux/reset.h> 17be944d42SStephen Warren #include <linux/slab.h> 18be944d42SStephen Warren #include <sound/soc.h> 19be944d42SStephen Warren #include "tegra30_ahub.h" 20be944d42SStephen Warren 21be944d42SStephen Warren #define DRV_NAME "tegra30-ahub" 22be944d42SStephen Warren 23be944d42SStephen Warren static struct tegra30_ahub *ahub; 24be944d42SStephen Warren 25be944d42SStephen Warren static inline void tegra30_apbif_write(u32 reg, u32 val) 26be944d42SStephen Warren { 27be944d42SStephen Warren regmap_write(ahub->regmap_apbif, reg, val); 28be944d42SStephen Warren } 29be944d42SStephen Warren 30be944d42SStephen Warren static inline u32 tegra30_apbif_read(u32 reg) 31be944d42SStephen Warren { 32be944d42SStephen Warren u32 val; 33bf3c6ef7SCodrut Grosu 34be944d42SStephen Warren regmap_read(ahub->regmap_apbif, reg, &val); 35be944d42SStephen Warren return val; 36be944d42SStephen Warren } 37be944d42SStephen Warren 38be944d42SStephen Warren static inline void tegra30_audio_write(u32 reg, u32 val) 39be944d42SStephen Warren { 40be944d42SStephen Warren regmap_write(ahub->regmap_ahub, reg, val); 41be944d42SStephen Warren } 42be944d42SStephen Warren 43be944d42SStephen Warren static int tegra30_ahub_runtime_suspend(struct device *dev) 44be944d42SStephen Warren { 45be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, true); 46be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, true); 47be944d42SStephen Warren 486d8ac9b1SDmitry Osipenko clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks); 49be944d42SStephen Warren 50be944d42SStephen Warren return 0; 51be944d42SStephen Warren } 52be944d42SStephen Warren 53be944d42SStephen Warren /* 54be944d42SStephen Warren * clk_apbif isn't required for an I2S<->I2S configuration where no PCM data 55be944d42SStephen Warren * is read from or sent to memory. However, that's not something the rest of 56be944d42SStephen Warren * the driver supports right now, so we'll just treat the two clocks as one 57be944d42SStephen Warren * for now. 58be944d42SStephen Warren * 59be944d42SStephen Warren * These functions should not be a plain ref-count. Instead, each active stream 60be944d42SStephen Warren * contributes some requirement to the minimum clock rate, so starting or 61be944d42SStephen Warren * stopping streams should dynamically adjust the clock as required. However, 62be944d42SStephen Warren * this is not yet implemented. 63be944d42SStephen Warren */ 64be944d42SStephen Warren static int tegra30_ahub_runtime_resume(struct device *dev) 65be944d42SStephen Warren { 66be944d42SStephen Warren int ret; 67be944d42SStephen Warren 68*ed9ce1edSDmitry Osipenko ret = reset_control_assert(ahub->reset); 69*ed9ce1edSDmitry Osipenko if (ret) 70*ed9ce1edSDmitry Osipenko return ret; 71*ed9ce1edSDmitry Osipenko 726d8ac9b1SDmitry Osipenko ret = clk_bulk_prepare_enable(ahub->nclocks, ahub->clocks); 736d8ac9b1SDmitry Osipenko if (ret) 74be944d42SStephen Warren return ret; 75be944d42SStephen Warren 76*ed9ce1edSDmitry Osipenko usleep_range(10, 100); 77*ed9ce1edSDmitry Osipenko 78*ed9ce1edSDmitry Osipenko ret = reset_control_deassert(ahub->reset); 79*ed9ce1edSDmitry Osipenko if (ret) 80*ed9ce1edSDmitry Osipenko goto disable_clocks; 81*ed9ce1edSDmitry Osipenko 82be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, false); 83be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, false); 84*ed9ce1edSDmitry Osipenko regcache_mark_dirty(ahub->regmap_apbif); 85*ed9ce1edSDmitry Osipenko regcache_mark_dirty(ahub->regmap_ahub); 86*ed9ce1edSDmitry Osipenko 87*ed9ce1edSDmitry Osipenko ret = regcache_sync(ahub->regmap_apbif); 88*ed9ce1edSDmitry Osipenko if (ret) 89*ed9ce1edSDmitry Osipenko goto disable_clocks; 90*ed9ce1edSDmitry Osipenko 91*ed9ce1edSDmitry Osipenko ret = regcache_sync(ahub->regmap_ahub); 92*ed9ce1edSDmitry Osipenko if (ret) 93*ed9ce1edSDmitry Osipenko goto disable_clocks; 94be944d42SStephen Warren 95be944d42SStephen Warren return 0; 96*ed9ce1edSDmitry Osipenko 97*ed9ce1edSDmitry Osipenko disable_clocks: 98*ed9ce1edSDmitry Osipenko clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks); 99*ed9ce1edSDmitry Osipenko 100*ed9ce1edSDmitry Osipenko return ret; 101be944d42SStephen Warren } 102be944d42SStephen Warren 103be944d42SStephen Warren int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 1045608bd3eSStephen Warren char *dmachan, int dmachan_len, 1055608bd3eSStephen Warren dma_addr_t *fiforeg) 106be944d42SStephen Warren { 107be944d42SStephen Warren int channel; 108be944d42SStephen Warren u32 reg, val; 1095e049fceSStephen Warren struct tegra30_ahub_cif_conf cif_conf; 110be944d42SStephen Warren 111be944d42SStephen Warren channel = find_first_zero_bit(ahub->rx_usage, 112be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 113be944d42SStephen Warren if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) 114be944d42SStephen Warren return -EBUSY; 115be944d42SStephen Warren 116be944d42SStephen Warren __set_bit(channel, ahub->rx_usage); 117be944d42SStephen Warren 118be944d42SStephen Warren *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel; 1195608bd3eSStephen Warren snprintf(dmachan, dmachan_len, "rx%d", channel); 120be944d42SStephen Warren *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO + 121be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE); 122be944d42SStephen Warren 123768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 124768db0b9SStephen Warren 125be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 126be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 127be944d42SStephen Warren val = tegra30_apbif_read(reg); 128be944d42SStephen Warren val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | 129be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK); 130be944d42SStephen Warren val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | 131be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN | 132be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16; 133be944d42SStephen Warren tegra30_apbif_write(reg, val); 134be944d42SStephen Warren 1355e049fceSStephen Warren cif_conf.threshold = 0; 1365e049fceSStephen Warren cif_conf.audio_channels = 2; 1375e049fceSStephen Warren cif_conf.client_channels = 2; 1385e049fceSStephen Warren cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; 1395e049fceSStephen Warren cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; 1405e049fceSStephen Warren cif_conf.expand = 0; 1415e049fceSStephen Warren cif_conf.stereo_conv = 0; 1425e049fceSStephen Warren cif_conf.replicate = 0; 1435e049fceSStephen Warren cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX; 1445e049fceSStephen Warren cif_conf.truncate = 0; 1455e049fceSStephen Warren cif_conf.mono_conv = 0; 1465e049fceSStephen Warren 147be944d42SStephen Warren reg = TEGRA30_AHUB_CIF_RX_CTRL + 148be944d42SStephen Warren (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); 1495e049fceSStephen Warren ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); 150be944d42SStephen Warren 151768db0b9SStephen Warren pm_runtime_put(ahub->dev); 152768db0b9SStephen Warren 153be944d42SStephen Warren return 0; 154be944d42SStephen Warren } 155be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo); 156be944d42SStephen Warren 157be944d42SStephen Warren int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif) 158be944d42SStephen Warren { 159be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 160be944d42SStephen Warren int reg, val; 161be944d42SStephen Warren 162768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 163768db0b9SStephen Warren 164be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 165be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 166be944d42SStephen Warren val = tegra30_apbif_read(reg); 167be944d42SStephen Warren val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 168be944d42SStephen Warren tegra30_apbif_write(reg, val); 169be944d42SStephen Warren 170768db0b9SStephen Warren pm_runtime_put(ahub->dev); 171768db0b9SStephen Warren 172be944d42SStephen Warren return 0; 173be944d42SStephen Warren } 174be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo); 175be944d42SStephen Warren 176be944d42SStephen Warren int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif) 177be944d42SStephen Warren { 178be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 179be944d42SStephen Warren int reg, val; 180be944d42SStephen Warren 181768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 182768db0b9SStephen Warren 183be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 184be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 185be944d42SStephen Warren val = tegra30_apbif_read(reg); 186be944d42SStephen Warren val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 187be944d42SStephen Warren tegra30_apbif_write(reg, val); 188be944d42SStephen Warren 189768db0b9SStephen Warren pm_runtime_put(ahub->dev); 190768db0b9SStephen Warren 191be944d42SStephen Warren return 0; 192be944d42SStephen Warren } 193be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo); 194be944d42SStephen Warren 195be944d42SStephen Warren int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif) 196be944d42SStephen Warren { 197be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 198be944d42SStephen Warren 199be944d42SStephen Warren __clear_bit(channel, ahub->rx_usage); 200be944d42SStephen Warren 201be944d42SStephen Warren return 0; 202be944d42SStephen Warren } 203be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo); 204be944d42SStephen Warren 205be944d42SStephen Warren int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 2065608bd3eSStephen Warren char *dmachan, int dmachan_len, 2075608bd3eSStephen Warren dma_addr_t *fiforeg) 208be944d42SStephen Warren { 209be944d42SStephen Warren int channel; 210be944d42SStephen Warren u32 reg, val; 2115e049fceSStephen Warren struct tegra30_ahub_cif_conf cif_conf; 212be944d42SStephen Warren 213be944d42SStephen Warren channel = find_first_zero_bit(ahub->tx_usage, 214be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 215be944d42SStephen Warren if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) 216be944d42SStephen Warren return -EBUSY; 217be944d42SStephen Warren 218be944d42SStephen Warren __set_bit(channel, ahub->tx_usage); 219be944d42SStephen Warren 220be944d42SStephen Warren *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel; 2215608bd3eSStephen Warren snprintf(dmachan, dmachan_len, "tx%d", channel); 222be944d42SStephen Warren *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO + 223be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE); 224be944d42SStephen Warren 225768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 226768db0b9SStephen Warren 227be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 228be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 229be944d42SStephen Warren val = tegra30_apbif_read(reg); 230be944d42SStephen Warren val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | 231be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK); 232be944d42SStephen Warren val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | 233be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN | 234be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16; 235be944d42SStephen Warren tegra30_apbif_write(reg, val); 236be944d42SStephen Warren 2375e049fceSStephen Warren cif_conf.threshold = 0; 2385e049fceSStephen Warren cif_conf.audio_channels = 2; 2395e049fceSStephen Warren cif_conf.client_channels = 2; 2405e049fceSStephen Warren cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; 2415e049fceSStephen Warren cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; 2425e049fceSStephen Warren cif_conf.expand = 0; 2435e049fceSStephen Warren cif_conf.stereo_conv = 0; 2445e049fceSStephen Warren cif_conf.replicate = 0; 2455e049fceSStephen Warren cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX; 2465e049fceSStephen Warren cif_conf.truncate = 0; 2475e049fceSStephen Warren cif_conf.mono_conv = 0; 2485e049fceSStephen Warren 249be944d42SStephen Warren reg = TEGRA30_AHUB_CIF_TX_CTRL + 250be944d42SStephen Warren (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); 2515e049fceSStephen Warren ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); 252be944d42SStephen Warren 253768db0b9SStephen Warren pm_runtime_put(ahub->dev); 254768db0b9SStephen Warren 255be944d42SStephen Warren return 0; 256be944d42SStephen Warren } 257be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo); 258be944d42SStephen Warren 259be944d42SStephen Warren int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif) 260be944d42SStephen Warren { 261be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 262be944d42SStephen Warren int reg, val; 263be944d42SStephen Warren 264768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 265768db0b9SStephen Warren 266be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 267be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 268be944d42SStephen Warren val = tegra30_apbif_read(reg); 269be944d42SStephen Warren val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 270be944d42SStephen Warren tegra30_apbif_write(reg, val); 271be944d42SStephen Warren 272768db0b9SStephen Warren pm_runtime_put(ahub->dev); 273768db0b9SStephen Warren 274be944d42SStephen Warren return 0; 275be944d42SStephen Warren } 276be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo); 277be944d42SStephen Warren 278be944d42SStephen Warren int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif) 279be944d42SStephen Warren { 280be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 281be944d42SStephen Warren int reg, val; 282be944d42SStephen Warren 283768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 284768db0b9SStephen Warren 285be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 286be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 287be944d42SStephen Warren val = tegra30_apbif_read(reg); 288be944d42SStephen Warren val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 289be944d42SStephen Warren tegra30_apbif_write(reg, val); 290be944d42SStephen Warren 291768db0b9SStephen Warren pm_runtime_put(ahub->dev); 292768db0b9SStephen Warren 293be944d42SStephen Warren return 0; 294be944d42SStephen Warren } 295be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo); 296be944d42SStephen Warren 297be944d42SStephen Warren int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif) 298be944d42SStephen Warren { 299be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 300be944d42SStephen Warren 301be944d42SStephen Warren __clear_bit(channel, ahub->tx_usage); 302be944d42SStephen Warren 303be944d42SStephen Warren return 0; 304be944d42SStephen Warren } 305be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo); 306be944d42SStephen Warren 307be944d42SStephen Warren int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, 308be944d42SStephen Warren enum tegra30_ahub_txcif txcif) 309be944d42SStephen Warren { 310be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 311be944d42SStephen Warren int reg; 312be944d42SStephen Warren 313768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 314768db0b9SStephen Warren 315be944d42SStephen Warren reg = TEGRA30_AHUB_AUDIO_RX + 316be944d42SStephen Warren (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 317be944d42SStephen Warren tegra30_audio_write(reg, 1 << txcif); 318be944d42SStephen Warren 319768db0b9SStephen Warren pm_runtime_put(ahub->dev); 320768db0b9SStephen Warren 321be944d42SStephen Warren return 0; 322be944d42SStephen Warren } 323be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source); 324be944d42SStephen Warren 325be944d42SStephen Warren int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif) 326be944d42SStephen Warren { 327be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 328be944d42SStephen Warren int reg; 329be944d42SStephen Warren 330768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 331768db0b9SStephen Warren 332be944d42SStephen Warren reg = TEGRA30_AHUB_AUDIO_RX + 333be944d42SStephen Warren (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 334be944d42SStephen Warren tegra30_audio_write(reg, 0); 335be944d42SStephen Warren 336768db0b9SStephen Warren pm_runtime_put(ahub->dev); 337768db0b9SStephen Warren 338be944d42SStephen Warren return 0; 339be944d42SStephen Warren } 340be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source); 341be944d42SStephen Warren 3425185e0acSStephen Warren #define MOD_LIST_MASK_TEGRA30 BIT(0) 3435185e0acSStephen Warren #define MOD_LIST_MASK_TEGRA114 BIT(1) 344f1d6ff79SStephen Warren #define MOD_LIST_MASK_TEGRA124 BIT(2) 34595d36075SStephen Warren 3465185e0acSStephen Warren #define MOD_LIST_MASK_TEGRA30_OR_LATER \ 347f1d6ff79SStephen Warren (MOD_LIST_MASK_TEGRA30 | MOD_LIST_MASK_TEGRA114 | \ 348f1d6ff79SStephen Warren MOD_LIST_MASK_TEGRA124) 349f1d6ff79SStephen Warren #define MOD_LIST_MASK_TEGRA114_OR_LATER \ 350f1d6ff79SStephen Warren (MOD_LIST_MASK_TEGRA114 | MOD_LIST_MASK_TEGRA124) 35195d36075SStephen Warren 35295d36075SStephen Warren static const struct { 3535185e0acSStephen Warren const char *rst_name; 3545185e0acSStephen Warren u32 mod_list_mask; 3555185e0acSStephen Warren } configlink_mods[] = { 35624a41a38SDmitry Osipenko { "d_audio", MOD_LIST_MASK_TEGRA30_OR_LATER }, 35724a41a38SDmitry Osipenko { "apbif", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3585185e0acSStephen Warren { "i2s0", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3595185e0acSStephen Warren { "i2s1", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3605185e0acSStephen Warren { "i2s2", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3615185e0acSStephen Warren { "i2s3", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3625185e0acSStephen Warren { "i2s4", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3635185e0acSStephen Warren { "dam0", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3645185e0acSStephen Warren { "dam1", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3655185e0acSStephen Warren { "dam2", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3665185e0acSStephen Warren { "spdif", MOD_LIST_MASK_TEGRA30_OR_LATER }, 367f1d6ff79SStephen Warren { "amx", MOD_LIST_MASK_TEGRA114_OR_LATER }, 368f1d6ff79SStephen Warren { "adx", MOD_LIST_MASK_TEGRA114_OR_LATER }, 369f1d6ff79SStephen Warren { "amx1", MOD_LIST_MASK_TEGRA124 }, 370f1d6ff79SStephen Warren { "adx1", MOD_LIST_MASK_TEGRA124 }, 371f1d6ff79SStephen Warren { "afc0", MOD_LIST_MASK_TEGRA124 }, 372f1d6ff79SStephen Warren { "afc1", MOD_LIST_MASK_TEGRA124 }, 373f1d6ff79SStephen Warren { "afc2", MOD_LIST_MASK_TEGRA124 }, 374f1d6ff79SStephen Warren { "afc3", MOD_LIST_MASK_TEGRA124 }, 375f1d6ff79SStephen Warren { "afc4", MOD_LIST_MASK_TEGRA124 }, 376f1d6ff79SStephen Warren { "afc5", MOD_LIST_MASK_TEGRA124 }, 377be944d42SStephen Warren }; 378be944d42SStephen Warren 379be944d42SStephen Warren #define LAST_REG(name) \ 380be944d42SStephen Warren (TEGRA30_AHUB_##name + \ 381be944d42SStephen Warren (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4) 382be944d42SStephen Warren 383be944d42SStephen Warren #define REG_IN_ARRAY(reg, name) \ 384be944d42SStephen Warren ((reg >= TEGRA30_AHUB_##name) && \ 385be944d42SStephen Warren (reg <= LAST_REG(name) && \ 386be944d42SStephen Warren (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE)))) 387be944d42SStephen Warren 388be944d42SStephen Warren static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) 389be944d42SStephen Warren { 390be944d42SStephen Warren switch (reg) { 391be944d42SStephen Warren case TEGRA30_AHUB_CONFIG_LINK_CTRL: 392be944d42SStephen Warren case TEGRA30_AHUB_MISC_CTRL: 393be944d42SStephen Warren case TEGRA30_AHUB_APBDMA_LIVE_STATUS: 394be944d42SStephen Warren case TEGRA30_AHUB_I2S_LIVE_STATUS: 395be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_LIVE_STATUS: 396be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_MASK: 397be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_MASK: 398be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_MASK: 399be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_MASK: 400be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_STATUS: 401be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_STATUS: 402be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_STATUS: 403be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_STATUS: 404be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SOURCE: 405be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SOURCE: 406be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SOURCE: 407be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SOURCE: 408be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SET: 409be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SET: 410be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SET: 411be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SET: 412be944d42SStephen Warren return true; 413be944d42SStephen Warren default: 414be944d42SStephen Warren break; 4151d198f26SJoe Perches } 416be944d42SStephen Warren 417be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || 418be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_CLEAR) || 419be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_STATUS) || 420be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 421be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || 422be944d42SStephen Warren REG_IN_ARRAY(reg, CIF_TX_CTRL) || 423be944d42SStephen Warren REG_IN_ARRAY(reg, CIF_RX_CTRL) || 424be944d42SStephen Warren REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) 425be944d42SStephen Warren return true; 426be944d42SStephen Warren 427be944d42SStephen Warren return false; 428be944d42SStephen Warren } 429be944d42SStephen Warren 430be944d42SStephen Warren static bool tegra30_ahub_apbif_volatile_reg(struct device *dev, 431be944d42SStephen Warren unsigned int reg) 432be944d42SStephen Warren { 433be944d42SStephen Warren switch (reg) { 434be944d42SStephen Warren case TEGRA30_AHUB_CONFIG_LINK_CTRL: 435be944d42SStephen Warren case TEGRA30_AHUB_MISC_CTRL: 436be944d42SStephen Warren case TEGRA30_AHUB_APBDMA_LIVE_STATUS: 437be944d42SStephen Warren case TEGRA30_AHUB_I2S_LIVE_STATUS: 438be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_LIVE_STATUS: 439be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_STATUS: 440be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_STATUS: 441be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_STATUS: 442be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_STATUS: 443be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SET: 444be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SET: 445be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SET: 446be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SET: 447be944d42SStephen Warren return true; 448be944d42SStephen Warren default: 449be944d42SStephen Warren break; 4501d198f26SJoe Perches } 451be944d42SStephen Warren 452be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || 453be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_STATUS) || 454be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 455be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || 456be944d42SStephen Warren REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) 457be944d42SStephen Warren return true; 458be944d42SStephen Warren 459be944d42SStephen Warren return false; 460be944d42SStephen Warren } 461be944d42SStephen Warren 462be944d42SStephen Warren static bool tegra30_ahub_apbif_precious_reg(struct device *dev, 463be944d42SStephen Warren unsigned int reg) 464be944d42SStephen Warren { 465be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 466be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) 467be944d42SStephen Warren return true; 468be944d42SStephen Warren 469be944d42SStephen Warren return false; 470be944d42SStephen Warren } 471be944d42SStephen Warren 472be944d42SStephen Warren static const struct regmap_config tegra30_ahub_apbif_regmap_config = { 473be944d42SStephen Warren .name = "apbif", 474be944d42SStephen Warren .reg_bits = 32, 475be944d42SStephen Warren .val_bits = 32, 476be944d42SStephen Warren .reg_stride = 4, 477be944d42SStephen Warren .max_register = TEGRA30_AHUB_APBIF_INT_SET, 478be944d42SStephen Warren .writeable_reg = tegra30_ahub_apbif_wr_rd_reg, 479be944d42SStephen Warren .readable_reg = tegra30_ahub_apbif_wr_rd_reg, 480be944d42SStephen Warren .volatile_reg = tegra30_ahub_apbif_volatile_reg, 481be944d42SStephen Warren .precious_reg = tegra30_ahub_apbif_precious_reg, 482591d14f0SDylan Reid .cache_type = REGCACHE_FLAT, 483be944d42SStephen Warren }; 484be944d42SStephen Warren 485be944d42SStephen Warren static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) 486be944d42SStephen Warren { 487be944d42SStephen Warren if (REG_IN_ARRAY(reg, AUDIO_RX)) 488be944d42SStephen Warren return true; 489be944d42SStephen Warren 490be944d42SStephen Warren return false; 491be944d42SStephen Warren } 492be944d42SStephen Warren 493be944d42SStephen Warren static const struct regmap_config tegra30_ahub_ahub_regmap_config = { 494be944d42SStephen Warren .name = "ahub", 495be944d42SStephen Warren .reg_bits = 32, 496be944d42SStephen Warren .val_bits = 32, 497be944d42SStephen Warren .reg_stride = 4, 498be944d42SStephen Warren .max_register = LAST_REG(AUDIO_RX), 499be944d42SStephen Warren .writeable_reg = tegra30_ahub_ahub_wr_rd_reg, 500be944d42SStephen Warren .readable_reg = tegra30_ahub_ahub_wr_rd_reg, 501591d14f0SDylan Reid .cache_type = REGCACHE_FLAT, 502be944d42SStephen Warren }; 503be944d42SStephen Warren 50495d36075SStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra30 = { 5055185e0acSStephen Warren .mod_list_mask = MOD_LIST_MASK_TEGRA30, 5065e049fceSStephen Warren .set_audio_cif = tegra30_ahub_set_cif, 50795d36075SStephen Warren }; 50895d36075SStephen Warren 50995d36075SStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra114 = { 5105185e0acSStephen Warren .mod_list_mask = MOD_LIST_MASK_TEGRA114, 5115e049fceSStephen Warren .set_audio_cif = tegra30_ahub_set_cif, 5125e049fceSStephen Warren }; 5135e049fceSStephen Warren 5145e049fceSStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra124 = { 515f1d6ff79SStephen Warren .mod_list_mask = MOD_LIST_MASK_TEGRA124, 5165e049fceSStephen Warren .set_audio_cif = tegra124_ahub_set_cif, 51795d36075SStephen Warren }; 51895d36075SStephen Warren 51995d36075SStephen Warren static const struct of_device_id tegra30_ahub_of_match[] = { 5205e049fceSStephen Warren { .compatible = "nvidia,tegra124-ahub", .data = &soc_data_tegra124 }, 52195d36075SStephen Warren { .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 }, 52295d36075SStephen Warren { .compatible = "nvidia,tegra30-ahub", .data = &soc_data_tegra30 }, 52395d36075SStephen Warren {}, 52495d36075SStephen Warren }; 52595d36075SStephen Warren 5264652a0d0SBill Pemberton static int tegra30_ahub_probe(struct platform_device *pdev) 527be944d42SStephen Warren { 52895d36075SStephen Warren const struct of_device_id *match; 52995d36075SStephen Warren const struct tegra30_ahub_soc_data *soc_data; 5305185e0acSStephen Warren struct reset_control *rst; 531be944d42SStephen Warren int i; 532a813d0e8SYueHaibing struct resource *res0; 533be944d42SStephen Warren void __iomem *regs_apbif, *regs_ahub; 534be944d42SStephen Warren int ret = 0; 535be944d42SStephen Warren 536be944d42SStephen Warren if (ahub) 537be944d42SStephen Warren return -ENODEV; 538be944d42SStephen Warren 53995d36075SStephen Warren match = of_match_device(tegra30_ahub_of_match, &pdev->dev); 54095d36075SStephen Warren if (!match) 54195d36075SStephen Warren return -EINVAL; 54295d36075SStephen Warren soc_data = match->data; 54395d36075SStephen Warren 544be944d42SStephen Warren /* 545be944d42SStephen Warren * The AHUB hosts a register bus: the "configlink". For this to 546be944d42SStephen Warren * operate correctly, all devices on this bus must be out of reset. 547be944d42SStephen Warren */ 5485185e0acSStephen Warren for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) { 5495185e0acSStephen Warren if (!(configlink_mods[i].mod_list_mask & 5505185e0acSStephen Warren soc_data->mod_list_mask)) 55195d36075SStephen Warren continue; 5525185e0acSStephen Warren 553181e8ce6SPhilipp Zabel rst = reset_control_get_exclusive(&pdev->dev, 5545185e0acSStephen Warren configlink_mods[i].rst_name); 5555185e0acSStephen Warren if (IS_ERR(rst)) { 5565185e0acSStephen Warren dev_err(&pdev->dev, "Can't get reset %s\n", 5575185e0acSStephen Warren configlink_mods[i].rst_name); 5585185e0acSStephen Warren ret = PTR_ERR(rst); 5598833c01aSVaishali Thakkar return ret; 560be944d42SStephen Warren } 5615185e0acSStephen Warren 562*ed9ce1edSDmitry Osipenko /* just check presence of the reset control in DT */ 5635185e0acSStephen Warren reset_control_put(rst); 564be944d42SStephen Warren } 565be944d42SStephen Warren 566be944d42SStephen Warren ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub), 567be944d42SStephen Warren GFP_KERNEL); 568e2c187a6SCodrut Grosu if (!ahub) 5698833c01aSVaishali Thakkar return -ENOMEM; 570be944d42SStephen Warren dev_set_drvdata(&pdev->dev, ahub); 571be944d42SStephen Warren 5725e049fceSStephen Warren ahub->soc_data = soc_data; 573be944d42SStephen Warren ahub->dev = &pdev->dev; 574be944d42SStephen Warren 5756d8ac9b1SDmitry Osipenko ahub->clocks[ahub->nclocks++].id = "apbif"; 5766d8ac9b1SDmitry Osipenko ahub->clocks[ahub->nclocks++].id = "d_audio"; 577be944d42SStephen Warren 5786d8ac9b1SDmitry Osipenko ret = devm_clk_bulk_get(&pdev->dev, ahub->nclocks, ahub->clocks); 5796d8ac9b1SDmitry Osipenko if (ret) 5808833c01aSVaishali Thakkar return ret; 581be944d42SStephen Warren 582*ed9ce1edSDmitry Osipenko ahub->reset = devm_reset_control_array_get_exclusive(&pdev->dev); 583*ed9ce1edSDmitry Osipenko if (IS_ERR(ahub->reset)) { 584*ed9ce1edSDmitry Osipenko dev_err(&pdev->dev, "Can't get resets: %pe\n", ahub->reset); 585*ed9ce1edSDmitry Osipenko return PTR_ERR(ahub->reset); 586*ed9ce1edSDmitry Osipenko } 587*ed9ce1edSDmitry Osipenko 588be944d42SStephen Warren res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 589f57ddcdfSAxel Lin regs_apbif = devm_ioremap_resource(&pdev->dev, res0); 590f57ddcdfSAxel Lin if (IS_ERR(regs_apbif)) 591f57ddcdfSAxel Lin return PTR_ERR(regs_apbif); 592be944d42SStephen Warren 593be944d42SStephen Warren ahub->apbif_addr = res0->start; 594be944d42SStephen Warren 595be944d42SStephen Warren ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif, 596be944d42SStephen Warren &tegra30_ahub_apbif_regmap_config); 597be944d42SStephen Warren if (IS_ERR(ahub->regmap_apbif)) { 598be944d42SStephen Warren dev_err(&pdev->dev, "apbif regmap init failed\n"); 599be944d42SStephen Warren ret = PTR_ERR(ahub->regmap_apbif); 6008833c01aSVaishali Thakkar return ret; 601be944d42SStephen Warren } 602be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, true); 603be944d42SStephen Warren 604a813d0e8SYueHaibing regs_ahub = devm_platform_ioremap_resource(pdev, 1); 605f57ddcdfSAxel Lin if (IS_ERR(regs_ahub)) 606f57ddcdfSAxel Lin return PTR_ERR(regs_ahub); 607be944d42SStephen Warren 608be944d42SStephen Warren ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub, 609be944d42SStephen Warren &tegra30_ahub_ahub_regmap_config); 610be944d42SStephen Warren if (IS_ERR(ahub->regmap_ahub)) { 611be944d42SStephen Warren dev_err(&pdev->dev, "ahub regmap init failed\n"); 612be944d42SStephen Warren ret = PTR_ERR(ahub->regmap_ahub); 6138833c01aSVaishali Thakkar return ret; 614be944d42SStephen Warren } 615be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, true); 616be944d42SStephen Warren 617be944d42SStephen Warren pm_runtime_enable(&pdev->dev); 618be944d42SStephen Warren if (!pm_runtime_enabled(&pdev->dev)) { 619be944d42SStephen Warren ret = tegra30_ahub_runtime_resume(&pdev->dev); 620be944d42SStephen Warren if (ret) 621be944d42SStephen Warren goto err_pm_disable; 622be944d42SStephen Warren } 623be944d42SStephen Warren 62479cf5918SPrashant Gaikwad of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 625be944d42SStephen Warren 626be944d42SStephen Warren return 0; 627be944d42SStephen Warren 628be944d42SStephen Warren err_pm_disable: 629be944d42SStephen Warren pm_runtime_disable(&pdev->dev); 6308833c01aSVaishali Thakkar 631be944d42SStephen Warren return ret; 632be944d42SStephen Warren } 633be944d42SStephen Warren 6344652a0d0SBill Pemberton static int tegra30_ahub_remove(struct platform_device *pdev) 635be944d42SStephen Warren { 636be944d42SStephen Warren if (!ahub) 637be944d42SStephen Warren return -ENODEV; 638be944d42SStephen Warren 639be944d42SStephen Warren pm_runtime_disable(&pdev->dev); 640be944d42SStephen Warren if (!pm_runtime_status_suspended(&pdev->dev)) 641be944d42SStephen Warren tegra30_ahub_runtime_suspend(&pdev->dev); 642be944d42SStephen Warren 643be944d42SStephen Warren return 0; 644be944d42SStephen Warren } 645be944d42SStephen Warren 6462f41a3f4SStephen Warren #ifdef CONFIG_PM_SLEEP 6472f41a3f4SStephen Warren static int tegra30_ahub_suspend(struct device *dev) 6482f41a3f4SStephen Warren { 6492f41a3f4SStephen Warren regcache_mark_dirty(ahub->regmap_ahub); 6502f41a3f4SStephen Warren regcache_mark_dirty(ahub->regmap_apbif); 6512f41a3f4SStephen Warren 6522f41a3f4SStephen Warren return 0; 6532f41a3f4SStephen Warren } 6542f41a3f4SStephen Warren 6552f41a3f4SStephen Warren static int tegra30_ahub_resume(struct device *dev) 6562f41a3f4SStephen Warren { 6572f41a3f4SStephen Warren int ret; 6582f41a3f4SStephen Warren 659249e66c3SStephen Warren ret = pm_runtime_get_sync(dev); 660deca1953SQiushi Wu if (ret < 0) { 661deca1953SQiushi Wu pm_runtime_put(dev); 662249e66c3SStephen Warren return ret; 663deca1953SQiushi Wu } 6642f41a3f4SStephen Warren ret = regcache_sync(ahub->regmap_ahub); 6652f41a3f4SStephen Warren ret |= regcache_sync(ahub->regmap_apbif); 666249e66c3SStephen Warren pm_runtime_put(dev); 6672f41a3f4SStephen Warren 6682f41a3f4SStephen Warren return ret; 6692f41a3f4SStephen Warren } 6702f41a3f4SStephen Warren #endif 6712f41a3f4SStephen Warren 672f6e65744SBill Pemberton static const struct dev_pm_ops tegra30_ahub_pm_ops = { 673be944d42SStephen Warren SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend, 674be944d42SStephen Warren tegra30_ahub_runtime_resume, NULL) 6752f41a3f4SStephen Warren SET_SYSTEM_SLEEP_PM_OPS(tegra30_ahub_suspend, tegra30_ahub_resume) 676be944d42SStephen Warren }; 677be944d42SStephen Warren 678be944d42SStephen Warren static struct platform_driver tegra30_ahub_driver = { 679be944d42SStephen Warren .probe = tegra30_ahub_probe, 6804652a0d0SBill Pemberton .remove = tegra30_ahub_remove, 681be944d42SStephen Warren .driver = { 682be944d42SStephen Warren .name = DRV_NAME, 683be944d42SStephen Warren .of_match_table = tegra30_ahub_of_match, 684be944d42SStephen Warren .pm = &tegra30_ahub_pm_ops, 685be944d42SStephen Warren }, 686be944d42SStephen Warren }; 687be944d42SStephen Warren module_platform_driver(tegra30_ahub_driver); 688be944d42SStephen Warren 6895e049fceSStephen Warren void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, 6905e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf) 6915e049fceSStephen Warren { 6925e049fceSStephen Warren unsigned int value; 6935e049fceSStephen Warren 6945e049fceSStephen Warren value = (conf->threshold << 6955e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 6965e049fceSStephen Warren ((conf->audio_channels - 1) << 6975e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 6985e049fceSStephen Warren ((conf->client_channels - 1) << 6995e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 7005e049fceSStephen Warren (conf->audio_bits << 7015e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | 7025e049fceSStephen Warren (conf->client_bits << 7035e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | 7045e049fceSStephen Warren (conf->expand << 7055e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | 7065e049fceSStephen Warren (conf->stereo_conv << 7075e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | 7085e049fceSStephen Warren (conf->replicate << 7095e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) | 7105e049fceSStephen Warren (conf->direction << 7115e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | 7125e049fceSStephen Warren (conf->truncate << 7135e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | 7145e049fceSStephen Warren (conf->mono_conv << 7155e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT); 7165e049fceSStephen Warren 7175e049fceSStephen Warren regmap_write(regmap, reg, value); 7185e049fceSStephen Warren } 7195e049fceSStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_set_cif); 7205e049fceSStephen Warren 7215e049fceSStephen Warren void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, 7225e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf) 7235e049fceSStephen Warren { 7245e049fceSStephen Warren unsigned int value; 7255e049fceSStephen Warren 7265e049fceSStephen Warren value = (conf->threshold << 7275e049fceSStephen Warren TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 7285e049fceSStephen Warren ((conf->audio_channels - 1) << 7295e049fceSStephen Warren TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 7305e049fceSStephen Warren ((conf->client_channels - 1) << 7315e049fceSStephen Warren TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 7325e049fceSStephen Warren (conf->audio_bits << 7335e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | 7345e049fceSStephen Warren (conf->client_bits << 7355e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | 7365e049fceSStephen Warren (conf->expand << 7375e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | 7385e049fceSStephen Warren (conf->stereo_conv << 7395e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | 7405e049fceSStephen Warren (conf->replicate << 7415e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) | 7425e049fceSStephen Warren (conf->direction << 7435e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | 7445e049fceSStephen Warren (conf->truncate << 7455e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | 7465e049fceSStephen Warren (conf->mono_conv << 7475e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT); 7485e049fceSStephen Warren 7495e049fceSStephen Warren regmap_write(regmap, reg, value); 7505e049fceSStephen Warren } 7515e049fceSStephen Warren EXPORT_SYMBOL_GPL(tegra124_ahub_set_cif); 7525e049fceSStephen Warren 753be944d42SStephen Warren MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 754be944d42SStephen Warren MODULE_DESCRIPTION("Tegra30 AHUB driver"); 755be944d42SStephen Warren MODULE_LICENSE("GPL v2"); 756be944d42SStephen Warren MODULE_ALIAS("platform:" DRV_NAME); 75769c5b753SStephen Warren MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match); 758