1be944d42SStephen Warren /* 2be944d42SStephen Warren * tegra30_ahub.c - Tegra30 AHUB driver 3be944d42SStephen Warren * 4be944d42SStephen Warren * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 5be944d42SStephen Warren * 6be944d42SStephen Warren * This program is free software; you can redistribute it and/or modify it 7be944d42SStephen Warren * under the terms and conditions of the GNU General Public License, 8be944d42SStephen Warren * version 2, as published by the Free Software Foundation. 9be944d42SStephen Warren * 10be944d42SStephen Warren * This program is distributed in the hope it will be useful, but WITHOUT 11be944d42SStephen Warren * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12be944d42SStephen Warren * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13be944d42SStephen Warren * more details. 14be944d42SStephen Warren * 15be944d42SStephen Warren * You should have received a copy of the GNU General Public License 16be944d42SStephen Warren * along with this program. If not, see <http://www.gnu.org/licenses/>. 17be944d42SStephen Warren */ 18be944d42SStephen Warren 19be944d42SStephen Warren #include <linux/clk.h> 20be944d42SStephen Warren #include <linux/device.h> 21be944d42SStephen Warren #include <linux/io.h> 22be944d42SStephen Warren #include <linux/module.h> 23be944d42SStephen Warren #include <linux/of_platform.h> 24be944d42SStephen Warren #include <linux/platform_device.h> 25be944d42SStephen Warren #include <linux/pm_runtime.h> 26be944d42SStephen Warren #include <linux/regmap.h> 275185e0acSStephen Warren #include <linux/reset.h> 28be944d42SStephen Warren #include <linux/slab.h> 29be944d42SStephen Warren #include <sound/soc.h> 30be944d42SStephen Warren #include "tegra30_ahub.h" 31be944d42SStephen Warren 32be944d42SStephen Warren #define DRV_NAME "tegra30-ahub" 33be944d42SStephen Warren 34be944d42SStephen Warren static struct tegra30_ahub *ahub; 35be944d42SStephen Warren 36be944d42SStephen Warren static inline void tegra30_apbif_write(u32 reg, u32 val) 37be944d42SStephen Warren { 38be944d42SStephen Warren regmap_write(ahub->regmap_apbif, reg, val); 39be944d42SStephen Warren } 40be944d42SStephen Warren 41be944d42SStephen Warren static inline u32 tegra30_apbif_read(u32 reg) 42be944d42SStephen Warren { 43be944d42SStephen Warren u32 val; 44bf3c6ef7SCodrut Grosu 45be944d42SStephen Warren regmap_read(ahub->regmap_apbif, reg, &val); 46be944d42SStephen Warren return val; 47be944d42SStephen Warren } 48be944d42SStephen Warren 49be944d42SStephen Warren static inline void tegra30_audio_write(u32 reg, u32 val) 50be944d42SStephen Warren { 51be944d42SStephen Warren regmap_write(ahub->regmap_ahub, reg, val); 52be944d42SStephen Warren } 53be944d42SStephen Warren 54be944d42SStephen Warren static int tegra30_ahub_runtime_suspend(struct device *dev) 55be944d42SStephen Warren { 56be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, true); 57be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, true); 58be944d42SStephen Warren 5965d2bdd3SPrashant Gaikwad clk_disable_unprepare(ahub->clk_apbif); 6065d2bdd3SPrashant Gaikwad clk_disable_unprepare(ahub->clk_d_audio); 61be944d42SStephen Warren 62be944d42SStephen Warren return 0; 63be944d42SStephen Warren } 64be944d42SStephen Warren 65be944d42SStephen Warren /* 66be944d42SStephen Warren * clk_apbif isn't required for an I2S<->I2S configuration where no PCM data 67be944d42SStephen Warren * is read from or sent to memory. However, that's not something the rest of 68be944d42SStephen Warren * the driver supports right now, so we'll just treat the two clocks as one 69be944d42SStephen Warren * for now. 70be944d42SStephen Warren * 71be944d42SStephen Warren * These functions should not be a plain ref-count. Instead, each active stream 72be944d42SStephen Warren * contributes some requirement to the minimum clock rate, so starting or 73be944d42SStephen Warren * stopping streams should dynamically adjust the clock as required. However, 74be944d42SStephen Warren * this is not yet implemented. 75be944d42SStephen Warren */ 76be944d42SStephen Warren static int tegra30_ahub_runtime_resume(struct device *dev) 77be944d42SStephen Warren { 78be944d42SStephen Warren int ret; 79be944d42SStephen Warren 8065d2bdd3SPrashant Gaikwad ret = clk_prepare_enable(ahub->clk_d_audio); 81be944d42SStephen Warren if (ret) { 82be944d42SStephen Warren dev_err(dev, "clk_enable d_audio failed: %d\n", ret); 83be944d42SStephen Warren return ret; 84be944d42SStephen Warren } 8565d2bdd3SPrashant Gaikwad ret = clk_prepare_enable(ahub->clk_apbif); 86be944d42SStephen Warren if (ret) { 87be944d42SStephen Warren dev_err(dev, "clk_enable apbif failed: %d\n", ret); 88be944d42SStephen Warren clk_disable(ahub->clk_d_audio); 89be944d42SStephen Warren return ret; 90be944d42SStephen Warren } 91be944d42SStephen Warren 92be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, false); 93be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, false); 94be944d42SStephen Warren 95be944d42SStephen Warren return 0; 96be944d42SStephen Warren } 97be944d42SStephen Warren 98be944d42SStephen Warren int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 995608bd3eSStephen Warren char *dmachan, int dmachan_len, 1005608bd3eSStephen Warren dma_addr_t *fiforeg) 101be944d42SStephen Warren { 102be944d42SStephen Warren int channel; 103be944d42SStephen Warren u32 reg, val; 1045e049fceSStephen Warren struct tegra30_ahub_cif_conf cif_conf; 105be944d42SStephen Warren 106be944d42SStephen Warren channel = find_first_zero_bit(ahub->rx_usage, 107be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 108be944d42SStephen Warren if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) 109be944d42SStephen Warren return -EBUSY; 110be944d42SStephen Warren 111be944d42SStephen Warren __set_bit(channel, ahub->rx_usage); 112be944d42SStephen Warren 113be944d42SStephen Warren *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel; 1145608bd3eSStephen Warren snprintf(dmachan, dmachan_len, "rx%d", channel); 115be944d42SStephen Warren *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO + 116be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE); 117be944d42SStephen Warren 118768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 119768db0b9SStephen Warren 120be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 121be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 122be944d42SStephen Warren val = tegra30_apbif_read(reg); 123be944d42SStephen Warren val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | 124be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK); 125be944d42SStephen Warren val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | 126be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN | 127be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16; 128be944d42SStephen Warren tegra30_apbif_write(reg, val); 129be944d42SStephen Warren 1305e049fceSStephen Warren cif_conf.threshold = 0; 1315e049fceSStephen Warren cif_conf.audio_channels = 2; 1325e049fceSStephen Warren cif_conf.client_channels = 2; 1335e049fceSStephen Warren cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; 1345e049fceSStephen Warren cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; 1355e049fceSStephen Warren cif_conf.expand = 0; 1365e049fceSStephen Warren cif_conf.stereo_conv = 0; 1375e049fceSStephen Warren cif_conf.replicate = 0; 1385e049fceSStephen Warren cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX; 1395e049fceSStephen Warren cif_conf.truncate = 0; 1405e049fceSStephen Warren cif_conf.mono_conv = 0; 1415e049fceSStephen Warren 142be944d42SStephen Warren reg = TEGRA30_AHUB_CIF_RX_CTRL + 143be944d42SStephen Warren (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); 1445e049fceSStephen Warren ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); 145be944d42SStephen Warren 146768db0b9SStephen Warren pm_runtime_put(ahub->dev); 147768db0b9SStephen Warren 148be944d42SStephen Warren return 0; 149be944d42SStephen Warren } 150be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo); 151be944d42SStephen Warren 152be944d42SStephen Warren int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif) 153be944d42SStephen Warren { 154be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 155be944d42SStephen Warren int reg, val; 156be944d42SStephen Warren 157768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 158768db0b9SStephen Warren 159be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 160be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 161be944d42SStephen Warren val = tegra30_apbif_read(reg); 162be944d42SStephen Warren val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 163be944d42SStephen Warren tegra30_apbif_write(reg, val); 164be944d42SStephen Warren 165768db0b9SStephen Warren pm_runtime_put(ahub->dev); 166768db0b9SStephen Warren 167be944d42SStephen Warren return 0; 168be944d42SStephen Warren } 169be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo); 170be944d42SStephen Warren 171be944d42SStephen Warren int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif) 172be944d42SStephen Warren { 173be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 174be944d42SStephen Warren int reg, val; 175be944d42SStephen Warren 176768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 177768db0b9SStephen Warren 178be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 179be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 180be944d42SStephen Warren val = tegra30_apbif_read(reg); 181be944d42SStephen Warren val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 182be944d42SStephen Warren tegra30_apbif_write(reg, val); 183be944d42SStephen Warren 184768db0b9SStephen Warren pm_runtime_put(ahub->dev); 185768db0b9SStephen Warren 186be944d42SStephen Warren return 0; 187be944d42SStephen Warren } 188be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo); 189be944d42SStephen Warren 190be944d42SStephen Warren int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif) 191be944d42SStephen Warren { 192be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 193be944d42SStephen Warren 194be944d42SStephen Warren __clear_bit(channel, ahub->rx_usage); 195be944d42SStephen Warren 196be944d42SStephen Warren return 0; 197be944d42SStephen Warren } 198be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo); 199be944d42SStephen Warren 200be944d42SStephen Warren int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 2015608bd3eSStephen Warren char *dmachan, int dmachan_len, 2025608bd3eSStephen Warren dma_addr_t *fiforeg) 203be944d42SStephen Warren { 204be944d42SStephen Warren int channel; 205be944d42SStephen Warren u32 reg, val; 2065e049fceSStephen Warren struct tegra30_ahub_cif_conf cif_conf; 207be944d42SStephen Warren 208be944d42SStephen Warren channel = find_first_zero_bit(ahub->tx_usage, 209be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 210be944d42SStephen Warren if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) 211be944d42SStephen Warren return -EBUSY; 212be944d42SStephen Warren 213be944d42SStephen Warren __set_bit(channel, ahub->tx_usage); 214be944d42SStephen Warren 215be944d42SStephen Warren *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel; 2165608bd3eSStephen Warren snprintf(dmachan, dmachan_len, "tx%d", channel); 217be944d42SStephen Warren *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO + 218be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE); 219be944d42SStephen Warren 220768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 221768db0b9SStephen Warren 222be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 223be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 224be944d42SStephen Warren val = tegra30_apbif_read(reg); 225be944d42SStephen Warren val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | 226be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK); 227be944d42SStephen Warren val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | 228be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN | 229be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16; 230be944d42SStephen Warren tegra30_apbif_write(reg, val); 231be944d42SStephen Warren 2325e049fceSStephen Warren cif_conf.threshold = 0; 2335e049fceSStephen Warren cif_conf.audio_channels = 2; 2345e049fceSStephen Warren cif_conf.client_channels = 2; 2355e049fceSStephen Warren cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; 2365e049fceSStephen Warren cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; 2375e049fceSStephen Warren cif_conf.expand = 0; 2385e049fceSStephen Warren cif_conf.stereo_conv = 0; 2395e049fceSStephen Warren cif_conf.replicate = 0; 2405e049fceSStephen Warren cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX; 2415e049fceSStephen Warren cif_conf.truncate = 0; 2425e049fceSStephen Warren cif_conf.mono_conv = 0; 2435e049fceSStephen Warren 244be944d42SStephen Warren reg = TEGRA30_AHUB_CIF_TX_CTRL + 245be944d42SStephen Warren (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); 2465e049fceSStephen Warren ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); 247be944d42SStephen Warren 248768db0b9SStephen Warren pm_runtime_put(ahub->dev); 249768db0b9SStephen Warren 250be944d42SStephen Warren return 0; 251be944d42SStephen Warren } 252be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo); 253be944d42SStephen Warren 254be944d42SStephen Warren int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif) 255be944d42SStephen Warren { 256be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 257be944d42SStephen Warren int reg, val; 258be944d42SStephen Warren 259768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 260768db0b9SStephen Warren 261be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 262be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 263be944d42SStephen Warren val = tegra30_apbif_read(reg); 264be944d42SStephen Warren val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 265be944d42SStephen Warren tegra30_apbif_write(reg, val); 266be944d42SStephen Warren 267768db0b9SStephen Warren pm_runtime_put(ahub->dev); 268768db0b9SStephen Warren 269be944d42SStephen Warren return 0; 270be944d42SStephen Warren } 271be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo); 272be944d42SStephen Warren 273be944d42SStephen Warren int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif) 274be944d42SStephen Warren { 275be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 276be944d42SStephen Warren int reg, val; 277be944d42SStephen Warren 278768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 279768db0b9SStephen Warren 280be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 281be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 282be944d42SStephen Warren val = tegra30_apbif_read(reg); 283be944d42SStephen Warren val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 284be944d42SStephen Warren tegra30_apbif_write(reg, val); 285be944d42SStephen Warren 286768db0b9SStephen Warren pm_runtime_put(ahub->dev); 287768db0b9SStephen Warren 288be944d42SStephen Warren return 0; 289be944d42SStephen Warren } 290be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo); 291be944d42SStephen Warren 292be944d42SStephen Warren int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif) 293be944d42SStephen Warren { 294be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 295be944d42SStephen Warren 296be944d42SStephen Warren __clear_bit(channel, ahub->tx_usage); 297be944d42SStephen Warren 298be944d42SStephen Warren return 0; 299be944d42SStephen Warren } 300be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo); 301be944d42SStephen Warren 302be944d42SStephen Warren int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, 303be944d42SStephen Warren enum tegra30_ahub_txcif txcif) 304be944d42SStephen Warren { 305be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 306be944d42SStephen Warren int reg; 307be944d42SStephen Warren 308768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 309768db0b9SStephen Warren 310be944d42SStephen Warren reg = TEGRA30_AHUB_AUDIO_RX + 311be944d42SStephen Warren (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 312be944d42SStephen Warren tegra30_audio_write(reg, 1 << txcif); 313be944d42SStephen Warren 314768db0b9SStephen Warren pm_runtime_put(ahub->dev); 315768db0b9SStephen Warren 316be944d42SStephen Warren return 0; 317be944d42SStephen Warren } 318be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source); 319be944d42SStephen Warren 320be944d42SStephen Warren int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif) 321be944d42SStephen Warren { 322be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 323be944d42SStephen Warren int reg; 324be944d42SStephen Warren 325768db0b9SStephen Warren pm_runtime_get_sync(ahub->dev); 326768db0b9SStephen Warren 327be944d42SStephen Warren reg = TEGRA30_AHUB_AUDIO_RX + 328be944d42SStephen Warren (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 329be944d42SStephen Warren tegra30_audio_write(reg, 0); 330be944d42SStephen Warren 331768db0b9SStephen Warren pm_runtime_put(ahub->dev); 332768db0b9SStephen Warren 333be944d42SStephen Warren return 0; 334be944d42SStephen Warren } 335be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source); 336be944d42SStephen Warren 3375185e0acSStephen Warren #define MOD_LIST_MASK_TEGRA30 BIT(0) 3385185e0acSStephen Warren #define MOD_LIST_MASK_TEGRA114 BIT(1) 339f1d6ff79SStephen Warren #define MOD_LIST_MASK_TEGRA124 BIT(2) 34095d36075SStephen Warren 3415185e0acSStephen Warren #define MOD_LIST_MASK_TEGRA30_OR_LATER \ 342f1d6ff79SStephen Warren (MOD_LIST_MASK_TEGRA30 | MOD_LIST_MASK_TEGRA114 | \ 343f1d6ff79SStephen Warren MOD_LIST_MASK_TEGRA124) 344f1d6ff79SStephen Warren #define MOD_LIST_MASK_TEGRA114_OR_LATER \ 345f1d6ff79SStephen Warren (MOD_LIST_MASK_TEGRA114 | MOD_LIST_MASK_TEGRA124) 34695d36075SStephen Warren 34795d36075SStephen Warren static const struct { 3485185e0acSStephen Warren const char *rst_name; 3495185e0acSStephen Warren u32 mod_list_mask; 3505185e0acSStephen Warren } configlink_mods[] = { 3515185e0acSStephen Warren { "i2s0", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3525185e0acSStephen Warren { "i2s1", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3535185e0acSStephen Warren { "i2s2", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3545185e0acSStephen Warren { "i2s3", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3555185e0acSStephen Warren { "i2s4", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3565185e0acSStephen Warren { "dam0", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3575185e0acSStephen Warren { "dam1", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3585185e0acSStephen Warren { "dam2", MOD_LIST_MASK_TEGRA30_OR_LATER }, 3595185e0acSStephen Warren { "spdif", MOD_LIST_MASK_TEGRA30_OR_LATER }, 360f1d6ff79SStephen Warren { "amx", MOD_LIST_MASK_TEGRA114_OR_LATER }, 361f1d6ff79SStephen Warren { "adx", MOD_LIST_MASK_TEGRA114_OR_LATER }, 362f1d6ff79SStephen Warren { "amx1", MOD_LIST_MASK_TEGRA124 }, 363f1d6ff79SStephen Warren { "adx1", MOD_LIST_MASK_TEGRA124 }, 364f1d6ff79SStephen Warren { "afc0", MOD_LIST_MASK_TEGRA124 }, 365f1d6ff79SStephen Warren { "afc1", MOD_LIST_MASK_TEGRA124 }, 366f1d6ff79SStephen Warren { "afc2", MOD_LIST_MASK_TEGRA124 }, 367f1d6ff79SStephen Warren { "afc3", MOD_LIST_MASK_TEGRA124 }, 368f1d6ff79SStephen Warren { "afc4", MOD_LIST_MASK_TEGRA124 }, 369f1d6ff79SStephen Warren { "afc5", MOD_LIST_MASK_TEGRA124 }, 370be944d42SStephen Warren }; 371be944d42SStephen Warren 372be944d42SStephen Warren #define LAST_REG(name) \ 373be944d42SStephen Warren (TEGRA30_AHUB_##name + \ 374be944d42SStephen Warren (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4) 375be944d42SStephen Warren 376be944d42SStephen Warren #define REG_IN_ARRAY(reg, name) \ 377be944d42SStephen Warren ((reg >= TEGRA30_AHUB_##name) && \ 378be944d42SStephen Warren (reg <= LAST_REG(name) && \ 379be944d42SStephen Warren (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE)))) 380be944d42SStephen Warren 381be944d42SStephen Warren static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) 382be944d42SStephen Warren { 383be944d42SStephen Warren switch (reg) { 384be944d42SStephen Warren case TEGRA30_AHUB_CONFIG_LINK_CTRL: 385be944d42SStephen Warren case TEGRA30_AHUB_MISC_CTRL: 386be944d42SStephen Warren case TEGRA30_AHUB_APBDMA_LIVE_STATUS: 387be944d42SStephen Warren case TEGRA30_AHUB_I2S_LIVE_STATUS: 388be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_LIVE_STATUS: 389be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_MASK: 390be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_MASK: 391be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_MASK: 392be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_MASK: 393be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_STATUS: 394be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_STATUS: 395be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_STATUS: 396be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_STATUS: 397be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SOURCE: 398be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SOURCE: 399be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SOURCE: 400be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SOURCE: 401be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SET: 402be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SET: 403be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SET: 404be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SET: 405be944d42SStephen Warren return true; 406be944d42SStephen Warren default: 407be944d42SStephen Warren break; 4081d198f26SJoe Perches } 409be944d42SStephen Warren 410be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || 411be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_CLEAR) || 412be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_STATUS) || 413be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 414be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || 415be944d42SStephen Warren REG_IN_ARRAY(reg, CIF_TX_CTRL) || 416be944d42SStephen Warren REG_IN_ARRAY(reg, CIF_RX_CTRL) || 417be944d42SStephen Warren REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) 418be944d42SStephen Warren return true; 419be944d42SStephen Warren 420be944d42SStephen Warren return false; 421be944d42SStephen Warren } 422be944d42SStephen Warren 423be944d42SStephen Warren static bool tegra30_ahub_apbif_volatile_reg(struct device *dev, 424be944d42SStephen Warren unsigned int reg) 425be944d42SStephen Warren { 426be944d42SStephen Warren switch (reg) { 427be944d42SStephen Warren case TEGRA30_AHUB_CONFIG_LINK_CTRL: 428be944d42SStephen Warren case TEGRA30_AHUB_MISC_CTRL: 429be944d42SStephen Warren case TEGRA30_AHUB_APBDMA_LIVE_STATUS: 430be944d42SStephen Warren case TEGRA30_AHUB_I2S_LIVE_STATUS: 431be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_LIVE_STATUS: 432be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_STATUS: 433be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_STATUS: 434be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_STATUS: 435be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_STATUS: 436be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SET: 437be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SET: 438be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SET: 439be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SET: 440be944d42SStephen Warren return true; 441be944d42SStephen Warren default: 442be944d42SStephen Warren break; 4431d198f26SJoe Perches } 444be944d42SStephen Warren 445be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || 446be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_STATUS) || 447be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 448be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || 449be944d42SStephen Warren REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) 450be944d42SStephen Warren return true; 451be944d42SStephen Warren 452be944d42SStephen Warren return false; 453be944d42SStephen Warren } 454be944d42SStephen Warren 455be944d42SStephen Warren static bool tegra30_ahub_apbif_precious_reg(struct device *dev, 456be944d42SStephen Warren unsigned int reg) 457be944d42SStephen Warren { 458be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 459be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) 460be944d42SStephen Warren return true; 461be944d42SStephen Warren 462be944d42SStephen Warren return false; 463be944d42SStephen Warren } 464be944d42SStephen Warren 465be944d42SStephen Warren static const struct regmap_config tegra30_ahub_apbif_regmap_config = { 466be944d42SStephen Warren .name = "apbif", 467be944d42SStephen Warren .reg_bits = 32, 468be944d42SStephen Warren .val_bits = 32, 469be944d42SStephen Warren .reg_stride = 4, 470be944d42SStephen Warren .max_register = TEGRA30_AHUB_APBIF_INT_SET, 471be944d42SStephen Warren .writeable_reg = tegra30_ahub_apbif_wr_rd_reg, 472be944d42SStephen Warren .readable_reg = tegra30_ahub_apbif_wr_rd_reg, 473be944d42SStephen Warren .volatile_reg = tegra30_ahub_apbif_volatile_reg, 474be944d42SStephen Warren .precious_reg = tegra30_ahub_apbif_precious_reg, 475591d14f0SDylan Reid .cache_type = REGCACHE_FLAT, 476be944d42SStephen Warren }; 477be944d42SStephen Warren 478be944d42SStephen Warren static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) 479be944d42SStephen Warren { 480be944d42SStephen Warren if (REG_IN_ARRAY(reg, AUDIO_RX)) 481be944d42SStephen Warren return true; 482be944d42SStephen Warren 483be944d42SStephen Warren return false; 484be944d42SStephen Warren } 485be944d42SStephen Warren 486be944d42SStephen Warren static const struct regmap_config tegra30_ahub_ahub_regmap_config = { 487be944d42SStephen Warren .name = "ahub", 488be944d42SStephen Warren .reg_bits = 32, 489be944d42SStephen Warren .val_bits = 32, 490be944d42SStephen Warren .reg_stride = 4, 491be944d42SStephen Warren .max_register = LAST_REG(AUDIO_RX), 492be944d42SStephen Warren .writeable_reg = tegra30_ahub_ahub_wr_rd_reg, 493be944d42SStephen Warren .readable_reg = tegra30_ahub_ahub_wr_rd_reg, 494591d14f0SDylan Reid .cache_type = REGCACHE_FLAT, 495be944d42SStephen Warren }; 496be944d42SStephen Warren 49795d36075SStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra30 = { 4985185e0acSStephen Warren .mod_list_mask = MOD_LIST_MASK_TEGRA30, 4995e049fceSStephen Warren .set_audio_cif = tegra30_ahub_set_cif, 50095d36075SStephen Warren }; 50195d36075SStephen Warren 50295d36075SStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra114 = { 5035185e0acSStephen Warren .mod_list_mask = MOD_LIST_MASK_TEGRA114, 5045e049fceSStephen Warren .set_audio_cif = tegra30_ahub_set_cif, 5055e049fceSStephen Warren }; 5065e049fceSStephen Warren 5075e049fceSStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra124 = { 508f1d6ff79SStephen Warren .mod_list_mask = MOD_LIST_MASK_TEGRA124, 5095e049fceSStephen Warren .set_audio_cif = tegra124_ahub_set_cif, 51095d36075SStephen Warren }; 51195d36075SStephen Warren 51295d36075SStephen Warren static const struct of_device_id tegra30_ahub_of_match[] = { 5135e049fceSStephen Warren { .compatible = "nvidia,tegra124-ahub", .data = &soc_data_tegra124 }, 51495d36075SStephen Warren { .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 }, 51595d36075SStephen Warren { .compatible = "nvidia,tegra30-ahub", .data = &soc_data_tegra30 }, 51695d36075SStephen Warren {}, 51795d36075SStephen Warren }; 51895d36075SStephen Warren 5194652a0d0SBill Pemberton static int tegra30_ahub_probe(struct platform_device *pdev) 520be944d42SStephen Warren { 52195d36075SStephen Warren const struct of_device_id *match; 52295d36075SStephen Warren const struct tegra30_ahub_soc_data *soc_data; 5235185e0acSStephen Warren struct reset_control *rst; 524be944d42SStephen Warren int i; 525f57ddcdfSAxel Lin struct resource *res0, *res1; 526be944d42SStephen Warren void __iomem *regs_apbif, *regs_ahub; 527be944d42SStephen Warren int ret = 0; 528be944d42SStephen Warren 529be944d42SStephen Warren if (ahub) 530be944d42SStephen Warren return -ENODEV; 531be944d42SStephen Warren 53295d36075SStephen Warren match = of_match_device(tegra30_ahub_of_match, &pdev->dev); 53395d36075SStephen Warren if (!match) 53495d36075SStephen Warren return -EINVAL; 53595d36075SStephen Warren soc_data = match->data; 53695d36075SStephen Warren 537be944d42SStephen Warren /* 538be944d42SStephen Warren * The AHUB hosts a register bus: the "configlink". For this to 539be944d42SStephen Warren * operate correctly, all devices on this bus must be out of reset. 540be944d42SStephen Warren * Ensure that here. 541be944d42SStephen Warren */ 5425185e0acSStephen Warren for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) { 5435185e0acSStephen Warren if (!(configlink_mods[i].mod_list_mask & 5445185e0acSStephen Warren soc_data->mod_list_mask)) 54595d36075SStephen Warren continue; 5465185e0acSStephen Warren 5475185e0acSStephen Warren rst = reset_control_get(&pdev->dev, 5485185e0acSStephen Warren configlink_mods[i].rst_name); 5495185e0acSStephen Warren if (IS_ERR(rst)) { 5505185e0acSStephen Warren dev_err(&pdev->dev, "Can't get reset %s\n", 5515185e0acSStephen Warren configlink_mods[i].rst_name); 5525185e0acSStephen Warren ret = PTR_ERR(rst); 5538833c01aSVaishali Thakkar return ret; 554be944d42SStephen Warren } 5555185e0acSStephen Warren 5565185e0acSStephen Warren ret = reset_control_deassert(rst); 5575185e0acSStephen Warren reset_control_put(rst); 5585185e0acSStephen Warren if (ret) 5598833c01aSVaishali Thakkar return ret; 560be944d42SStephen Warren } 561be944d42SStephen Warren 562be944d42SStephen Warren ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub), 563be944d42SStephen Warren GFP_KERNEL); 564e2c187a6SCodrut Grosu if (!ahub) 5658833c01aSVaishali Thakkar return -ENOMEM; 566be944d42SStephen Warren dev_set_drvdata(&pdev->dev, ahub); 567be944d42SStephen Warren 5685e049fceSStephen Warren ahub->soc_data = soc_data; 569be944d42SStephen Warren ahub->dev = &pdev->dev; 570be944d42SStephen Warren 5718833c01aSVaishali Thakkar ahub->clk_d_audio = devm_clk_get(&pdev->dev, "d_audio"); 572be944d42SStephen Warren if (IS_ERR(ahub->clk_d_audio)) { 573be944d42SStephen Warren dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n"); 574be944d42SStephen Warren ret = PTR_ERR(ahub->clk_d_audio); 5758833c01aSVaishali Thakkar return ret; 576be944d42SStephen Warren } 577be944d42SStephen Warren 5788833c01aSVaishali Thakkar ahub->clk_apbif = devm_clk_get(&pdev->dev, "apbif"); 579be944d42SStephen Warren if (IS_ERR(ahub->clk_apbif)) { 580be944d42SStephen Warren dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n"); 581be944d42SStephen Warren ret = PTR_ERR(ahub->clk_apbif); 5828833c01aSVaishali Thakkar return ret; 583be944d42SStephen Warren } 584be944d42SStephen Warren 585be944d42SStephen Warren res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 586f57ddcdfSAxel Lin regs_apbif = devm_ioremap_resource(&pdev->dev, res0); 587f57ddcdfSAxel Lin if (IS_ERR(regs_apbif)) 588f57ddcdfSAxel Lin return PTR_ERR(regs_apbif); 589be944d42SStephen Warren 590be944d42SStephen Warren ahub->apbif_addr = res0->start; 591be944d42SStephen Warren 592be944d42SStephen Warren ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif, 593be944d42SStephen Warren &tegra30_ahub_apbif_regmap_config); 594be944d42SStephen Warren if (IS_ERR(ahub->regmap_apbif)) { 595be944d42SStephen Warren dev_err(&pdev->dev, "apbif regmap init failed\n"); 596be944d42SStephen Warren ret = PTR_ERR(ahub->regmap_apbif); 5978833c01aSVaishali Thakkar return ret; 598be944d42SStephen Warren } 599be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, true); 600be944d42SStephen Warren 601be944d42SStephen Warren res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); 602f57ddcdfSAxel Lin regs_ahub = devm_ioremap_resource(&pdev->dev, res1); 603f57ddcdfSAxel Lin if (IS_ERR(regs_ahub)) 604f57ddcdfSAxel Lin return PTR_ERR(regs_ahub); 605be944d42SStephen Warren 606be944d42SStephen Warren ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub, 607be944d42SStephen Warren &tegra30_ahub_ahub_regmap_config); 608be944d42SStephen Warren if (IS_ERR(ahub->regmap_ahub)) { 609be944d42SStephen Warren dev_err(&pdev->dev, "ahub regmap init failed\n"); 610be944d42SStephen Warren ret = PTR_ERR(ahub->regmap_ahub); 6118833c01aSVaishali Thakkar return ret; 612be944d42SStephen Warren } 613be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, true); 614be944d42SStephen Warren 615be944d42SStephen Warren pm_runtime_enable(&pdev->dev); 616be944d42SStephen Warren if (!pm_runtime_enabled(&pdev->dev)) { 617be944d42SStephen Warren ret = tegra30_ahub_runtime_resume(&pdev->dev); 618be944d42SStephen Warren if (ret) 619be944d42SStephen Warren goto err_pm_disable; 620be944d42SStephen Warren } 621be944d42SStephen Warren 62279cf5918SPrashant Gaikwad of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 623be944d42SStephen Warren 624be944d42SStephen Warren return 0; 625be944d42SStephen Warren 626be944d42SStephen Warren err_pm_disable: 627be944d42SStephen Warren pm_runtime_disable(&pdev->dev); 6288833c01aSVaishali Thakkar 629be944d42SStephen Warren return ret; 630be944d42SStephen Warren } 631be944d42SStephen Warren 6324652a0d0SBill Pemberton static int tegra30_ahub_remove(struct platform_device *pdev) 633be944d42SStephen Warren { 634be944d42SStephen Warren if (!ahub) 635be944d42SStephen Warren return -ENODEV; 636be944d42SStephen Warren 637be944d42SStephen Warren pm_runtime_disable(&pdev->dev); 638be944d42SStephen Warren if (!pm_runtime_status_suspended(&pdev->dev)) 639be944d42SStephen Warren tegra30_ahub_runtime_suspend(&pdev->dev); 640be944d42SStephen Warren 641be944d42SStephen Warren return 0; 642be944d42SStephen Warren } 643be944d42SStephen Warren 6442f41a3f4SStephen Warren #ifdef CONFIG_PM_SLEEP 6452f41a3f4SStephen Warren static int tegra30_ahub_suspend(struct device *dev) 6462f41a3f4SStephen Warren { 6472f41a3f4SStephen Warren regcache_mark_dirty(ahub->regmap_ahub); 6482f41a3f4SStephen Warren regcache_mark_dirty(ahub->regmap_apbif); 6492f41a3f4SStephen Warren 6502f41a3f4SStephen Warren return 0; 6512f41a3f4SStephen Warren } 6522f41a3f4SStephen Warren 6532f41a3f4SStephen Warren static int tegra30_ahub_resume(struct device *dev) 6542f41a3f4SStephen Warren { 6552f41a3f4SStephen Warren int ret; 6562f41a3f4SStephen Warren 657249e66c3SStephen Warren ret = pm_runtime_get_sync(dev); 658249e66c3SStephen Warren if (ret < 0) 659249e66c3SStephen Warren return ret; 6602f41a3f4SStephen Warren ret = regcache_sync(ahub->regmap_ahub); 6612f41a3f4SStephen Warren ret |= regcache_sync(ahub->regmap_apbif); 662249e66c3SStephen Warren pm_runtime_put(dev); 6632f41a3f4SStephen Warren 6642f41a3f4SStephen Warren return ret; 6652f41a3f4SStephen Warren } 6662f41a3f4SStephen Warren #endif 6672f41a3f4SStephen Warren 668f6e65744SBill Pemberton static const struct dev_pm_ops tegra30_ahub_pm_ops = { 669be944d42SStephen Warren SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend, 670be944d42SStephen Warren tegra30_ahub_runtime_resume, NULL) 6712f41a3f4SStephen Warren SET_SYSTEM_SLEEP_PM_OPS(tegra30_ahub_suspend, tegra30_ahub_resume) 672be944d42SStephen Warren }; 673be944d42SStephen Warren 674be944d42SStephen Warren static struct platform_driver tegra30_ahub_driver = { 675be944d42SStephen Warren .probe = tegra30_ahub_probe, 6764652a0d0SBill Pemberton .remove = tegra30_ahub_remove, 677be944d42SStephen Warren .driver = { 678be944d42SStephen Warren .name = DRV_NAME, 679be944d42SStephen Warren .of_match_table = tegra30_ahub_of_match, 680be944d42SStephen Warren .pm = &tegra30_ahub_pm_ops, 681be944d42SStephen Warren }, 682be944d42SStephen Warren }; 683be944d42SStephen Warren module_platform_driver(tegra30_ahub_driver); 684be944d42SStephen Warren 6855e049fceSStephen Warren void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, 6865e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf) 6875e049fceSStephen Warren { 6885e049fceSStephen Warren unsigned int value; 6895e049fceSStephen Warren 6905e049fceSStephen Warren value = (conf->threshold << 6915e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 6925e049fceSStephen Warren ((conf->audio_channels - 1) << 6935e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 6945e049fceSStephen Warren ((conf->client_channels - 1) << 6955e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 6965e049fceSStephen Warren (conf->audio_bits << 6975e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | 6985e049fceSStephen Warren (conf->client_bits << 6995e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | 7005e049fceSStephen Warren (conf->expand << 7015e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | 7025e049fceSStephen Warren (conf->stereo_conv << 7035e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | 7045e049fceSStephen Warren (conf->replicate << 7055e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) | 7065e049fceSStephen Warren (conf->direction << 7075e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | 7085e049fceSStephen Warren (conf->truncate << 7095e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | 7105e049fceSStephen Warren (conf->mono_conv << 7115e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT); 7125e049fceSStephen Warren 7135e049fceSStephen Warren regmap_write(regmap, reg, value); 7145e049fceSStephen Warren } 7155e049fceSStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_set_cif); 7165e049fceSStephen Warren 7175e049fceSStephen Warren void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, 7185e049fceSStephen Warren struct tegra30_ahub_cif_conf *conf) 7195e049fceSStephen Warren { 7205e049fceSStephen Warren unsigned int value; 7215e049fceSStephen Warren 7225e049fceSStephen Warren value = (conf->threshold << 7235e049fceSStephen Warren TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 7245e049fceSStephen Warren ((conf->audio_channels - 1) << 7255e049fceSStephen Warren TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 7265e049fceSStephen Warren ((conf->client_channels - 1) << 7275e049fceSStephen Warren TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 7285e049fceSStephen Warren (conf->audio_bits << 7295e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | 7305e049fceSStephen Warren (conf->client_bits << 7315e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | 7325e049fceSStephen Warren (conf->expand << 7335e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | 7345e049fceSStephen Warren (conf->stereo_conv << 7355e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | 7365e049fceSStephen Warren (conf->replicate << 7375e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) | 7385e049fceSStephen Warren (conf->direction << 7395e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | 7405e049fceSStephen Warren (conf->truncate << 7415e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | 7425e049fceSStephen Warren (conf->mono_conv << 7435e049fceSStephen Warren TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT); 7445e049fceSStephen Warren 7455e049fceSStephen Warren regmap_write(regmap, reg, value); 7465e049fceSStephen Warren } 7475e049fceSStephen Warren EXPORT_SYMBOL_GPL(tegra124_ahub_set_cif); 7485e049fceSStephen Warren 749be944d42SStephen Warren MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 750be944d42SStephen Warren MODULE_DESCRIPTION("Tegra30 AHUB driver"); 751be944d42SStephen Warren MODULE_LICENSE("GPL v2"); 752be944d42SStephen Warren MODULE_ALIAS("platform:" DRV_NAME); 75369c5b753SStephen Warren MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match); 754