1be944d42SStephen Warren /* 2be944d42SStephen Warren * tegra30_ahub.c - Tegra30 AHUB driver 3be944d42SStephen Warren * 4be944d42SStephen Warren * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. 5be944d42SStephen Warren * 6be944d42SStephen Warren * This program is free software; you can redistribute it and/or modify it 7be944d42SStephen Warren * under the terms and conditions of the GNU General Public License, 8be944d42SStephen Warren * version 2, as published by the Free Software Foundation. 9be944d42SStephen Warren * 10be944d42SStephen Warren * This program is distributed in the hope it will be useful, but WITHOUT 11be944d42SStephen Warren * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12be944d42SStephen Warren * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13be944d42SStephen Warren * more details. 14be944d42SStephen Warren * 15be944d42SStephen Warren * You should have received a copy of the GNU General Public License 16be944d42SStephen Warren * along with this program. If not, see <http://www.gnu.org/licenses/>. 17be944d42SStephen Warren */ 18be944d42SStephen Warren 19be944d42SStephen Warren #include <linux/clk.h> 20be944d42SStephen Warren #include <linux/device.h> 21be944d42SStephen Warren #include <linux/io.h> 22be944d42SStephen Warren #include <linux/module.h> 23be944d42SStephen Warren #include <linux/of_platform.h> 24be944d42SStephen Warren #include <linux/platform_device.h> 25be944d42SStephen Warren #include <linux/pm_runtime.h> 26be944d42SStephen Warren #include <linux/regmap.h> 27be944d42SStephen Warren #include <linux/slab.h> 2861fd290dSPrashant Gaikwad #include <linux/clk/tegra.h> 29be944d42SStephen Warren #include <sound/soc.h> 30be944d42SStephen Warren #include "tegra30_ahub.h" 31be944d42SStephen Warren 32be944d42SStephen Warren #define DRV_NAME "tegra30-ahub" 33be944d42SStephen Warren 34be944d42SStephen Warren static struct tegra30_ahub *ahub; 35be944d42SStephen Warren 36be944d42SStephen Warren static inline void tegra30_apbif_write(u32 reg, u32 val) 37be944d42SStephen Warren { 38be944d42SStephen Warren regmap_write(ahub->regmap_apbif, reg, val); 39be944d42SStephen Warren } 40be944d42SStephen Warren 41be944d42SStephen Warren static inline u32 tegra30_apbif_read(u32 reg) 42be944d42SStephen Warren { 43be944d42SStephen Warren u32 val; 44be944d42SStephen Warren regmap_read(ahub->regmap_apbif, reg, &val); 45be944d42SStephen Warren return val; 46be944d42SStephen Warren } 47be944d42SStephen Warren 48be944d42SStephen Warren static inline void tegra30_audio_write(u32 reg, u32 val) 49be944d42SStephen Warren { 50be944d42SStephen Warren regmap_write(ahub->regmap_ahub, reg, val); 51be944d42SStephen Warren } 52be944d42SStephen Warren 53be944d42SStephen Warren static int tegra30_ahub_runtime_suspend(struct device *dev) 54be944d42SStephen Warren { 55be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, true); 56be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, true); 57be944d42SStephen Warren 5865d2bdd3SPrashant Gaikwad clk_disable_unprepare(ahub->clk_apbif); 5965d2bdd3SPrashant Gaikwad clk_disable_unprepare(ahub->clk_d_audio); 60be944d42SStephen Warren 61be944d42SStephen Warren return 0; 62be944d42SStephen Warren } 63be944d42SStephen Warren 64be944d42SStephen Warren /* 65be944d42SStephen Warren * clk_apbif isn't required for an I2S<->I2S configuration where no PCM data 66be944d42SStephen Warren * is read from or sent to memory. However, that's not something the rest of 67be944d42SStephen Warren * the driver supports right now, so we'll just treat the two clocks as one 68be944d42SStephen Warren * for now. 69be944d42SStephen Warren * 70be944d42SStephen Warren * These functions should not be a plain ref-count. Instead, each active stream 71be944d42SStephen Warren * contributes some requirement to the minimum clock rate, so starting or 72be944d42SStephen Warren * stopping streams should dynamically adjust the clock as required. However, 73be944d42SStephen Warren * this is not yet implemented. 74be944d42SStephen Warren */ 75be944d42SStephen Warren static int tegra30_ahub_runtime_resume(struct device *dev) 76be944d42SStephen Warren { 77be944d42SStephen Warren int ret; 78be944d42SStephen Warren 7965d2bdd3SPrashant Gaikwad ret = clk_prepare_enable(ahub->clk_d_audio); 80be944d42SStephen Warren if (ret) { 81be944d42SStephen Warren dev_err(dev, "clk_enable d_audio failed: %d\n", ret); 82be944d42SStephen Warren return ret; 83be944d42SStephen Warren } 8465d2bdd3SPrashant Gaikwad ret = clk_prepare_enable(ahub->clk_apbif); 85be944d42SStephen Warren if (ret) { 86be944d42SStephen Warren dev_err(dev, "clk_enable apbif failed: %d\n", ret); 87be944d42SStephen Warren clk_disable(ahub->clk_d_audio); 88be944d42SStephen Warren return ret; 89be944d42SStephen Warren } 90be944d42SStephen Warren 91be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, false); 92be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, false); 93be944d42SStephen Warren 94be944d42SStephen Warren return 0; 95be944d42SStephen Warren } 96be944d42SStephen Warren 97be944d42SStephen Warren int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 983489d506SLars-Peter Clausen dma_addr_t *fiforeg, 993489d506SLars-Peter Clausen unsigned int *reqsel) 100be944d42SStephen Warren { 101be944d42SStephen Warren int channel; 102be944d42SStephen Warren u32 reg, val; 103be944d42SStephen Warren 104be944d42SStephen Warren channel = find_first_zero_bit(ahub->rx_usage, 105be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 106be944d42SStephen Warren if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) 107be944d42SStephen Warren return -EBUSY; 108be944d42SStephen Warren 109be944d42SStephen Warren __set_bit(channel, ahub->rx_usage); 110be944d42SStephen Warren 111be944d42SStephen Warren *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel; 112be944d42SStephen Warren *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO + 113be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE); 114be944d42SStephen Warren *reqsel = ahub->dma_sel + channel; 115be944d42SStephen Warren 116be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 117be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 118be944d42SStephen Warren val = tegra30_apbif_read(reg); 119be944d42SStephen Warren val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | 120be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK); 121be944d42SStephen Warren val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | 122be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN | 123be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16; 124be944d42SStephen Warren tegra30_apbif_write(reg, val); 125be944d42SStephen Warren 126be944d42SStephen Warren reg = TEGRA30_AHUB_CIF_RX_CTRL + 127be944d42SStephen Warren (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); 128be944d42SStephen Warren val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 129be944d42SStephen Warren (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 130be944d42SStephen Warren (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 131be944d42SStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 | 132be944d42SStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 | 133be944d42SStephen Warren TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX; 134be944d42SStephen Warren tegra30_apbif_write(reg, val); 135be944d42SStephen Warren 136be944d42SStephen Warren return 0; 137be944d42SStephen Warren } 138be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo); 139be944d42SStephen Warren 140be944d42SStephen Warren int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif) 141be944d42SStephen Warren { 142be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 143be944d42SStephen Warren int reg, val; 144be944d42SStephen Warren 145be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 146be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 147be944d42SStephen Warren val = tegra30_apbif_read(reg); 148be944d42SStephen Warren val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 149be944d42SStephen Warren tegra30_apbif_write(reg, val); 150be944d42SStephen Warren 151be944d42SStephen Warren return 0; 152be944d42SStephen Warren } 153be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo); 154be944d42SStephen Warren 155be944d42SStephen Warren int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif) 156be944d42SStephen Warren { 157be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 158be944d42SStephen Warren int reg, val; 159be944d42SStephen Warren 160be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 161be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 162be944d42SStephen Warren val = tegra30_apbif_read(reg); 163be944d42SStephen Warren val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 164be944d42SStephen Warren tegra30_apbif_write(reg, val); 165be944d42SStephen Warren 166be944d42SStephen Warren return 0; 167be944d42SStephen Warren } 168be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo); 169be944d42SStephen Warren 170be944d42SStephen Warren int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif) 171be944d42SStephen Warren { 172be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 173be944d42SStephen Warren 174be944d42SStephen Warren __clear_bit(channel, ahub->rx_usage); 175be944d42SStephen Warren 176be944d42SStephen Warren return 0; 177be944d42SStephen Warren } 178be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo); 179be944d42SStephen Warren 180be944d42SStephen Warren int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 1813489d506SLars-Peter Clausen dma_addr_t *fiforeg, 1823489d506SLars-Peter Clausen unsigned int *reqsel) 183be944d42SStephen Warren { 184be944d42SStephen Warren int channel; 185be944d42SStephen Warren u32 reg, val; 186be944d42SStephen Warren 187be944d42SStephen Warren channel = find_first_zero_bit(ahub->tx_usage, 188be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_COUNT); 189be944d42SStephen Warren if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) 190be944d42SStephen Warren return -EBUSY; 191be944d42SStephen Warren 192be944d42SStephen Warren __set_bit(channel, ahub->tx_usage); 193be944d42SStephen Warren 194be944d42SStephen Warren *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel; 195be944d42SStephen Warren *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO + 196be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE); 197be944d42SStephen Warren *reqsel = ahub->dma_sel + channel; 198be944d42SStephen Warren 199be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 200be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 201be944d42SStephen Warren val = tegra30_apbif_read(reg); 202be944d42SStephen Warren val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | 203be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK); 204be944d42SStephen Warren val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | 205be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN | 206be944d42SStephen Warren TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16; 207be944d42SStephen Warren tegra30_apbif_write(reg, val); 208be944d42SStephen Warren 209be944d42SStephen Warren reg = TEGRA30_AHUB_CIF_TX_CTRL + 210be944d42SStephen Warren (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); 211be944d42SStephen Warren val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | 212be944d42SStephen Warren (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | 213be944d42SStephen Warren (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | 214be944d42SStephen Warren TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 | 215be944d42SStephen Warren TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 | 216be944d42SStephen Warren TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX; 217be944d42SStephen Warren tegra30_apbif_write(reg, val); 218be944d42SStephen Warren 219be944d42SStephen Warren return 0; 220be944d42SStephen Warren } 221be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo); 222be944d42SStephen Warren 223be944d42SStephen Warren int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif) 224be944d42SStephen Warren { 225be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 226be944d42SStephen Warren int reg, val; 227be944d42SStephen Warren 228be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 229be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 230be944d42SStephen Warren val = tegra30_apbif_read(reg); 231be944d42SStephen Warren val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 232be944d42SStephen Warren tegra30_apbif_write(reg, val); 233be944d42SStephen Warren 234be944d42SStephen Warren return 0; 235be944d42SStephen Warren } 236be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo); 237be944d42SStephen Warren 238be944d42SStephen Warren int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif) 239be944d42SStephen Warren { 240be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 241be944d42SStephen Warren int reg, val; 242be944d42SStephen Warren 243be944d42SStephen Warren reg = TEGRA30_AHUB_CHANNEL_CTRL + 244be944d42SStephen Warren (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 245be944d42SStephen Warren val = tegra30_apbif_read(reg); 246be944d42SStephen Warren val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 247be944d42SStephen Warren tegra30_apbif_write(reg, val); 248be944d42SStephen Warren 249be944d42SStephen Warren return 0; 250be944d42SStephen Warren } 251be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo); 252be944d42SStephen Warren 253be944d42SStephen Warren int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif) 254be944d42SStephen Warren { 255be944d42SStephen Warren int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 256be944d42SStephen Warren 257be944d42SStephen Warren __clear_bit(channel, ahub->tx_usage); 258be944d42SStephen Warren 259be944d42SStephen Warren return 0; 260be944d42SStephen Warren } 261be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo); 262be944d42SStephen Warren 263be944d42SStephen Warren int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, 264be944d42SStephen Warren enum tegra30_ahub_txcif txcif) 265be944d42SStephen Warren { 266be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 267be944d42SStephen Warren int reg; 268be944d42SStephen Warren 269be944d42SStephen Warren reg = TEGRA30_AHUB_AUDIO_RX + 270be944d42SStephen Warren (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 271be944d42SStephen Warren tegra30_audio_write(reg, 1 << txcif); 272be944d42SStephen Warren 273be944d42SStephen Warren return 0; 274be944d42SStephen Warren } 275be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source); 276be944d42SStephen Warren 277be944d42SStephen Warren int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif) 278be944d42SStephen Warren { 279be944d42SStephen Warren int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 280be944d42SStephen Warren int reg; 281be944d42SStephen Warren 282be944d42SStephen Warren reg = TEGRA30_AHUB_AUDIO_RX + 283be944d42SStephen Warren (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 284be944d42SStephen Warren tegra30_audio_write(reg, 0); 285be944d42SStephen Warren 286be944d42SStephen Warren return 0; 287be944d42SStephen Warren } 288be944d42SStephen Warren EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source); 289be944d42SStephen Warren 29095d36075SStephen Warren #define CLK_LIST_MASK_TEGRA30 BIT(0) 29195d36075SStephen Warren #define CLK_LIST_MASK_TEGRA114 BIT(1) 29295d36075SStephen Warren 29395d36075SStephen Warren #define CLK_LIST_MASK_TEGRA30_OR_LATER \ 29495d36075SStephen Warren (CLK_LIST_MASK_TEGRA30 | CLK_LIST_MASK_TEGRA114) 29595d36075SStephen Warren 29695d36075SStephen Warren static const struct { 29795d36075SStephen Warren const char *clk_name; 29895d36075SStephen Warren u32 clk_list_mask; 29995d36075SStephen Warren } configlink_clocks[] = { 30095d36075SStephen Warren { "i2s0", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30195d36075SStephen Warren { "i2s1", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30295d36075SStephen Warren { "i2s2", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30395d36075SStephen Warren { "i2s3", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30495d36075SStephen Warren { "i2s4", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30595d36075SStephen Warren { "dam0", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30695d36075SStephen Warren { "dam1", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30795d36075SStephen Warren { "dam2", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30895d36075SStephen Warren { "spdif_in", CLK_LIST_MASK_TEGRA30_OR_LATER }, 30995d36075SStephen Warren { "amx", CLK_LIST_MASK_TEGRA114 }, 31095d36075SStephen Warren { "adx", CLK_LIST_MASK_TEGRA114 }, 311be944d42SStephen Warren }; 312be944d42SStephen Warren 313be944d42SStephen Warren #define LAST_REG(name) \ 314be944d42SStephen Warren (TEGRA30_AHUB_##name + \ 315be944d42SStephen Warren (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4) 316be944d42SStephen Warren 317be944d42SStephen Warren #define REG_IN_ARRAY(reg, name) \ 318be944d42SStephen Warren ((reg >= TEGRA30_AHUB_##name) && \ 319be944d42SStephen Warren (reg <= LAST_REG(name) && \ 320be944d42SStephen Warren (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE)))) 321be944d42SStephen Warren 322be944d42SStephen Warren static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) 323be944d42SStephen Warren { 324be944d42SStephen Warren switch (reg) { 325be944d42SStephen Warren case TEGRA30_AHUB_CONFIG_LINK_CTRL: 326be944d42SStephen Warren case TEGRA30_AHUB_MISC_CTRL: 327be944d42SStephen Warren case TEGRA30_AHUB_APBDMA_LIVE_STATUS: 328be944d42SStephen Warren case TEGRA30_AHUB_I2S_LIVE_STATUS: 329be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_LIVE_STATUS: 330be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_MASK: 331be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_MASK: 332be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_MASK: 333be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_MASK: 334be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_STATUS: 335be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_STATUS: 336be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_STATUS: 337be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_STATUS: 338be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SOURCE: 339be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SOURCE: 340be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SOURCE: 341be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SOURCE: 342be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SET: 343be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SET: 344be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SET: 345be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SET: 346be944d42SStephen Warren return true; 347be944d42SStephen Warren default: 348be944d42SStephen Warren break; 349be944d42SStephen Warren }; 350be944d42SStephen Warren 351be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || 352be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_CLEAR) || 353be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_STATUS) || 354be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 355be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || 356be944d42SStephen Warren REG_IN_ARRAY(reg, CIF_TX_CTRL) || 357be944d42SStephen Warren REG_IN_ARRAY(reg, CIF_RX_CTRL) || 358be944d42SStephen Warren REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) 359be944d42SStephen Warren return true; 360be944d42SStephen Warren 361be944d42SStephen Warren return false; 362be944d42SStephen Warren } 363be944d42SStephen Warren 364be944d42SStephen Warren static bool tegra30_ahub_apbif_volatile_reg(struct device *dev, 365be944d42SStephen Warren unsigned int reg) 366be944d42SStephen Warren { 367be944d42SStephen Warren switch (reg) { 368be944d42SStephen Warren case TEGRA30_AHUB_CONFIG_LINK_CTRL: 369be944d42SStephen Warren case TEGRA30_AHUB_MISC_CTRL: 370be944d42SStephen Warren case TEGRA30_AHUB_APBDMA_LIVE_STATUS: 371be944d42SStephen Warren case TEGRA30_AHUB_I2S_LIVE_STATUS: 372be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_LIVE_STATUS: 373be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_STATUS: 374be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_STATUS: 375be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_STATUS: 376be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_STATUS: 377be944d42SStephen Warren case TEGRA30_AHUB_I2S_INT_SET: 378be944d42SStephen Warren case TEGRA30_AHUB_DAM_INT_SET: 379be944d42SStephen Warren case TEGRA30_AHUB_SPDIF_INT_SET: 380be944d42SStephen Warren case TEGRA30_AHUB_APBIF_INT_SET: 381be944d42SStephen Warren return true; 382be944d42SStephen Warren default: 383be944d42SStephen Warren break; 384be944d42SStephen Warren }; 385be944d42SStephen Warren 386be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || 387be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_STATUS) || 388be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 389be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || 390be944d42SStephen Warren REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) 391be944d42SStephen Warren return true; 392be944d42SStephen Warren 393be944d42SStephen Warren return false; 394be944d42SStephen Warren } 395be944d42SStephen Warren 396be944d42SStephen Warren static bool tegra30_ahub_apbif_precious_reg(struct device *dev, 397be944d42SStephen Warren unsigned int reg) 398be944d42SStephen Warren { 399be944d42SStephen Warren if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || 400be944d42SStephen Warren REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) 401be944d42SStephen Warren return true; 402be944d42SStephen Warren 403be944d42SStephen Warren return false; 404be944d42SStephen Warren } 405be944d42SStephen Warren 406be944d42SStephen Warren static const struct regmap_config tegra30_ahub_apbif_regmap_config = { 407be944d42SStephen Warren .name = "apbif", 408be944d42SStephen Warren .reg_bits = 32, 409be944d42SStephen Warren .val_bits = 32, 410be944d42SStephen Warren .reg_stride = 4, 411be944d42SStephen Warren .max_register = TEGRA30_AHUB_APBIF_INT_SET, 412be944d42SStephen Warren .writeable_reg = tegra30_ahub_apbif_wr_rd_reg, 413be944d42SStephen Warren .readable_reg = tegra30_ahub_apbif_wr_rd_reg, 414be944d42SStephen Warren .volatile_reg = tegra30_ahub_apbif_volatile_reg, 415be944d42SStephen Warren .precious_reg = tegra30_ahub_apbif_precious_reg, 416be944d42SStephen Warren .cache_type = REGCACHE_RBTREE, 417be944d42SStephen Warren }; 418be944d42SStephen Warren 419be944d42SStephen Warren static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) 420be944d42SStephen Warren { 421be944d42SStephen Warren if (REG_IN_ARRAY(reg, AUDIO_RX)) 422be944d42SStephen Warren return true; 423be944d42SStephen Warren 424be944d42SStephen Warren return false; 425be944d42SStephen Warren } 426be944d42SStephen Warren 427be944d42SStephen Warren static const struct regmap_config tegra30_ahub_ahub_regmap_config = { 428be944d42SStephen Warren .name = "ahub", 429be944d42SStephen Warren .reg_bits = 32, 430be944d42SStephen Warren .val_bits = 32, 431be944d42SStephen Warren .reg_stride = 4, 432be944d42SStephen Warren .max_register = LAST_REG(AUDIO_RX), 433be944d42SStephen Warren .writeable_reg = tegra30_ahub_ahub_wr_rd_reg, 434be944d42SStephen Warren .readable_reg = tegra30_ahub_ahub_wr_rd_reg, 435be944d42SStephen Warren .cache_type = REGCACHE_RBTREE, 436be944d42SStephen Warren }; 437be944d42SStephen Warren 43895d36075SStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra30 = { 43995d36075SStephen Warren .clk_list_mask = CLK_LIST_MASK_TEGRA30, 44095d36075SStephen Warren }; 44195d36075SStephen Warren 44295d36075SStephen Warren static struct tegra30_ahub_soc_data soc_data_tegra114 = { 44395d36075SStephen Warren .clk_list_mask = CLK_LIST_MASK_TEGRA114, 44495d36075SStephen Warren }; 44595d36075SStephen Warren 44695d36075SStephen Warren static const struct of_device_id tegra30_ahub_of_match[] = { 44795d36075SStephen Warren { .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 }, 44895d36075SStephen Warren { .compatible = "nvidia,tegra30-ahub", .data = &soc_data_tegra30 }, 44995d36075SStephen Warren {}, 45095d36075SStephen Warren }; 45195d36075SStephen Warren 4524652a0d0SBill Pemberton static int tegra30_ahub_probe(struct platform_device *pdev) 453be944d42SStephen Warren { 45495d36075SStephen Warren const struct of_device_id *match; 45595d36075SStephen Warren const struct tegra30_ahub_soc_data *soc_data; 456be944d42SStephen Warren struct clk *clk; 457be944d42SStephen Warren int i; 458be944d42SStephen Warren struct resource *res0, *res1, *region; 459be944d42SStephen Warren u32 of_dma[2]; 460be944d42SStephen Warren void __iomem *regs_apbif, *regs_ahub; 461be944d42SStephen Warren int ret = 0; 462be944d42SStephen Warren 463be944d42SStephen Warren if (ahub) 464be944d42SStephen Warren return -ENODEV; 465be944d42SStephen Warren 46695d36075SStephen Warren match = of_match_device(tegra30_ahub_of_match, &pdev->dev); 46795d36075SStephen Warren if (!match) 46895d36075SStephen Warren return -EINVAL; 46995d36075SStephen Warren soc_data = match->data; 47095d36075SStephen Warren 471be944d42SStephen Warren /* 472be944d42SStephen Warren * The AHUB hosts a register bus: the "configlink". For this to 473be944d42SStephen Warren * operate correctly, all devices on this bus must be out of reset. 474be944d42SStephen Warren * Ensure that here. 475be944d42SStephen Warren */ 476be944d42SStephen Warren for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) { 47795d36075SStephen Warren if (!(configlink_clocks[i].clk_list_mask & 47895d36075SStephen Warren soc_data->clk_list_mask)) 47995d36075SStephen Warren continue; 48095d36075SStephen Warren clk = clk_get(&pdev->dev, configlink_clocks[i].clk_name); 481be944d42SStephen Warren if (IS_ERR(clk)) { 482be944d42SStephen Warren dev_err(&pdev->dev, "Can't get clock %s\n", 48395d36075SStephen Warren configlink_clocks[i].clk_name); 484be944d42SStephen Warren ret = PTR_ERR(clk); 485be944d42SStephen Warren goto err; 486be944d42SStephen Warren } 487be944d42SStephen Warren tegra_periph_reset_deassert(clk); 488be944d42SStephen Warren clk_put(clk); 489be944d42SStephen Warren } 490be944d42SStephen Warren 491be944d42SStephen Warren ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub), 492be944d42SStephen Warren GFP_KERNEL); 493be944d42SStephen Warren if (!ahub) { 494be944d42SStephen Warren dev_err(&pdev->dev, "Can't allocate tegra30_ahub\n"); 495be944d42SStephen Warren ret = -ENOMEM; 496be944d42SStephen Warren goto err; 497be944d42SStephen Warren } 498be944d42SStephen Warren dev_set_drvdata(&pdev->dev, ahub); 499be944d42SStephen Warren 500be944d42SStephen Warren ahub->dev = &pdev->dev; 501be944d42SStephen Warren 502be944d42SStephen Warren ahub->clk_d_audio = clk_get(&pdev->dev, "d_audio"); 503be944d42SStephen Warren if (IS_ERR(ahub->clk_d_audio)) { 504be944d42SStephen Warren dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n"); 505be944d42SStephen Warren ret = PTR_ERR(ahub->clk_d_audio); 506be944d42SStephen Warren goto err; 507be944d42SStephen Warren } 508be944d42SStephen Warren 509be944d42SStephen Warren ahub->clk_apbif = clk_get(&pdev->dev, "apbif"); 510be944d42SStephen Warren if (IS_ERR(ahub->clk_apbif)) { 511be944d42SStephen Warren dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n"); 512be944d42SStephen Warren ret = PTR_ERR(ahub->clk_apbif); 513be944d42SStephen Warren goto err_clk_put_d_audio; 514be944d42SStephen Warren } 515be944d42SStephen Warren 516be944d42SStephen Warren if (of_property_read_u32_array(pdev->dev.of_node, 517be944d42SStephen Warren "nvidia,dma-request-selector", 518be944d42SStephen Warren of_dma, 2) < 0) { 519be944d42SStephen Warren dev_err(&pdev->dev, 520be944d42SStephen Warren "Missing property nvidia,dma-request-selector\n"); 521be944d42SStephen Warren ret = -ENODEV; 522be944d42SStephen Warren goto err_clk_put_d_audio; 523be944d42SStephen Warren } 524be944d42SStephen Warren ahub->dma_sel = of_dma[1]; 525be944d42SStephen Warren 526be944d42SStephen Warren res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 527be944d42SStephen Warren if (!res0) { 528be944d42SStephen Warren dev_err(&pdev->dev, "No apbif memory resource\n"); 529be944d42SStephen Warren ret = -ENODEV; 530be944d42SStephen Warren goto err_clk_put_apbif; 531be944d42SStephen Warren } 532be944d42SStephen Warren 533be944d42SStephen Warren region = devm_request_mem_region(&pdev->dev, res0->start, 534be944d42SStephen Warren resource_size(res0), DRV_NAME); 535be944d42SStephen Warren if (!region) { 536be944d42SStephen Warren dev_err(&pdev->dev, "request region apbif failed\n"); 537be944d42SStephen Warren ret = -EBUSY; 538be944d42SStephen Warren goto err_clk_put_apbif; 539be944d42SStephen Warren } 540be944d42SStephen Warren ahub->apbif_addr = res0->start; 541be944d42SStephen Warren 542be944d42SStephen Warren regs_apbif = devm_ioremap(&pdev->dev, res0->start, 543be944d42SStephen Warren resource_size(res0)); 544be944d42SStephen Warren if (!regs_apbif) { 545be944d42SStephen Warren dev_err(&pdev->dev, "ioremap apbif failed\n"); 546be944d42SStephen Warren ret = -ENOMEM; 547be944d42SStephen Warren goto err_clk_put_apbif; 548be944d42SStephen Warren } 549be944d42SStephen Warren 550be944d42SStephen Warren ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif, 551be944d42SStephen Warren &tegra30_ahub_apbif_regmap_config); 552be944d42SStephen Warren if (IS_ERR(ahub->regmap_apbif)) { 553be944d42SStephen Warren dev_err(&pdev->dev, "apbif regmap init failed\n"); 554be944d42SStephen Warren ret = PTR_ERR(ahub->regmap_apbif); 555be944d42SStephen Warren goto err_clk_put_apbif; 556be944d42SStephen Warren } 557be944d42SStephen Warren regcache_cache_only(ahub->regmap_apbif, true); 558be944d42SStephen Warren 559be944d42SStephen Warren res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); 560be944d42SStephen Warren if (!res1) { 561be944d42SStephen Warren dev_err(&pdev->dev, "No ahub memory resource\n"); 562be944d42SStephen Warren ret = -ENODEV; 563be944d42SStephen Warren goto err_clk_put_apbif; 564be944d42SStephen Warren } 565be944d42SStephen Warren 566be944d42SStephen Warren region = devm_request_mem_region(&pdev->dev, res1->start, 567be944d42SStephen Warren resource_size(res1), DRV_NAME); 568be944d42SStephen Warren if (!region) { 569be944d42SStephen Warren dev_err(&pdev->dev, "request region ahub failed\n"); 570be944d42SStephen Warren ret = -EBUSY; 571be944d42SStephen Warren goto err_clk_put_apbif; 572be944d42SStephen Warren } 573be944d42SStephen Warren 574be944d42SStephen Warren regs_ahub = devm_ioremap(&pdev->dev, res1->start, 575be944d42SStephen Warren resource_size(res1)); 576be944d42SStephen Warren if (!regs_ahub) { 577be944d42SStephen Warren dev_err(&pdev->dev, "ioremap ahub failed\n"); 578be944d42SStephen Warren ret = -ENOMEM; 579be944d42SStephen Warren goto err_clk_put_apbif; 580be944d42SStephen Warren } 581be944d42SStephen Warren 582be944d42SStephen Warren ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub, 583be944d42SStephen Warren &tegra30_ahub_ahub_regmap_config); 584be944d42SStephen Warren if (IS_ERR(ahub->regmap_ahub)) { 585be944d42SStephen Warren dev_err(&pdev->dev, "ahub regmap init failed\n"); 586be944d42SStephen Warren ret = PTR_ERR(ahub->regmap_ahub); 587be944d42SStephen Warren goto err_clk_put_apbif; 588be944d42SStephen Warren } 589be944d42SStephen Warren regcache_cache_only(ahub->regmap_ahub, true); 590be944d42SStephen Warren 591be944d42SStephen Warren pm_runtime_enable(&pdev->dev); 592be944d42SStephen Warren if (!pm_runtime_enabled(&pdev->dev)) { 593be944d42SStephen Warren ret = tegra30_ahub_runtime_resume(&pdev->dev); 594be944d42SStephen Warren if (ret) 595be944d42SStephen Warren goto err_pm_disable; 596be944d42SStephen Warren } 597be944d42SStephen Warren 59879cf5918SPrashant Gaikwad of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 599be944d42SStephen Warren 600be944d42SStephen Warren return 0; 601be944d42SStephen Warren 602be944d42SStephen Warren err_pm_disable: 603be944d42SStephen Warren pm_runtime_disable(&pdev->dev); 604be944d42SStephen Warren err_clk_put_apbif: 605be944d42SStephen Warren clk_put(ahub->clk_apbif); 606be944d42SStephen Warren err_clk_put_d_audio: 607be944d42SStephen Warren clk_put(ahub->clk_d_audio); 608ecb2c174SSachin Kamat ahub = NULL; 609be944d42SStephen Warren err: 610be944d42SStephen Warren return ret; 611be944d42SStephen Warren } 612be944d42SStephen Warren 6134652a0d0SBill Pemberton static int tegra30_ahub_remove(struct platform_device *pdev) 614be944d42SStephen Warren { 615be944d42SStephen Warren if (!ahub) 616be944d42SStephen Warren return -ENODEV; 617be944d42SStephen Warren 618be944d42SStephen Warren pm_runtime_disable(&pdev->dev); 619be944d42SStephen Warren if (!pm_runtime_status_suspended(&pdev->dev)) 620be944d42SStephen Warren tegra30_ahub_runtime_suspend(&pdev->dev); 621be944d42SStephen Warren 622be944d42SStephen Warren clk_put(ahub->clk_apbif); 623be944d42SStephen Warren clk_put(ahub->clk_d_audio); 624be944d42SStephen Warren 625ecb2c174SSachin Kamat ahub = NULL; 626be944d42SStephen Warren 627be944d42SStephen Warren return 0; 628be944d42SStephen Warren } 629be944d42SStephen Warren 6302f41a3f4SStephen Warren #ifdef CONFIG_PM_SLEEP 6312f41a3f4SStephen Warren static int tegra30_ahub_suspend(struct device *dev) 6322f41a3f4SStephen Warren { 6332f41a3f4SStephen Warren regcache_mark_dirty(ahub->regmap_ahub); 6342f41a3f4SStephen Warren regcache_mark_dirty(ahub->regmap_apbif); 6352f41a3f4SStephen Warren 6362f41a3f4SStephen Warren return 0; 6372f41a3f4SStephen Warren } 6382f41a3f4SStephen Warren 6392f41a3f4SStephen Warren static int tegra30_ahub_resume(struct device *dev) 6402f41a3f4SStephen Warren { 6412f41a3f4SStephen Warren int ret; 6422f41a3f4SStephen Warren 6432f41a3f4SStephen Warren ret = regcache_sync(ahub->regmap_ahub); 6442f41a3f4SStephen Warren ret |= regcache_sync(ahub->regmap_apbif); 6452f41a3f4SStephen Warren 6462f41a3f4SStephen Warren return ret; 6472f41a3f4SStephen Warren } 6482f41a3f4SStephen Warren #endif 6492f41a3f4SStephen Warren 650f6e65744SBill Pemberton static const struct dev_pm_ops tegra30_ahub_pm_ops = { 651be944d42SStephen Warren SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend, 652be944d42SStephen Warren tegra30_ahub_runtime_resume, NULL) 6532f41a3f4SStephen Warren SET_SYSTEM_SLEEP_PM_OPS(tegra30_ahub_suspend, tegra30_ahub_resume) 654be944d42SStephen Warren }; 655be944d42SStephen Warren 656be944d42SStephen Warren static struct platform_driver tegra30_ahub_driver = { 657be944d42SStephen Warren .probe = tegra30_ahub_probe, 6584652a0d0SBill Pemberton .remove = tegra30_ahub_remove, 659be944d42SStephen Warren .driver = { 660be944d42SStephen Warren .name = DRV_NAME, 661be944d42SStephen Warren .owner = THIS_MODULE, 662be944d42SStephen Warren .of_match_table = tegra30_ahub_of_match, 663be944d42SStephen Warren .pm = &tegra30_ahub_pm_ops, 664be944d42SStephen Warren }, 665be944d42SStephen Warren }; 666be944d42SStephen Warren module_platform_driver(tegra30_ahub_driver); 667be944d42SStephen Warren 668be944d42SStephen Warren MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 669be944d42SStephen Warren MODULE_DESCRIPTION("Tegra30 AHUB driver"); 670be944d42SStephen Warren MODULE_LICENSE("GPL v2"); 671be944d42SStephen Warren MODULE_ALIAS("platform:" DRV_NAME); 67269c5b753SStephen Warren MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match); 673