1*7358a803SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*7358a803SSameer Pujar /* 3*7358a803SSameer Pujar * tegra210_peq.h - Definitions for Tegra210 PEQ driver 4*7358a803SSameer Pujar * 5*7358a803SSameer Pujar * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. 6*7358a803SSameer Pujar * 7*7358a803SSameer Pujar */ 8*7358a803SSameer Pujar 9*7358a803SSameer Pujar #ifndef __TEGRA210_PEQ_H__ 10*7358a803SSameer Pujar #define __TEGRA210_PEQ_H__ 11*7358a803SSameer Pujar 12*7358a803SSameer Pujar #include <linux/platform_device.h> 13*7358a803SSameer Pujar #include <linux/regmap.h> 14*7358a803SSameer Pujar #include <sound/soc.h> 15*7358a803SSameer Pujar 16*7358a803SSameer Pujar /* Register offsets from PEQ base */ 17*7358a803SSameer Pujar #define TEGRA210_PEQ_SOFT_RESET 0x0 18*7358a803SSameer Pujar #define TEGRA210_PEQ_CG 0x4 19*7358a803SSameer Pujar #define TEGRA210_PEQ_STATUS 0x8 20*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG 0xc 21*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_RAM_CTRL 0x10 22*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_RAM_DATA 0x14 23*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL 0x18 24*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_RAM_SHIFT_DATA 0x1c 25*7358a803SSameer Pujar 26*7358a803SSameer Pujar /* Fields in TEGRA210_PEQ_CFG */ 27*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT 2 28*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_BIQUAD_STAGES_MASK (0xf << TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT) 29*7358a803SSameer Pujar 30*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_MODE_SHIFT 0 31*7358a803SSameer Pujar #define TEGRA210_PEQ_CFG_MODE_MASK (0x1 << TEGRA210_PEQ_CFG_MODE_SHIFT) 32*7358a803SSameer Pujar 33*7358a803SSameer Pujar #define TEGRA210_PEQ_RAM_CTRL_RW_READ 0 34*7358a803SSameer Pujar #define TEGRA210_PEQ_RAM_CTRL_RW_WRITE (1 << 14) 35*7358a803SSameer Pujar #define TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN (1 << 13) 36*7358a803SSameer Pujar #define TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN (1 << 12) 37*7358a803SSameer Pujar #define TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK 0x1ff 38*7358a803SSameer Pujar 39*7358a803SSameer Pujar /* PEQ register definition ends here */ 40*7358a803SSameer Pujar #define TEGRA210_PEQ_MAX_BIQUAD_STAGES 12 41*7358a803SSameer Pujar 42*7358a803SSameer Pujar #define TEGRA210_PEQ_MAX_CHANNELS 8 43*7358a803SSameer Pujar 44*7358a803SSameer Pujar #define TEGRA210_PEQ_BIQUAD_INIT_STAGE 5 45*7358a803SSameer Pujar 46*7358a803SSameer Pujar #define TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES * 5) 47*7358a803SSameer Pujar #define TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES) 48*7358a803SSameer Pujar 49*7358a803SSameer Pujar int tegra210_peq_regmap_init(struct platform_device *pdev); 50*7358a803SSameer Pujar int tegra210_peq_component_init(struct snd_soc_component *cmpnt); 51*7358a803SSameer Pujar void tegra210_peq_restore(struct regmap *regmap, u32 *biquad_gains, 52*7358a803SSameer Pujar u32 *biquad_shifts); 53*7358a803SSameer Pujar void tegra210_peq_save(struct regmap *regmap, u32 *biquad_gains, 54*7358a803SSameer Pujar u32 *biquad_shifts); 55*7358a803SSameer Pujar 56*7358a803SSameer Pujar #endif 57