1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // tegra210_ahub.c - Tegra210 AHUB driver 4 // 5 // Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 #include "tegra210_ahub.h" 16 17 static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl, 18 struct snd_ctl_elem_value *uctl) 19 { 20 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl); 21 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 23 unsigned int reg, i, bit_pos = 0; 24 25 /* 26 * Find the bit position of current MUX input. 27 * If nothing is set, position would be 0 and it corresponds to 'None'. 28 */ 29 for (i = 0; i < ahub->soc_data->reg_count; i++) { 30 unsigned int reg_val; 31 32 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); 33 reg_val = snd_soc_component_read(cmpnt, reg); 34 reg_val &= ahub->soc_data->mask[i]; 35 36 if (reg_val) { 37 bit_pos = ffs(reg_val) + 38 (8 * cmpnt->val_bytes * i); 39 break; 40 } 41 } 42 43 /* Find index related to the item in array *_ahub_mux_texts[] */ 44 for (i = 0; i < e->items; i++) { 45 if (bit_pos == e->values[i]) { 46 uctl->value.enumerated.item[0] = i; 47 break; 48 } 49 } 50 51 return 0; 52 } 53 54 static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl, 55 struct snd_ctl_elem_value *uctl) 56 { 57 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl); 58 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 59 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl); 60 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 61 struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { }; 62 unsigned int *item = uctl->value.enumerated.item; 63 unsigned int value = e->values[item[0]]; 64 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; 65 int change = 0; 66 67 if (item[0] >= e->items) 68 return -EINVAL; 69 70 if (value) { 71 /* Get the register index and value to set */ 72 reg_idx = (value - 1) / (8 * cmpnt->val_bytes); 73 bit_pos = (value - 1) % (8 * cmpnt->val_bytes); 74 reg_val = BIT(bit_pos); 75 } 76 77 /* 78 * Run through all parts of a MUX register to find the state changes. 79 * There will be an additional update if new MUX input value is from 80 * different part of the MUX register. 81 */ 82 for (i = 0; i < ahub->soc_data->reg_count; i++) { 83 update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); 84 update[i].val = (i == reg_idx) ? reg_val : 0; 85 update[i].mask = ahub->soc_data->mask[i]; 86 update[i].kcontrol = kctl; 87 88 /* Update widget power if state has changed */ 89 if (snd_soc_component_test_bits(cmpnt, update[i].reg, 90 update[i].mask, 91 update[i].val)) 92 change |= snd_soc_dapm_mux_update_power(dapm, kctl, 93 item[0], e, 94 &update[i]); 95 } 96 97 return change; 98 } 99 100 static struct snd_soc_dai_driver tegra210_ahub_dais[] = { 101 DAI(ADMAIF1), 102 DAI(ADMAIF2), 103 DAI(ADMAIF3), 104 DAI(ADMAIF4), 105 DAI(ADMAIF5), 106 DAI(ADMAIF6), 107 DAI(ADMAIF7), 108 DAI(ADMAIF8), 109 DAI(ADMAIF9), 110 DAI(ADMAIF10), 111 /* XBAR <-> I2S <-> Codec */ 112 DAI(I2S1), 113 DAI(I2S2), 114 DAI(I2S3), 115 DAI(I2S4), 116 DAI(I2S5), 117 /* XBAR <- DMIC <- Codec */ 118 DAI(DMIC1), 119 DAI(DMIC2), 120 DAI(DMIC3), 121 /* XBAR -> SFC -> XBAR */ 122 DAI(SFC1 RX), 123 DAI(SFC1 TX), 124 DAI(SFC2 RX), 125 DAI(SFC2 TX), 126 DAI(SFC3 RX), 127 DAI(SFC3 TX), 128 DAI(SFC4 RX), 129 DAI(SFC4 TX), 130 /* XBAR -> MVC -> XBAR */ 131 DAI(MVC1 RX), 132 DAI(MVC1 TX), 133 DAI(MVC2 RX), 134 DAI(MVC2 TX), 135 /* XBAR -> AMX(4:1) -> XBAR */ 136 DAI(AMX1 RX1), 137 DAI(AMX1 RX2), 138 DAI(AMX1 RX3), 139 DAI(AMX1 RX4), 140 DAI(AMX1), 141 DAI(AMX2 RX1), 142 DAI(AMX2 RX2), 143 DAI(AMX2 RX3), 144 DAI(AMX2 RX4), 145 DAI(AMX2), 146 /* XBAR -> ADX(1:4) -> XBAR */ 147 DAI(ADX1), 148 DAI(ADX1 TX1), 149 DAI(ADX1 TX2), 150 DAI(ADX1 TX3), 151 DAI(ADX1 TX4), 152 DAI(ADX2), 153 DAI(ADX2 TX1), 154 DAI(ADX2 TX2), 155 DAI(ADX2 TX3), 156 DAI(ADX2 TX4), 157 /* XBAR -> MIXER(10:5) -> XBAR */ 158 DAI(MIXER1 RX1), 159 DAI(MIXER1 RX2), 160 DAI(MIXER1 RX3), 161 DAI(MIXER1 RX4), 162 DAI(MIXER1 RX5), 163 DAI(MIXER1 RX6), 164 DAI(MIXER1 RX7), 165 DAI(MIXER1 RX8), 166 DAI(MIXER1 RX9), 167 DAI(MIXER1 RX10), 168 DAI(MIXER1 TX1), 169 DAI(MIXER1 TX2), 170 DAI(MIXER1 TX3), 171 DAI(MIXER1 TX4), 172 DAI(MIXER1 TX5), 173 }; 174 175 static struct snd_soc_dai_driver tegra186_ahub_dais[] = { 176 DAI(ADMAIF1), 177 DAI(ADMAIF2), 178 DAI(ADMAIF3), 179 DAI(ADMAIF4), 180 DAI(ADMAIF5), 181 DAI(ADMAIF6), 182 DAI(ADMAIF7), 183 DAI(ADMAIF8), 184 DAI(ADMAIF9), 185 DAI(ADMAIF10), 186 DAI(ADMAIF11), 187 DAI(ADMAIF12), 188 DAI(ADMAIF13), 189 DAI(ADMAIF14), 190 DAI(ADMAIF15), 191 DAI(ADMAIF16), 192 DAI(ADMAIF17), 193 DAI(ADMAIF18), 194 DAI(ADMAIF19), 195 DAI(ADMAIF20), 196 /* XBAR <-> I2S <-> Codec */ 197 DAI(I2S1), 198 DAI(I2S2), 199 DAI(I2S3), 200 DAI(I2S4), 201 DAI(I2S5), 202 DAI(I2S6), 203 /* XBAR <- DMIC <- Codec */ 204 DAI(DMIC1), 205 DAI(DMIC2), 206 DAI(DMIC3), 207 DAI(DMIC4), 208 /* XBAR -> DSPK -> Codec */ 209 DAI(DSPK1), 210 DAI(DSPK2), 211 /* XBAR -> SFC -> XBAR */ 212 DAI(SFC1 RX), 213 DAI(SFC1 TX), 214 DAI(SFC2 RX), 215 DAI(SFC2 TX), 216 DAI(SFC3 RX), 217 DAI(SFC3 TX), 218 DAI(SFC4 RX), 219 DAI(SFC4 TX), 220 /* XBAR -> MVC -> XBAR */ 221 DAI(MVC1 RX), 222 DAI(MVC1 TX), 223 DAI(MVC2 RX), 224 DAI(MVC2 TX), 225 /* XBAR -> AMX(4:1) -> XBAR */ 226 DAI(AMX1 RX1), 227 DAI(AMX1 RX2), 228 DAI(AMX1 RX3), 229 DAI(AMX1 RX4), 230 DAI(AMX1), 231 DAI(AMX2 RX1), 232 DAI(AMX2 RX2), 233 DAI(AMX2 RX3), 234 DAI(AMX2 RX4), 235 DAI(AMX2), 236 DAI(AMX3 RX1), 237 DAI(AMX3 RX2), 238 DAI(AMX3 RX3), 239 DAI(AMX3 RX4), 240 DAI(AMX3), 241 DAI(AMX4 RX1), 242 DAI(AMX4 RX2), 243 DAI(AMX4 RX3), 244 DAI(AMX4 RX4), 245 DAI(AMX4), 246 /* XBAR -> ADX(1:4) -> XBAR */ 247 DAI(ADX1), 248 DAI(ADX1 TX1), 249 DAI(ADX1 TX2), 250 DAI(ADX1 TX3), 251 DAI(ADX1 TX4), 252 DAI(ADX2), 253 DAI(ADX2 TX1), 254 DAI(ADX2 TX2), 255 DAI(ADX2 TX3), 256 DAI(ADX2 TX4), 257 DAI(ADX3), 258 DAI(ADX3 TX1), 259 DAI(ADX3 TX2), 260 DAI(ADX3 TX3), 261 DAI(ADX3 TX4), 262 DAI(ADX4), 263 DAI(ADX4 TX1), 264 DAI(ADX4 TX2), 265 DAI(ADX4 TX3), 266 DAI(ADX4 TX4), 267 /* XBAR -> MIXER1(10:5) -> XBAR */ 268 DAI(MIXER1 RX1), 269 DAI(MIXER1 RX2), 270 DAI(MIXER1 RX3), 271 DAI(MIXER1 RX4), 272 DAI(MIXER1 RX5), 273 DAI(MIXER1 RX6), 274 DAI(MIXER1 RX7), 275 DAI(MIXER1 RX8), 276 DAI(MIXER1 RX9), 277 DAI(MIXER1 RX10), 278 DAI(MIXER1 TX1), 279 DAI(MIXER1 TX2), 280 DAI(MIXER1 TX3), 281 DAI(MIXER1 TX4), 282 DAI(MIXER1 TX5), 283 /* XBAR -> ASRC -> XBAR */ 284 DAI(ASRC1 RX1), 285 DAI(ASRC1 TX1), 286 DAI(ASRC1 RX2), 287 DAI(ASRC1 TX2), 288 DAI(ASRC1 RX3), 289 DAI(ASRC1 TX3), 290 DAI(ASRC1 RX4), 291 DAI(ASRC1 TX4), 292 DAI(ASRC1 RX5), 293 DAI(ASRC1 TX5), 294 DAI(ASRC1 RX6), 295 DAI(ASRC1 TX6), 296 DAI(ASRC1 RX7), 297 }; 298 299 static const char * const tegra210_ahub_mux_texts[] = { 300 "None", 301 "ADMAIF1", 302 "ADMAIF2", 303 "ADMAIF3", 304 "ADMAIF4", 305 "ADMAIF5", 306 "ADMAIF6", 307 "ADMAIF7", 308 "ADMAIF8", 309 "ADMAIF9", 310 "ADMAIF10", 311 "I2S1", 312 "I2S2", 313 "I2S3", 314 "I2S4", 315 "I2S5", 316 "DMIC1", 317 "DMIC2", 318 "DMIC3", 319 "SFC1", 320 "SFC2", 321 "SFC3", 322 "SFC4", 323 "MVC1", 324 "MVC2", 325 "AMX1", 326 "AMX2", 327 "ADX1 TX1", 328 "ADX1 TX2", 329 "ADX1 TX3", 330 "ADX1 TX4", 331 "ADX2 TX1", 332 "ADX2 TX2", 333 "ADX2 TX3", 334 "ADX2 TX4", 335 "MIXER1 TX1", 336 "MIXER1 TX2", 337 "MIXER1 TX3", 338 "MIXER1 TX4", 339 "MIXER1 TX5", 340 }; 341 342 static const char * const tegra186_ahub_mux_texts[] = { 343 "None", 344 "ADMAIF1", 345 "ADMAIF2", 346 "ADMAIF3", 347 "ADMAIF4", 348 "ADMAIF5", 349 "ADMAIF6", 350 "ADMAIF7", 351 "ADMAIF8", 352 "ADMAIF9", 353 "ADMAIF10", 354 "ADMAIF11", 355 "ADMAIF12", 356 "ADMAIF13", 357 "ADMAIF14", 358 "ADMAIF15", 359 "ADMAIF16", 360 "I2S1", 361 "I2S2", 362 "I2S3", 363 "I2S4", 364 "I2S5", 365 "I2S6", 366 "ADMAIF17", 367 "ADMAIF18", 368 "ADMAIF19", 369 "ADMAIF20", 370 "DMIC1", 371 "DMIC2", 372 "DMIC3", 373 "DMIC4", 374 "SFC1", 375 "SFC2", 376 "SFC3", 377 "SFC4", 378 "MVC1", 379 "MVC2", 380 "AMX1", 381 "AMX2", 382 "AMX3", 383 "AMX4", 384 "ADX1 TX1", 385 "ADX1 TX2", 386 "ADX1 TX3", 387 "ADX1 TX4", 388 "ADX2 TX1", 389 "ADX2 TX2", 390 "ADX2 TX3", 391 "ADX2 TX4", 392 "ADX3 TX1", 393 "ADX3 TX2", 394 "ADX3 TX3", 395 "ADX3 TX4", 396 "ADX4 TX1", 397 "ADX4 TX2", 398 "ADX4 TX3", 399 "ADX4 TX4", 400 "MIXER1 TX1", 401 "MIXER1 TX2", 402 "MIXER1 TX3", 403 "MIXER1 TX4", 404 "MIXER1 TX5", 405 "ASRC1 TX1", 406 "ASRC1 TX2", 407 "ASRC1 TX3", 408 "ASRC1 TX4", 409 "ASRC1 TX5", 410 "ASRC1 TX6", 411 }; 412 413 static const unsigned int tegra210_ahub_mux_values[] = { 414 0, 415 /* ADMAIF */ 416 MUX_VALUE(0, 0), 417 MUX_VALUE(0, 1), 418 MUX_VALUE(0, 2), 419 MUX_VALUE(0, 3), 420 MUX_VALUE(0, 4), 421 MUX_VALUE(0, 5), 422 MUX_VALUE(0, 6), 423 MUX_VALUE(0, 7), 424 MUX_VALUE(0, 8), 425 MUX_VALUE(0, 9), 426 /* I2S */ 427 MUX_VALUE(0, 16), 428 MUX_VALUE(0, 17), 429 MUX_VALUE(0, 18), 430 MUX_VALUE(0, 19), 431 MUX_VALUE(0, 20), 432 /* DMIC */ 433 MUX_VALUE(2, 18), 434 MUX_VALUE(2, 19), 435 MUX_VALUE(2, 20), 436 /* SFC */ 437 MUX_VALUE(0, 24), 438 MUX_VALUE(0, 25), 439 MUX_VALUE(0, 26), 440 MUX_VALUE(0, 27), 441 /* MVC */ 442 MUX_VALUE(2, 8), 443 MUX_VALUE(2, 9), 444 /* AMX */ 445 MUX_VALUE(1, 8), 446 MUX_VALUE(1, 9), 447 /* ADX */ 448 MUX_VALUE(2, 24), 449 MUX_VALUE(2, 25), 450 MUX_VALUE(2, 26), 451 MUX_VALUE(2, 27), 452 MUX_VALUE(2, 28), 453 MUX_VALUE(2, 29), 454 MUX_VALUE(2, 30), 455 MUX_VALUE(2, 31), 456 /* MIXER */ 457 MUX_VALUE(1, 0), 458 MUX_VALUE(1, 1), 459 MUX_VALUE(1, 2), 460 MUX_VALUE(1, 3), 461 MUX_VALUE(1, 4), 462 }; 463 464 static const unsigned int tegra186_ahub_mux_values[] = { 465 0, 466 /* ADMAIF */ 467 MUX_VALUE(0, 0), 468 MUX_VALUE(0, 1), 469 MUX_VALUE(0, 2), 470 MUX_VALUE(0, 3), 471 MUX_VALUE(0, 4), 472 MUX_VALUE(0, 5), 473 MUX_VALUE(0, 6), 474 MUX_VALUE(0, 7), 475 MUX_VALUE(0, 8), 476 MUX_VALUE(0, 9), 477 MUX_VALUE(0, 10), 478 MUX_VALUE(0, 11), 479 MUX_VALUE(0, 12), 480 MUX_VALUE(0, 13), 481 MUX_VALUE(0, 14), 482 MUX_VALUE(0, 15), 483 /* I2S */ 484 MUX_VALUE(0, 16), 485 MUX_VALUE(0, 17), 486 MUX_VALUE(0, 18), 487 MUX_VALUE(0, 19), 488 MUX_VALUE(0, 20), 489 MUX_VALUE(0, 21), 490 /* ADMAIF */ 491 MUX_VALUE(3, 16), 492 MUX_VALUE(3, 17), 493 MUX_VALUE(3, 18), 494 MUX_VALUE(3, 19), 495 /* DMIC */ 496 MUX_VALUE(2, 18), 497 MUX_VALUE(2, 19), 498 MUX_VALUE(2, 20), 499 MUX_VALUE(2, 21), 500 /* SFC */ 501 MUX_VALUE(0, 24), 502 MUX_VALUE(0, 25), 503 MUX_VALUE(0, 26), 504 MUX_VALUE(0, 27), 505 /* MVC */ 506 MUX_VALUE(2, 8), 507 MUX_VALUE(2, 9), 508 /* AMX */ 509 MUX_VALUE(1, 8), 510 MUX_VALUE(1, 9), 511 MUX_VALUE(1, 10), 512 MUX_VALUE(1, 11), 513 /* ADX */ 514 MUX_VALUE(2, 24), 515 MUX_VALUE(2, 25), 516 MUX_VALUE(2, 26), 517 MUX_VALUE(2, 27), 518 MUX_VALUE(2, 28), 519 MUX_VALUE(2, 29), 520 MUX_VALUE(2, 30), 521 MUX_VALUE(2, 31), 522 MUX_VALUE(3, 0), 523 MUX_VALUE(3, 1), 524 MUX_VALUE(3, 2), 525 MUX_VALUE(3, 3), 526 MUX_VALUE(3, 4), 527 MUX_VALUE(3, 5), 528 MUX_VALUE(3, 6), 529 MUX_VALUE(3, 7), 530 /* MIXER */ 531 MUX_VALUE(1, 0), 532 MUX_VALUE(1, 1), 533 MUX_VALUE(1, 2), 534 MUX_VALUE(1, 3), 535 MUX_VALUE(1, 4), 536 /* ASRC */ 537 MUX_VALUE(3, 24), 538 MUX_VALUE(3, 25), 539 MUX_VALUE(3, 26), 540 MUX_VALUE(3, 27), 541 MUX_VALUE(3, 28), 542 MUX_VALUE(3, 29), 543 }; 544 545 /* Controls for t210 */ 546 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00); 547 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01); 548 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02); 549 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03); 550 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04); 551 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05); 552 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06); 553 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07); 554 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08); 555 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09); 556 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10); 557 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11); 558 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12); 559 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13); 560 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14); 561 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18); 562 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19); 563 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a); 564 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b); 565 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48); 566 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49); 567 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50); 568 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51); 569 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52); 570 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53); 571 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54); 572 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55); 573 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56); 574 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57); 575 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58); 576 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59); 577 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20); 578 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21); 579 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22); 580 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23); 581 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24); 582 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25); 583 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26); 584 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27); 585 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28); 586 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29); 587 588 /* Controls for t186 */ 589 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00); 590 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01); 591 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02); 592 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03); 593 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04); 594 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05); 595 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06); 596 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07); 597 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08); 598 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09); 599 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10); 600 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11); 601 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12); 602 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13); 603 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14); 604 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a); 605 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b); 606 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c); 607 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d); 608 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e); 609 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f); 610 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15); 611 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); 612 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); 613 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68); 614 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69); 615 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a); 616 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b); 617 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18); 618 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19); 619 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a); 620 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b); 621 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48); 622 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49); 623 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50); 624 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51); 625 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52); 626 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53); 627 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54); 628 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55); 629 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56); 630 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57); 631 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58); 632 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59); 633 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a); 634 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b); 635 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64); 636 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65); 637 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66); 638 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67); 639 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60); 640 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61); 641 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62); 642 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63); 643 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20); 644 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21); 645 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22); 646 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23); 647 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24); 648 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25); 649 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26); 650 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); 651 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); 652 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); 653 MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c); 654 MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d); 655 MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e); 656 MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f); 657 MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70); 658 MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71); 659 MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72); 660 661 /* Controls for t234 */ 662 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44); 663 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45); 664 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48); 665 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49); 666 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a); 667 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b); 668 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c); 669 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d); 670 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e); 671 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f); 672 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50); 673 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51); 674 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52); 675 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53); 676 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58); 677 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59); 678 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a); 679 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b); 680 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c); 681 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d); 682 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e); 683 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f); 684 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60); 685 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61); 686 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62); 687 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63); 688 MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64); 689 MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65); 690 MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66); 691 MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67); 692 MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68); 693 MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69); 694 MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a); 695 696 /* 697 * The number of entries in, and order of, this array is closely tied to the 698 * calculation of tegra210_ahub_codec.num_dapm_widgets near the end of 699 * tegra210_ahub_probe() 700 */ 701 static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { 702 WIDGETS("ADMAIF1", t210_admaif1_tx), 703 WIDGETS("ADMAIF2", t210_admaif2_tx), 704 WIDGETS("ADMAIF3", t210_admaif3_tx), 705 WIDGETS("ADMAIF4", t210_admaif4_tx), 706 WIDGETS("ADMAIF5", t210_admaif5_tx), 707 WIDGETS("ADMAIF6", t210_admaif6_tx), 708 WIDGETS("ADMAIF7", t210_admaif7_tx), 709 WIDGETS("ADMAIF8", t210_admaif8_tx), 710 WIDGETS("ADMAIF9", t210_admaif9_tx), 711 WIDGETS("ADMAIF10", t210_admaif10_tx), 712 WIDGETS("I2S1", t210_i2s1_tx), 713 WIDGETS("I2S2", t210_i2s2_tx), 714 WIDGETS("I2S3", t210_i2s3_tx), 715 WIDGETS("I2S4", t210_i2s4_tx), 716 WIDGETS("I2S5", t210_i2s5_tx), 717 TX_WIDGETS("DMIC1"), 718 TX_WIDGETS("DMIC2"), 719 TX_WIDGETS("DMIC3"), 720 WIDGETS("SFC1", t210_sfc1_tx), 721 WIDGETS("SFC2", t210_sfc2_tx), 722 WIDGETS("SFC3", t210_sfc3_tx), 723 WIDGETS("SFC4", t210_sfc4_tx), 724 WIDGETS("MVC1", t210_mvc1_tx), 725 WIDGETS("MVC2", t210_mvc2_tx), 726 WIDGETS("AMX1 RX1", t210_amx11_tx), 727 WIDGETS("AMX1 RX2", t210_amx12_tx), 728 WIDGETS("AMX1 RX3", t210_amx13_tx), 729 WIDGETS("AMX1 RX4", t210_amx14_tx), 730 WIDGETS("AMX2 RX1", t210_amx21_tx), 731 WIDGETS("AMX2 RX2", t210_amx22_tx), 732 WIDGETS("AMX2 RX3", t210_amx23_tx), 733 WIDGETS("AMX2 RX4", t210_amx24_tx), 734 TX_WIDGETS("AMX1"), 735 TX_WIDGETS("AMX2"), 736 WIDGETS("ADX1", t210_adx1_tx), 737 WIDGETS("ADX2", t210_adx2_tx), 738 TX_WIDGETS("ADX1 TX1"), 739 TX_WIDGETS("ADX1 TX2"), 740 TX_WIDGETS("ADX1 TX3"), 741 TX_WIDGETS("ADX1 TX4"), 742 TX_WIDGETS("ADX2 TX1"), 743 TX_WIDGETS("ADX2 TX2"), 744 TX_WIDGETS("ADX2 TX3"), 745 TX_WIDGETS("ADX2 TX4"), 746 WIDGETS("MIXER1 RX1", t210_mixer11_tx), 747 WIDGETS("MIXER1 RX2", t210_mixer12_tx), 748 WIDGETS("MIXER1 RX3", t210_mixer13_tx), 749 WIDGETS("MIXER1 RX4", t210_mixer14_tx), 750 WIDGETS("MIXER1 RX5", t210_mixer15_tx), 751 WIDGETS("MIXER1 RX6", t210_mixer16_tx), 752 WIDGETS("MIXER1 RX7", t210_mixer17_tx), 753 WIDGETS("MIXER1 RX8", t210_mixer18_tx), 754 WIDGETS("MIXER1 RX9", t210_mixer19_tx), 755 WIDGETS("MIXER1 RX10", t210_mixer110_tx), 756 TX_WIDGETS("MIXER1 TX1"), 757 TX_WIDGETS("MIXER1 TX2"), 758 TX_WIDGETS("MIXER1 TX3"), 759 TX_WIDGETS("MIXER1 TX4"), 760 TX_WIDGETS("MIXER1 TX5"), 761 }; 762 763 static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { 764 WIDGETS("ADMAIF1", t186_admaif1_tx), 765 WIDGETS("ADMAIF2", t186_admaif2_tx), 766 WIDGETS("ADMAIF3", t186_admaif3_tx), 767 WIDGETS("ADMAIF4", t186_admaif4_tx), 768 WIDGETS("ADMAIF5", t186_admaif5_tx), 769 WIDGETS("ADMAIF6", t186_admaif6_tx), 770 WIDGETS("ADMAIF7", t186_admaif7_tx), 771 WIDGETS("ADMAIF8", t186_admaif8_tx), 772 WIDGETS("ADMAIF9", t186_admaif9_tx), 773 WIDGETS("ADMAIF10", t186_admaif10_tx), 774 WIDGETS("ADMAIF11", t186_admaif11_tx), 775 WIDGETS("ADMAIF12", t186_admaif12_tx), 776 WIDGETS("ADMAIF13", t186_admaif13_tx), 777 WIDGETS("ADMAIF14", t186_admaif14_tx), 778 WIDGETS("ADMAIF15", t186_admaif15_tx), 779 WIDGETS("ADMAIF16", t186_admaif16_tx), 780 WIDGETS("ADMAIF17", t186_admaif17_tx), 781 WIDGETS("ADMAIF18", t186_admaif18_tx), 782 WIDGETS("ADMAIF19", t186_admaif19_tx), 783 WIDGETS("ADMAIF20", t186_admaif20_tx), 784 WIDGETS("I2S1", t186_i2s1_tx), 785 WIDGETS("I2S2", t186_i2s2_tx), 786 WIDGETS("I2S3", t186_i2s3_tx), 787 WIDGETS("I2S4", t186_i2s4_tx), 788 WIDGETS("I2S5", t186_i2s5_tx), 789 WIDGETS("I2S6", t186_i2s6_tx), 790 TX_WIDGETS("DMIC1"), 791 TX_WIDGETS("DMIC2"), 792 TX_WIDGETS("DMIC3"), 793 TX_WIDGETS("DMIC4"), 794 WIDGETS("DSPK1", t186_dspk1_tx), 795 WIDGETS("DSPK2", t186_dspk2_tx), 796 WIDGETS("SFC1", t186_sfc1_tx), 797 WIDGETS("SFC2", t186_sfc2_tx), 798 WIDGETS("SFC3", t186_sfc3_tx), 799 WIDGETS("SFC4", t186_sfc4_tx), 800 WIDGETS("MVC1", t186_mvc1_tx), 801 WIDGETS("MVC2", t186_mvc2_tx), 802 WIDGETS("AMX1 RX1", t186_amx11_tx), 803 WIDGETS("AMX1 RX2", t186_amx12_tx), 804 WIDGETS("AMX1 RX3", t186_amx13_tx), 805 WIDGETS("AMX1 RX4", t186_amx14_tx), 806 WIDGETS("AMX2 RX1", t186_amx21_tx), 807 WIDGETS("AMX2 RX2", t186_amx22_tx), 808 WIDGETS("AMX2 RX3", t186_amx23_tx), 809 WIDGETS("AMX2 RX4", t186_amx24_tx), 810 WIDGETS("AMX3 RX1", t186_amx31_tx), 811 WIDGETS("AMX3 RX2", t186_amx32_tx), 812 WIDGETS("AMX3 RX3", t186_amx33_tx), 813 WIDGETS("AMX3 RX4", t186_amx34_tx), 814 WIDGETS("AMX4 RX1", t186_amx41_tx), 815 WIDGETS("AMX4 RX2", t186_amx42_tx), 816 WIDGETS("AMX4 RX3", t186_amx43_tx), 817 WIDGETS("AMX4 RX4", t186_amx44_tx), 818 TX_WIDGETS("AMX1"), 819 TX_WIDGETS("AMX2"), 820 TX_WIDGETS("AMX3"), 821 TX_WIDGETS("AMX4"), 822 WIDGETS("ADX1", t186_adx1_tx), 823 WIDGETS("ADX2", t186_adx2_tx), 824 WIDGETS("ADX3", t186_adx3_tx), 825 WIDGETS("ADX4", t186_adx4_tx), 826 TX_WIDGETS("ADX1 TX1"), 827 TX_WIDGETS("ADX1 TX2"), 828 TX_WIDGETS("ADX1 TX3"), 829 TX_WIDGETS("ADX1 TX4"), 830 TX_WIDGETS("ADX2 TX1"), 831 TX_WIDGETS("ADX2 TX2"), 832 TX_WIDGETS("ADX2 TX3"), 833 TX_WIDGETS("ADX2 TX4"), 834 TX_WIDGETS("ADX3 TX1"), 835 TX_WIDGETS("ADX3 TX2"), 836 TX_WIDGETS("ADX3 TX3"), 837 TX_WIDGETS("ADX3 TX4"), 838 TX_WIDGETS("ADX4 TX1"), 839 TX_WIDGETS("ADX4 TX2"), 840 TX_WIDGETS("ADX4 TX3"), 841 TX_WIDGETS("ADX4 TX4"), 842 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 843 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 844 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 845 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 846 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 847 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 848 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 849 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 850 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 851 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 852 TX_WIDGETS("MIXER1 TX1"), 853 TX_WIDGETS("MIXER1 TX2"), 854 TX_WIDGETS("MIXER1 TX3"), 855 TX_WIDGETS("MIXER1 TX4"), 856 TX_WIDGETS("MIXER1 TX5"), 857 WIDGETS("ASRC1 RX1", t186_asrc11_tx), 858 WIDGETS("ASRC1 RX2", t186_asrc12_tx), 859 WIDGETS("ASRC1 RX3", t186_asrc13_tx), 860 WIDGETS("ASRC1 RX4", t186_asrc14_tx), 861 WIDGETS("ASRC1 RX5", t186_asrc15_tx), 862 WIDGETS("ASRC1 RX6", t186_asrc16_tx), 863 WIDGETS("ASRC1 RX7", t186_asrc17_tx), 864 TX_WIDGETS("ASRC1 TX1"), 865 TX_WIDGETS("ASRC1 TX2"), 866 TX_WIDGETS("ASRC1 TX3"), 867 TX_WIDGETS("ASRC1 TX4"), 868 TX_WIDGETS("ASRC1 TX5"), 869 TX_WIDGETS("ASRC1 TX6"), 870 }; 871 872 static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = { 873 WIDGETS("ADMAIF1", t186_admaif1_tx), 874 WIDGETS("ADMAIF2", t186_admaif2_tx), 875 WIDGETS("ADMAIF3", t186_admaif3_tx), 876 WIDGETS("ADMAIF4", t186_admaif4_tx), 877 WIDGETS("ADMAIF5", t186_admaif5_tx), 878 WIDGETS("ADMAIF6", t186_admaif6_tx), 879 WIDGETS("ADMAIF7", t186_admaif7_tx), 880 WIDGETS("ADMAIF8", t186_admaif8_tx), 881 WIDGETS("ADMAIF9", t186_admaif9_tx), 882 WIDGETS("ADMAIF10", t186_admaif10_tx), 883 WIDGETS("ADMAIF11", t186_admaif11_tx), 884 WIDGETS("ADMAIF12", t186_admaif12_tx), 885 WIDGETS("ADMAIF13", t186_admaif13_tx), 886 WIDGETS("ADMAIF14", t186_admaif14_tx), 887 WIDGETS("ADMAIF15", t186_admaif15_tx), 888 WIDGETS("ADMAIF16", t186_admaif16_tx), 889 WIDGETS("ADMAIF17", t234_admaif17_tx), 890 WIDGETS("ADMAIF18", t234_admaif18_tx), 891 WIDGETS("ADMAIF19", t234_admaif19_tx), 892 WIDGETS("ADMAIF20", t234_admaif20_tx), 893 WIDGETS("I2S1", t186_i2s1_tx), 894 WIDGETS("I2S2", t186_i2s2_tx), 895 WIDGETS("I2S3", t186_i2s3_tx), 896 WIDGETS("I2S4", t186_i2s4_tx), 897 WIDGETS("I2S5", t186_i2s5_tx), 898 WIDGETS("I2S6", t186_i2s6_tx), 899 TX_WIDGETS("DMIC1"), 900 TX_WIDGETS("DMIC2"), 901 TX_WIDGETS("DMIC3"), 902 TX_WIDGETS("DMIC4"), 903 WIDGETS("DSPK1", t186_dspk1_tx), 904 WIDGETS("DSPK2", t186_dspk2_tx), 905 WIDGETS("SFC1", t186_sfc1_tx), 906 WIDGETS("SFC2", t186_sfc2_tx), 907 WIDGETS("SFC3", t186_sfc3_tx), 908 WIDGETS("SFC4", t186_sfc4_tx), 909 WIDGETS("MVC1", t234_mvc1_tx), 910 WIDGETS("MVC2", t234_mvc2_tx), 911 WIDGETS("AMX1 RX1", t234_amx11_tx), 912 WIDGETS("AMX1 RX2", t234_amx12_tx), 913 WIDGETS("AMX1 RX3", t234_amx13_tx), 914 WIDGETS("AMX1 RX4", t234_amx14_tx), 915 WIDGETS("AMX2 RX1", t234_amx21_tx), 916 WIDGETS("AMX2 RX2", t234_amx22_tx), 917 WIDGETS("AMX2 RX3", t234_amx23_tx), 918 WIDGETS("AMX2 RX4", t234_amx24_tx), 919 WIDGETS("AMX3 RX1", t234_amx31_tx), 920 WIDGETS("AMX3 RX2", t234_amx32_tx), 921 WIDGETS("AMX3 RX3", t234_amx33_tx), 922 WIDGETS("AMX3 RX4", t234_amx34_tx), 923 WIDGETS("AMX4 RX1", t234_amx41_tx), 924 WIDGETS("AMX4 RX2", t234_amx42_tx), 925 WIDGETS("AMX4 RX3", t234_amx43_tx), 926 WIDGETS("AMX4 RX4", t234_amx44_tx), 927 TX_WIDGETS("AMX1"), 928 TX_WIDGETS("AMX2"), 929 TX_WIDGETS("AMX3"), 930 TX_WIDGETS("AMX4"), 931 WIDGETS("ADX1", t234_adx1_tx), 932 WIDGETS("ADX2", t234_adx2_tx), 933 WIDGETS("ADX3", t234_adx3_tx), 934 WIDGETS("ADX4", t234_adx4_tx), 935 TX_WIDGETS("ADX1 TX1"), 936 TX_WIDGETS("ADX1 TX2"), 937 TX_WIDGETS("ADX1 TX3"), 938 TX_WIDGETS("ADX1 TX4"), 939 TX_WIDGETS("ADX2 TX1"), 940 TX_WIDGETS("ADX2 TX2"), 941 TX_WIDGETS("ADX2 TX3"), 942 TX_WIDGETS("ADX2 TX4"), 943 TX_WIDGETS("ADX3 TX1"), 944 TX_WIDGETS("ADX3 TX2"), 945 TX_WIDGETS("ADX3 TX3"), 946 TX_WIDGETS("ADX3 TX4"), 947 TX_WIDGETS("ADX4 TX1"), 948 TX_WIDGETS("ADX4 TX2"), 949 TX_WIDGETS("ADX4 TX3"), 950 TX_WIDGETS("ADX4 TX4"), 951 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 952 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 953 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 954 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 955 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 956 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 957 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 958 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 959 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 960 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 961 TX_WIDGETS("MIXER1 TX1"), 962 TX_WIDGETS("MIXER1 TX2"), 963 TX_WIDGETS("MIXER1 TX3"), 964 TX_WIDGETS("MIXER1 TX4"), 965 TX_WIDGETS("MIXER1 TX5"), 966 WIDGETS("ASRC1 RX1", t234_asrc11_tx), 967 WIDGETS("ASRC1 RX2", t234_asrc12_tx), 968 WIDGETS("ASRC1 RX3", t234_asrc13_tx), 969 WIDGETS("ASRC1 RX4", t234_asrc14_tx), 970 WIDGETS("ASRC1 RX5", t234_asrc15_tx), 971 WIDGETS("ASRC1 RX6", t234_asrc16_tx), 972 WIDGETS("ASRC1 RX7", t234_asrc17_tx), 973 TX_WIDGETS("ASRC1 TX1"), 974 TX_WIDGETS("ASRC1 TX2"), 975 TX_WIDGETS("ASRC1 TX3"), 976 TX_WIDGETS("ASRC1 TX4"), 977 TX_WIDGETS("ASRC1 TX5"), 978 TX_WIDGETS("ASRC1 TX6"), 979 }; 980 981 #define TEGRA_COMMON_MUX_ROUTES(name) \ 982 { name " XBAR-TX", NULL, name " Mux" }, \ 983 { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \ 984 { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \ 985 { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \ 986 { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \ 987 { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \ 988 { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \ 989 { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \ 990 { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \ 991 { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \ 992 { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \ 993 { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \ 994 { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \ 995 { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \ 996 { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \ 997 { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \ 998 { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \ 999 { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \ 1000 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1001 { name " Mux", "SFC1", "SFC1 XBAR-RX" }, \ 1002 { name " Mux", "SFC2", "SFC2 XBAR-RX" }, \ 1003 { name " Mux", "SFC3", "SFC3 XBAR-RX" }, \ 1004 { name " Mux", "SFC4", "SFC4 XBAR-RX" }, \ 1005 { name " Mux", "MVC1", "MVC1 XBAR-RX" }, \ 1006 { name " Mux", "MVC2", "MVC2 XBAR-RX" }, \ 1007 { name " Mux", "AMX1", "AMX1 XBAR-RX" }, \ 1008 { name " Mux", "AMX2", "AMX2 XBAR-RX" }, \ 1009 { name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \ 1010 { name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \ 1011 { name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \ 1012 { name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \ 1013 { name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \ 1014 { name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \ 1015 { name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \ 1016 { name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \ 1017 { name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \ 1018 { name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \ 1019 { name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \ 1020 { name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \ 1021 { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, 1022 1023 #define TEGRA186_ONLY_MUX_ROUTES(name) \ 1024 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1025 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1026 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1027 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1028 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1029 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1030 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1031 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1032 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1033 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1034 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1035 { name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \ 1036 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1037 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1038 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1039 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1040 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1041 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1042 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1043 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1044 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1045 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1046 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1047 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1048 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1049 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1050 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1051 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1052 1053 #define TEGRA210_MUX_ROUTES(name) \ 1054 TEGRA_COMMON_MUX_ROUTES(name) 1055 1056 #define TEGRA186_MUX_ROUTES(name) \ 1057 TEGRA_COMMON_MUX_ROUTES(name) \ 1058 TEGRA186_ONLY_MUX_ROUTES(name) 1059 1060 /* Connect FEs with XBAR */ 1061 #define TEGRA_FE_ROUTES(name) \ 1062 { name " XBAR-Playback", NULL, name " Playback" }, \ 1063 { name " XBAR-RX", NULL, name " XBAR-Playback"}, \ 1064 { name " XBAR-Capture", NULL, name " XBAR-TX" }, \ 1065 { name " Capture", NULL, name " XBAR-Capture" }, 1066 1067 /* 1068 * The number of entries in, and order of, this array is closely tied to the 1069 * calculation of tegra210_ahub_codec.num_dapm_routes near the end of 1070 * tegra210_ahub_probe() 1071 */ 1072 static const struct snd_soc_dapm_route tegra210_ahub_routes[] = { 1073 TEGRA_FE_ROUTES("ADMAIF1") 1074 TEGRA_FE_ROUTES("ADMAIF2") 1075 TEGRA_FE_ROUTES("ADMAIF3") 1076 TEGRA_FE_ROUTES("ADMAIF4") 1077 TEGRA_FE_ROUTES("ADMAIF5") 1078 TEGRA_FE_ROUTES("ADMAIF6") 1079 TEGRA_FE_ROUTES("ADMAIF7") 1080 TEGRA_FE_ROUTES("ADMAIF8") 1081 TEGRA_FE_ROUTES("ADMAIF9") 1082 TEGRA_FE_ROUTES("ADMAIF10") 1083 TEGRA210_MUX_ROUTES("ADMAIF1") 1084 TEGRA210_MUX_ROUTES("ADMAIF2") 1085 TEGRA210_MUX_ROUTES("ADMAIF3") 1086 TEGRA210_MUX_ROUTES("ADMAIF4") 1087 TEGRA210_MUX_ROUTES("ADMAIF5") 1088 TEGRA210_MUX_ROUTES("ADMAIF6") 1089 TEGRA210_MUX_ROUTES("ADMAIF7") 1090 TEGRA210_MUX_ROUTES("ADMAIF8") 1091 TEGRA210_MUX_ROUTES("ADMAIF9") 1092 TEGRA210_MUX_ROUTES("ADMAIF10") 1093 TEGRA210_MUX_ROUTES("I2S1") 1094 TEGRA210_MUX_ROUTES("I2S2") 1095 TEGRA210_MUX_ROUTES("I2S3") 1096 TEGRA210_MUX_ROUTES("I2S4") 1097 TEGRA210_MUX_ROUTES("I2S5") 1098 TEGRA210_MUX_ROUTES("SFC1") 1099 TEGRA210_MUX_ROUTES("SFC2") 1100 TEGRA210_MUX_ROUTES("SFC3") 1101 TEGRA210_MUX_ROUTES("SFC4") 1102 TEGRA210_MUX_ROUTES("MVC1") 1103 TEGRA210_MUX_ROUTES("MVC2") 1104 TEGRA210_MUX_ROUTES("AMX1 RX1") 1105 TEGRA210_MUX_ROUTES("AMX1 RX2") 1106 TEGRA210_MUX_ROUTES("AMX1 RX3") 1107 TEGRA210_MUX_ROUTES("AMX1 RX4") 1108 TEGRA210_MUX_ROUTES("AMX2 RX1") 1109 TEGRA210_MUX_ROUTES("AMX2 RX2") 1110 TEGRA210_MUX_ROUTES("AMX2 RX3") 1111 TEGRA210_MUX_ROUTES("AMX2 RX4") 1112 TEGRA210_MUX_ROUTES("ADX1") 1113 TEGRA210_MUX_ROUTES("ADX2") 1114 TEGRA210_MUX_ROUTES("MIXER1 RX1") 1115 TEGRA210_MUX_ROUTES("MIXER1 RX2") 1116 TEGRA210_MUX_ROUTES("MIXER1 RX3") 1117 TEGRA210_MUX_ROUTES("MIXER1 RX4") 1118 TEGRA210_MUX_ROUTES("MIXER1 RX5") 1119 TEGRA210_MUX_ROUTES("MIXER1 RX6") 1120 TEGRA210_MUX_ROUTES("MIXER1 RX7") 1121 TEGRA210_MUX_ROUTES("MIXER1 RX8") 1122 TEGRA210_MUX_ROUTES("MIXER1 RX9") 1123 TEGRA210_MUX_ROUTES("MIXER1 RX10") 1124 }; 1125 1126 static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { 1127 TEGRA_FE_ROUTES("ADMAIF1") 1128 TEGRA_FE_ROUTES("ADMAIF2") 1129 TEGRA_FE_ROUTES("ADMAIF3") 1130 TEGRA_FE_ROUTES("ADMAIF4") 1131 TEGRA_FE_ROUTES("ADMAIF5") 1132 TEGRA_FE_ROUTES("ADMAIF6") 1133 TEGRA_FE_ROUTES("ADMAIF7") 1134 TEGRA_FE_ROUTES("ADMAIF8") 1135 TEGRA_FE_ROUTES("ADMAIF9") 1136 TEGRA_FE_ROUTES("ADMAIF10") 1137 TEGRA_FE_ROUTES("ADMAIF11") 1138 TEGRA_FE_ROUTES("ADMAIF12") 1139 TEGRA_FE_ROUTES("ADMAIF13") 1140 TEGRA_FE_ROUTES("ADMAIF14") 1141 TEGRA_FE_ROUTES("ADMAIF15") 1142 TEGRA_FE_ROUTES("ADMAIF16") 1143 TEGRA_FE_ROUTES("ADMAIF17") 1144 TEGRA_FE_ROUTES("ADMAIF18") 1145 TEGRA_FE_ROUTES("ADMAIF19") 1146 TEGRA_FE_ROUTES("ADMAIF20") 1147 TEGRA186_MUX_ROUTES("ADMAIF1") 1148 TEGRA186_MUX_ROUTES("ADMAIF2") 1149 TEGRA186_MUX_ROUTES("ADMAIF3") 1150 TEGRA186_MUX_ROUTES("ADMAIF4") 1151 TEGRA186_MUX_ROUTES("ADMAIF5") 1152 TEGRA186_MUX_ROUTES("ADMAIF6") 1153 TEGRA186_MUX_ROUTES("ADMAIF7") 1154 TEGRA186_MUX_ROUTES("ADMAIF8") 1155 TEGRA186_MUX_ROUTES("ADMAIF9") 1156 TEGRA186_MUX_ROUTES("ADMAIF10") 1157 TEGRA186_MUX_ROUTES("ADMAIF11") 1158 TEGRA186_MUX_ROUTES("ADMAIF12") 1159 TEGRA186_MUX_ROUTES("ADMAIF13") 1160 TEGRA186_MUX_ROUTES("ADMAIF14") 1161 TEGRA186_MUX_ROUTES("ADMAIF15") 1162 TEGRA186_MUX_ROUTES("ADMAIF16") 1163 TEGRA186_MUX_ROUTES("ADMAIF17") 1164 TEGRA186_MUX_ROUTES("ADMAIF18") 1165 TEGRA186_MUX_ROUTES("ADMAIF19") 1166 TEGRA186_MUX_ROUTES("ADMAIF20") 1167 TEGRA186_MUX_ROUTES("I2S1") 1168 TEGRA186_MUX_ROUTES("I2S2") 1169 TEGRA186_MUX_ROUTES("I2S3") 1170 TEGRA186_MUX_ROUTES("I2S4") 1171 TEGRA186_MUX_ROUTES("I2S5") 1172 TEGRA186_MUX_ROUTES("I2S6") 1173 TEGRA186_MUX_ROUTES("DSPK1") 1174 TEGRA186_MUX_ROUTES("DSPK2") 1175 TEGRA186_MUX_ROUTES("SFC1") 1176 TEGRA186_MUX_ROUTES("SFC2") 1177 TEGRA186_MUX_ROUTES("SFC3") 1178 TEGRA186_MUX_ROUTES("SFC4") 1179 TEGRA186_MUX_ROUTES("MVC1") 1180 TEGRA186_MUX_ROUTES("MVC2") 1181 TEGRA186_MUX_ROUTES("AMX1 RX1") 1182 TEGRA186_MUX_ROUTES("AMX1 RX2") 1183 TEGRA186_MUX_ROUTES("AMX1 RX3") 1184 TEGRA186_MUX_ROUTES("AMX1 RX4") 1185 TEGRA186_MUX_ROUTES("AMX2 RX1") 1186 TEGRA186_MUX_ROUTES("AMX2 RX2") 1187 TEGRA186_MUX_ROUTES("AMX2 RX3") 1188 TEGRA186_MUX_ROUTES("AMX2 RX4") 1189 TEGRA186_MUX_ROUTES("AMX3 RX1") 1190 TEGRA186_MUX_ROUTES("AMX3 RX2") 1191 TEGRA186_MUX_ROUTES("AMX3 RX3") 1192 TEGRA186_MUX_ROUTES("AMX3 RX4") 1193 TEGRA186_MUX_ROUTES("AMX4 RX1") 1194 TEGRA186_MUX_ROUTES("AMX4 RX2") 1195 TEGRA186_MUX_ROUTES("AMX4 RX3") 1196 TEGRA186_MUX_ROUTES("AMX4 RX4") 1197 TEGRA186_MUX_ROUTES("ADX1") 1198 TEGRA186_MUX_ROUTES("ADX2") 1199 TEGRA186_MUX_ROUTES("ADX3") 1200 TEGRA186_MUX_ROUTES("ADX4") 1201 TEGRA186_MUX_ROUTES("MIXER1 RX1") 1202 TEGRA186_MUX_ROUTES("MIXER1 RX2") 1203 TEGRA186_MUX_ROUTES("MIXER1 RX3") 1204 TEGRA186_MUX_ROUTES("MIXER1 RX4") 1205 TEGRA186_MUX_ROUTES("MIXER1 RX5") 1206 TEGRA186_MUX_ROUTES("MIXER1 RX6") 1207 TEGRA186_MUX_ROUTES("MIXER1 RX7") 1208 TEGRA186_MUX_ROUTES("MIXER1 RX8") 1209 TEGRA186_MUX_ROUTES("MIXER1 RX9") 1210 TEGRA186_MUX_ROUTES("MIXER1 RX10") 1211 TEGRA186_MUX_ROUTES("ASRC1 RX1") 1212 TEGRA186_MUX_ROUTES("ASRC1 RX2") 1213 TEGRA186_MUX_ROUTES("ASRC1 RX3") 1214 TEGRA186_MUX_ROUTES("ASRC1 RX4") 1215 TEGRA186_MUX_ROUTES("ASRC1 RX5") 1216 TEGRA186_MUX_ROUTES("ASRC1 RX6") 1217 TEGRA186_MUX_ROUTES("ASRC1 RX7") 1218 }; 1219 1220 static const struct snd_soc_component_driver tegra210_ahub_component = { 1221 .dapm_widgets = tegra210_ahub_widgets, 1222 .num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets), 1223 .dapm_routes = tegra210_ahub_routes, 1224 .num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes), 1225 }; 1226 1227 static const struct snd_soc_component_driver tegra186_ahub_component = { 1228 .dapm_widgets = tegra186_ahub_widgets, 1229 .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets), 1230 .dapm_routes = tegra186_ahub_routes, 1231 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 1232 }; 1233 1234 static const struct snd_soc_component_driver tegra234_ahub_component = { 1235 .dapm_widgets = tegra234_ahub_widgets, 1236 .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets), 1237 .dapm_routes = tegra186_ahub_routes, 1238 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 1239 }; 1240 1241 static const struct regmap_config tegra210_ahub_regmap_config = { 1242 .reg_bits = 32, 1243 .val_bits = 32, 1244 .reg_stride = 4, 1245 .max_register = TEGRA210_MAX_REGISTER_ADDR, 1246 .cache_type = REGCACHE_FLAT, 1247 }; 1248 1249 static const struct regmap_config tegra186_ahub_regmap_config = { 1250 .reg_bits = 32, 1251 .val_bits = 32, 1252 .reg_stride = 4, 1253 .max_register = TEGRA186_MAX_REGISTER_ADDR, 1254 .cache_type = REGCACHE_FLAT, 1255 }; 1256 1257 static const struct tegra_ahub_soc_data soc_data_tegra210 = { 1258 .cmpnt_drv = &tegra210_ahub_component, 1259 .dai_drv = tegra210_ahub_dais, 1260 .num_dais = ARRAY_SIZE(tegra210_ahub_dais), 1261 .regmap_config = &tegra210_ahub_regmap_config, 1262 .mask[0] = TEGRA210_XBAR_REG_MASK_0, 1263 .mask[1] = TEGRA210_XBAR_REG_MASK_1, 1264 .mask[2] = TEGRA210_XBAR_REG_MASK_2, 1265 .mask[3] = TEGRA210_XBAR_REG_MASK_3, 1266 .reg_count = TEGRA210_XBAR_UPDATE_MAX_REG, 1267 }; 1268 1269 static const struct tegra_ahub_soc_data soc_data_tegra186 = { 1270 .cmpnt_drv = &tegra186_ahub_component, 1271 .dai_drv = tegra186_ahub_dais, 1272 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 1273 .regmap_config = &tegra186_ahub_regmap_config, 1274 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 1275 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 1276 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 1277 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 1278 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 1279 }; 1280 1281 static const struct tegra_ahub_soc_data soc_data_tegra234 = { 1282 .cmpnt_drv = &tegra234_ahub_component, 1283 .dai_drv = tegra186_ahub_dais, 1284 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 1285 .regmap_config = &tegra186_ahub_regmap_config, 1286 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 1287 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 1288 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 1289 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 1290 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 1291 }; 1292 1293 static const struct of_device_id tegra_ahub_of_match[] = { 1294 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 }, 1295 { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 }, 1296 { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 }, 1297 {}, 1298 }; 1299 MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); 1300 1301 static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev) 1302 { 1303 struct tegra_ahub *ahub = dev_get_drvdata(dev); 1304 1305 regcache_cache_only(ahub->regmap, true); 1306 regcache_mark_dirty(ahub->regmap); 1307 1308 clk_disable_unprepare(ahub->clk); 1309 1310 return 0; 1311 } 1312 1313 static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev) 1314 { 1315 struct tegra_ahub *ahub = dev_get_drvdata(dev); 1316 int err; 1317 1318 err = clk_prepare_enable(ahub->clk); 1319 if (err) { 1320 dev_err(dev, "failed to enable AHUB clock, err: %d\n", err); 1321 return err; 1322 } 1323 1324 regcache_cache_only(ahub->regmap, false); 1325 regcache_sync(ahub->regmap); 1326 1327 return 0; 1328 } 1329 1330 static int tegra_ahub_probe(struct platform_device *pdev) 1331 { 1332 struct tegra_ahub *ahub; 1333 void __iomem *regs; 1334 int err; 1335 1336 ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL); 1337 if (!ahub) 1338 return -ENOMEM; 1339 1340 ahub->soc_data = of_device_get_match_data(&pdev->dev); 1341 1342 platform_set_drvdata(pdev, ahub); 1343 1344 ahub->clk = devm_clk_get(&pdev->dev, "ahub"); 1345 if (IS_ERR(ahub->clk)) { 1346 dev_err(&pdev->dev, "can't retrieve AHUB clock\n"); 1347 return PTR_ERR(ahub->clk); 1348 } 1349 1350 regs = devm_platform_ioremap_resource(pdev, 0); 1351 if (IS_ERR(regs)) 1352 return PTR_ERR(regs); 1353 1354 ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1355 ahub->soc_data->regmap_config); 1356 if (IS_ERR(ahub->regmap)) { 1357 dev_err(&pdev->dev, "regmap init failed\n"); 1358 return PTR_ERR(ahub->regmap); 1359 } 1360 1361 regcache_cache_only(ahub->regmap, true); 1362 1363 err = devm_snd_soc_register_component(&pdev->dev, 1364 ahub->soc_data->cmpnt_drv, 1365 ahub->soc_data->dai_drv, 1366 ahub->soc_data->num_dais); 1367 if (err) { 1368 dev_err(&pdev->dev, "can't register AHUB component, err: %d\n", 1369 err); 1370 return err; 1371 } 1372 1373 err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 1374 if (err) 1375 return err; 1376 1377 pm_runtime_enable(&pdev->dev); 1378 1379 return 0; 1380 } 1381 1382 static int tegra_ahub_remove(struct platform_device *pdev) 1383 { 1384 pm_runtime_disable(&pdev->dev); 1385 1386 return 0; 1387 } 1388 1389 static const struct dev_pm_ops tegra_ahub_pm_ops = { 1390 SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend, 1391 tegra_ahub_runtime_resume, NULL) 1392 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1393 pm_runtime_force_resume) 1394 }; 1395 1396 static struct platform_driver tegra_ahub_driver = { 1397 .probe = tegra_ahub_probe, 1398 .remove = tegra_ahub_remove, 1399 .driver = { 1400 .name = "tegra210-ahub", 1401 .of_match_table = tegra_ahub_of_match, 1402 .pm = &tegra_ahub_pm_ops, 1403 }, 1404 }; 1405 module_platform_driver(tegra_ahub_driver); 1406 1407 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 1408 MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>"); 1409 MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver"); 1410 MODULE_LICENSE("GPL v2"); 1411