1f74028e1SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2f74028e1SSameer Pujar /* 3f74028e1SSameer Pujar * tegra210_admaif.h - Tegra ADMAIF registers 4f74028e1SSameer Pujar * 5f74028e1SSameer Pujar * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6f74028e1SSameer Pujar * 7f74028e1SSameer Pujar */ 8f74028e1SSameer Pujar 9f74028e1SSameer Pujar #ifndef __TEGRA_ADMAIF_H__ 10f74028e1SSameer Pujar #define __TEGRA_ADMAIF_H__ 11f74028e1SSameer Pujar 12f74028e1SSameer Pujar #define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40 13f74028e1SSameer Pujar /* Tegra210 specific */ 14f74028e1SSameer Pujar #define TEGRA210_ADMAIF_LAST_REG 0x75f 15f74028e1SSameer Pujar #define TEGRA210_ADMAIF_CHANNEL_COUNT 10 16f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX_BASE 0x0 17f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX_BASE 0x300 18f74028e1SSameer Pujar #define TEGRA210_ADMAIF_GLOBAL_BASE 0x700 19f74028e1SSameer Pujar /* Tegra186 specific */ 20f74028e1SSameer Pujar #define TEGRA186_ADMAIF_LAST_REG 0xd5f 21f74028e1SSameer Pujar #define TEGRA186_ADMAIF_CHANNEL_COUNT 20 22f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX_BASE 0x0 23f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX_BASE 0x500 24f74028e1SSameer Pujar #define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00 25f74028e1SSameer Pujar /* Global registers */ 26f74028e1SSameer Pujar #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0 27f74028e1SSameer Pujar #define TEGRA_ADMAIF_GLOBAL_CG_0 0x8 28f74028e1SSameer Pujar #define TEGRA_ADMAIF_GLOBAL_STATUS 0x10 29f74028e1SSameer Pujar #define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20 30f74028e1SSameer Pujar #define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24 31f74028e1SSameer Pujar /* RX channel registers */ 32f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_ENABLE 0x0 33f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_SOFT_RESET 0x4 34f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_STATUS 0xc 35f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_INT_STATUS 0x10 36f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_INT_MASK 0x14 37f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_INT_SET 0x18 38f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c 39f74028e1SSameer Pujar #define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20 40f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28 41f74028e1SSameer Pujar #define TEGRA_ADMAIF_RX_FIFO_READ 0x2c 42f74028e1SSameer Pujar /* TX channel registers */ 43f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_ENABLE 0x0 44f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_SOFT_RESET 0x4 45f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_STATUS 0xc 46f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_INT_STATUS 0x10 47f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_INT_MASK 0x14 48f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_INT_SET 0x18 49f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c 50f74028e1SSameer Pujar #define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20 51f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28 52f74028e1SSameer Pujar #define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c 53f74028e1SSameer Pujar /* Bit fields */ 54f74028e1SSameer Pujar #define PACK8_EN_SHIFT 31 55f74028e1SSameer Pujar #define PACK8_EN_MASK BIT(PACK8_EN_SHIFT) 56f74028e1SSameer Pujar #define PACK8_EN BIT(PACK8_EN_SHIFT) 57f74028e1SSameer Pujar #define PACK16_EN_SHIFT 30 58f74028e1SSameer Pujar #define PACK16_EN_MASK BIT(PACK16_EN_SHIFT) 59f74028e1SSameer Pujar #define PACK16_EN BIT(PACK16_EN_SHIFT) 60f74028e1SSameer Pujar #define TX_ENABLE_SHIFT 0 61f74028e1SSameer Pujar #define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT) 62f74028e1SSameer Pujar #define TX_ENABLE BIT(TX_ENABLE_SHIFT) 63f74028e1SSameer Pujar #define RX_ENABLE_SHIFT 0 64f74028e1SSameer Pujar #define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT) 65f74028e1SSameer Pujar #define RX_ENABLE BIT(RX_ENABLE_SHIFT) 66f74028e1SSameer Pujar #define SW_RESET_MASK 1 67f74028e1SSameer Pujar #define SW_RESET 1 68f74028e1SSameer Pujar /* Default values - Tegra210 */ 69f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 70f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 71f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208 72f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b 73f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e 74f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211 75f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214 76f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217 77f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a 78f74028e1SSameer Pujar #define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d 79f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 80f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 81f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208 82f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b 83f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e 84f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211 85f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214 86f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217 87f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a 88f74028e1SSameer Pujar #define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d 89f74028e1SSameer Pujar /* Default values - Tegra186 */ 90f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 91f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 92f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308 93f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c 94f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210 95f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213 96f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216 97f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219 98f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c 99f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f 100f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222 101f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225 102f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228 103f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b 104f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e 105f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231 106f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234 107f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237 108f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a 109f74028e1SSameer Pujar #define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d 110f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 111f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 112f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308 113f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c 114f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210 115f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213 116f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216 117f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219 118f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c 119f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f 120f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222 121f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225 122f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228 123f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b 124f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e 125f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231 126f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234 127f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237 128f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a 129f74028e1SSameer Pujar #define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d 130f74028e1SSameer Pujar 131f74028e1SSameer Pujar enum { 132f74028e1SSameer Pujar DATA_8BIT, 133f74028e1SSameer Pujar DATA_16BIT, 134f74028e1SSameer Pujar DATA_32BIT 135f74028e1SSameer Pujar }; 136f74028e1SSameer Pujar 137f74028e1SSameer Pujar enum { 138f74028e1SSameer Pujar ADMAIF_RX_PATH, 139f74028e1SSameer Pujar ADMAIF_TX_PATH, 140f74028e1SSameer Pujar ADMAIF_PATHS, 141f74028e1SSameer Pujar }; 142f74028e1SSameer Pujar 143f74028e1SSameer Pujar struct tegra_admaif_soc_data { 144f74028e1SSameer Pujar const struct snd_soc_component_driver *cmpnt; 145f74028e1SSameer Pujar const struct regmap_config *regmap_conf; 146f74028e1SSameer Pujar struct snd_soc_dai_driver *dais; 147f74028e1SSameer Pujar unsigned int global_base; 148f74028e1SSameer Pujar unsigned int tx_base; 149f74028e1SSameer Pujar unsigned int rx_base; 150f74028e1SSameer Pujar unsigned int num_ch; 151f74028e1SSameer Pujar }; 152f74028e1SSameer Pujar 153f74028e1SSameer Pujar struct tegra_admaif { 154f74028e1SSameer Pujar struct snd_dmaengine_dai_dma_data *capture_dma_data; 155f74028e1SSameer Pujar struct snd_dmaengine_dai_dma_data *playback_dma_data; 156f74028e1SSameer Pujar const struct tegra_admaif_soc_data *soc_data; 157f74028e1SSameer Pujar unsigned int *mono_to_stereo[ADMAIF_PATHS]; 158f74028e1SSameer Pujar unsigned int *stereo_to_mono[ADMAIF_PATHS]; 159f74028e1SSameer Pujar struct regmap *regmap; 160f74028e1SSameer Pujar }; 161f74028e1SSameer Pujar 162f74028e1SSameer Pujar #endif 163