1ef280d39SStephen Warren /* 2ef280d39SStephen Warren * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver 3ef280d39SStephen Warren * 4ef280d39SStephen Warren * Author: Stephen Warren <swarren@nvidia.com> 5ef280d39SStephen Warren * Copyright (C) 2011 - NVIDIA, Inc. 6ef280d39SStephen Warren * 7ef280d39SStephen Warren * Based on code copyright/by: 8ef280d39SStephen Warren * Copyright (c) 2008-2009, NVIDIA Corporation 9ef280d39SStephen Warren * 10ef280d39SStephen Warren * This program is free software; you can redistribute it and/or 11ef280d39SStephen Warren * modify it under the terms of the GNU General Public License 12ef280d39SStephen Warren * version 2 as published by the Free Software Foundation. 13ef280d39SStephen Warren * 14ef280d39SStephen Warren * This program is distributed in the hope that it will be useful, but 15ef280d39SStephen Warren * WITHOUT ANY WARRANTY; without even the implied warranty of 16ef280d39SStephen Warren * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17ef280d39SStephen Warren * General Public License for more details. 18ef280d39SStephen Warren * 19ef280d39SStephen Warren * You should have received a copy of the GNU General Public License 20ef280d39SStephen Warren * along with this program; if not, write to the Free Software 21ef280d39SStephen Warren * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 22ef280d39SStephen Warren * 02110-1301 USA 23ef280d39SStephen Warren * 24ef280d39SStephen Warren */ 25ef280d39SStephen Warren 26896637acSStephen Warren #ifndef __TEGRA20_SPDIF_H__ 27896637acSStephen Warren #define __TEGRA20_SPDIF_H__ 28ef280d39SStephen Warren 29ef280d39SStephen Warren #include "tegra_pcm.h" 30ef280d39SStephen Warren 31896637acSStephen Warren /* Offsets from TEGRA20_SPDIF_BASE */ 32ef280d39SStephen Warren 33896637acSStephen Warren #define TEGRA20_SPDIF_CTRL 0x0 34896637acSStephen Warren #define TEGRA20_SPDIF_STATUS 0x4 35896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL 0x8 36896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C 37896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT 0x40 38896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN 0x80 39896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_A 0x100 40896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_B 0x104 41896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_C 0x108 42896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_D 0x10C 43896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_E 0x110 44896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_F 0x114 45896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_A 0x140 46896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_B 0x144 47896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_C 0x148 48896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_D 0x14C 49896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_E 0x150 50896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_F 0x154 51896637acSStephen Warren #define TEGRA20_SPDIF_USR_STA_RX_A 0x180 52896637acSStephen Warren #define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0 53ef280d39SStephen Warren 54896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CTRL */ 55ef280d39SStephen Warren 56ef280d39SStephen Warren /* Start capturing from 0=right, 1=left channel */ 57896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30) 58ef280d39SStephen Warren 59ef280d39SStephen Warren /* SPDIF receiver(RX) enable */ 60896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29) 61ef280d39SStephen Warren 62ef280d39SStephen Warren /* SPDIF Transmitter(TX) enable */ 63896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28) 64ef280d39SStephen Warren 65ef280d39SStephen Warren /* Transmit Channel status */ 66896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27) 67ef280d39SStephen Warren 68ef280d39SStephen Warren /* Transmit user Data */ 69896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26) 70ef280d39SStephen Warren 71ef280d39SStephen Warren /* Interrupt on transmit error */ 72896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25) 73ef280d39SStephen Warren 74ef280d39SStephen Warren /* Interrupt on receive error */ 75896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24) 76ef280d39SStephen Warren 77ef280d39SStephen Warren /* Interrupt on invalid preamble */ 78896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_P (1 << 23) 79ef280d39SStephen Warren 80ef280d39SStephen Warren /* Interrupt on "B" preamble */ 81896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_B (1 << 22) 82ef280d39SStephen Warren 83ef280d39SStephen Warren /* Interrupt when block of channel status received */ 84896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_C (1 << 21) 85ef280d39SStephen Warren 86ef280d39SStephen Warren /* Interrupt when a valid information unit (IU) is received */ 87896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_U (1 << 20) 88ef280d39SStephen Warren 89ef280d39SStephen Warren /* Interrupt when RX user FIFO attention level is reached */ 90896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19) 91ef280d39SStephen Warren 92ef280d39SStephen Warren /* Interrupt when TX user FIFO attention level is reached */ 93896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18) 94ef280d39SStephen Warren 95ef280d39SStephen Warren /* Interrupt when RX data FIFO attention level is reached */ 96896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17) 97ef280d39SStephen Warren 98ef280d39SStephen Warren /* Interrupt when TX data FIFO attention level is reached */ 99896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16) 100ef280d39SStephen Warren 101ef280d39SStephen Warren /* Loopback test mode enable */ 102896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15) 103ef280d39SStephen Warren 104ef280d39SStephen Warren /* 105ef280d39SStephen Warren * Pack data mode: 106ef280d39SStephen Warren * 0 = Single data (16 bit needs to be padded to match the 107ef280d39SStephen Warren * interface data bit size). 108ef280d39SStephen Warren * 1 = Packeted left/right channel data into a single word. 109ef280d39SStephen Warren */ 110896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_PACK (1 << 14) 111ef280d39SStephen Warren 112ef280d39SStephen Warren /* 113ef280d39SStephen Warren * 00 = 16bit data 114ef280d39SStephen Warren * 01 = 20bit data 115ef280d39SStephen Warren * 10 = 24bit data 116ef280d39SStephen Warren * 11 = raw data 117ef280d39SStephen Warren */ 118896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_16BIT 0 119896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_20BIT 1 120896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_24BIT 2 121896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_RAW 3 122ef280d39SStephen Warren 123896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12 124896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 125896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 126896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 127896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 128896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 129ef280d39SStephen Warren 130896637acSStephen Warren /* Fields in TEGRA20_SPDIF_STATUS */ 131ef280d39SStephen Warren 132ef280d39SStephen Warren /* 133ef280d39SStephen Warren * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must 134ef280d39SStephen Warren * write a 1 to the corresponding bit location to clear the status. 135ef280d39SStephen Warren */ 136ef280d39SStephen Warren 137ef280d39SStephen Warren /* 138ef280d39SStephen Warren * Receiver(RX) shifter is busy receiving data. 139ef280d39SStephen Warren * This bit is asserted when the receiver first locked onto the 140ef280d39SStephen Warren * preamble of the data stream after RX_EN is asserted. This bit is 141ef280d39SStephen Warren * deasserted when either, 142ef280d39SStephen Warren * (a) the end of a frame is reached after RX_EN is deeasserted, or 143ef280d39SStephen Warren * (b) the SPDIF data stream becomes inactive. 144ef280d39SStephen Warren */ 145896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29) 146ef280d39SStephen Warren 147ef280d39SStephen Warren /* 148ef280d39SStephen Warren * Transmitter(TX) shifter is busy transmitting data. 149ef280d39SStephen Warren * This bit is asserted when TX_EN is asserted. 150ef280d39SStephen Warren * This bit is deasserted when the end of a frame is reached after 151ef280d39SStephen Warren * TX_EN is deasserted. 152ef280d39SStephen Warren */ 153896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28) 154ef280d39SStephen Warren 155ef280d39SStephen Warren /* 156ef280d39SStephen Warren * TX is busy shifting out channel status. 157ef280d39SStephen Warren * This bit is asserted when both TX_EN and TC_EN are asserted and 158ef280d39SStephen Warren * data from CH_STA_TX_A register is loaded into the internal shifter. 159ef280d39SStephen Warren * This bit is deasserted when either, 160ef280d39SStephen Warren * (a) the end of a frame is reached after TX_EN is deasserted, or 161ef280d39SStephen Warren * (b) CH_STA_TX_F register is loaded into the internal shifter. 162ef280d39SStephen Warren */ 163896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27) 164ef280d39SStephen Warren 165ef280d39SStephen Warren /* 166ef280d39SStephen Warren * TX User data FIFO busy. 167ef280d39SStephen Warren * This bit is asserted when TX_EN and TXU_EN are asserted and 168ef280d39SStephen Warren * there's data in the TX user FIFO. This bit is deassert when either, 169ef280d39SStephen Warren * (a) the end of a frame is reached after TX_EN is deasserted, or 170ef280d39SStephen Warren * (b) there's no data left in the TX user FIFO. 171ef280d39SStephen Warren */ 172896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26) 173ef280d39SStephen Warren 174ef280d39SStephen Warren /* TX FIFO Underrun error status */ 175896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25) 176ef280d39SStephen Warren 177ef280d39SStephen Warren /* RX FIFO Overrun error status */ 178896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24) 179ef280d39SStephen Warren 180ef280d39SStephen Warren /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */ 181896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_P (1 << 23) 182ef280d39SStephen Warren 183ef280d39SStephen Warren /* B-preamble detection status: 0=not detected, 1=B-preamble detected */ 184896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_B (1 << 22) 185ef280d39SStephen Warren 186ef280d39SStephen Warren /* 187ef280d39SStephen Warren * RX channel block data receive status: 188ef280d39SStephen Warren * 0=entire block not recieved yet. 189ef280d39SStephen Warren * 1=received entire block of channel status, 190ef280d39SStephen Warren */ 191896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_C (1 << 21) 192ef280d39SStephen Warren 193ef280d39SStephen Warren /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */ 194896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_U (1 << 20) 195ef280d39SStephen Warren 196ef280d39SStephen Warren /* 197ef280d39SStephen Warren * RX User FIFO Status: 198ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 199ef280d39SStephen Warren */ 200896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19) 201ef280d39SStephen Warren 202ef280d39SStephen Warren /* 203ef280d39SStephen Warren * TX User FIFO Status: 204ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 205ef280d39SStephen Warren */ 206896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18) 207ef280d39SStephen Warren 208ef280d39SStephen Warren /* 209ef280d39SStephen Warren * RX Data FIFO Status: 210ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 211ef280d39SStephen Warren */ 212896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17) 213ef280d39SStephen Warren 214ef280d39SStephen Warren /* 215ef280d39SStephen Warren * TX Data FIFO Status: 216ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 217ef280d39SStephen Warren */ 218896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16) 219ef280d39SStephen Warren 220896637acSStephen Warren /* Fields in TEGRA20_SPDIF_STROBE_CTRL */ 221ef280d39SStephen Warren 222ef280d39SStephen Warren /* 223ef280d39SStephen Warren * Indicates the approximate number of detected SPDIFIN clocks within a 224ef280d39SStephen Warren * bi-phase period. 225ef280d39SStephen Warren */ 226896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16 227896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT) 228ef280d39SStephen Warren 229ef280d39SStephen Warren /* Data strobe mode: 0=Auto-locked 1=Manual locked */ 230896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15) 231ef280d39SStephen Warren 232ef280d39SStephen Warren /* 233ef280d39SStephen Warren * Manual data strobe time within the bi-phase clock period (in terms of 234ef280d39SStephen Warren * the number of over-sampling clocks). 235ef280d39SStephen Warren */ 236896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8 237896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT) 238ef280d39SStephen Warren 239ef280d39SStephen Warren /* 240ef280d39SStephen Warren * Manual SPDIFIN bi-phase clock period (in terms of the number of 241ef280d39SStephen Warren * over-sampling clocks). 242ef280d39SStephen Warren */ 243896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0 244896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT) 245ef280d39SStephen Warren 246ef280d39SStephen Warren /* Fields in SPDIF_DATA_FIFO_CSR */ 247ef280d39SStephen Warren 248ef280d39SStephen Warren /* Clear Receiver User FIFO (RX USR.FIFO) */ 249896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31) 250ef280d39SStephen Warren 251896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0 252896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1 253896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2 254896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3 255ef280d39SStephen Warren 256ef280d39SStephen Warren /* RU FIFO attention level */ 257896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29 258896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \ 259896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 260896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \ 261896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 262896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \ 263896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 264896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \ 265896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 266896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \ 267896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 268ef280d39SStephen Warren 269ef280d39SStephen Warren /* Number of RX USR.FIFO levels with valid data. */ 270896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24 271896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT) 272ef280d39SStephen Warren 273ef280d39SStephen Warren /* Clear Transmitter User FIFO (TX USR.FIFO) */ 274896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23) 275ef280d39SStephen Warren 276ef280d39SStephen Warren /* TU FIFO attention level */ 277896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21 278896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \ 279896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 280896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \ 281896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 282896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \ 283896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 284896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \ 285896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 286896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \ 287896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 288ef280d39SStephen Warren 289ef280d39SStephen Warren /* Number of TX USR.FIFO levels that could be filled. */ 290896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16 291896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT) 292ef280d39SStephen Warren 293ef280d39SStephen Warren /* Clear Receiver Data FIFO (RX DATA.FIFO) */ 294896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15) 295ef280d39SStephen Warren 296896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0 297896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1 298896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2 299896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3 300ef280d39SStephen Warren 301ef280d39SStephen Warren /* RU FIFO attention level */ 302896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13 303896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \ 304896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 305896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \ 306896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 307896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \ 308896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 309896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \ 310896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 311896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \ 312896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 313ef280d39SStephen Warren 314ef280d39SStephen Warren /* Number of RX DATA.FIFO levels with valid data. */ 315896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8 316896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT) 317ef280d39SStephen Warren 318ef280d39SStephen Warren /* Clear Transmitter Data FIFO (TX DATA.FIFO) */ 319896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7) 320ef280d39SStephen Warren 321ef280d39SStephen Warren /* TU FIFO attention level */ 322896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5 323896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \ 324896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 325896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \ 326896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 327896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \ 328896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 329896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \ 330896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 331896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \ 332896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 333ef280d39SStephen Warren 334ef280d39SStephen Warren /* Number of TX DATA.FIFO levels that could be filled. */ 335896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0 336896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT) 337ef280d39SStephen Warren 338896637acSStephen Warren /* Fields in TEGRA20_SPDIF_DATA_OUT */ 339ef280d39SStephen Warren 340ef280d39SStephen Warren /* 341ef280d39SStephen Warren * This register has 5 different formats: 342ef280d39SStephen Warren * 16-bit (BIT_MODE=00, PACK=0) 343ef280d39SStephen Warren * 20-bit (BIT_MODE=01, PACK=0) 344ef280d39SStephen Warren * 24-bit (BIT_MODE=10, PACK=0) 345ef280d39SStephen Warren * raw (BIT_MODE=11, PACK=0) 346ef280d39SStephen Warren * 16-bit packed (BIT_MODE=00, PACK=1) 347ef280d39SStephen Warren */ 348ef280d39SStephen Warren 349896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0 350896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT) 351ef280d39SStephen Warren 352896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0 353896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT) 354ef280d39SStephen Warren 355896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0 356896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT) 357ef280d39SStephen Warren 358896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31) 359896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30) 360896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29) 361896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28) 362ef280d39SStephen Warren 363896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8 364896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT) 365ef280d39SStephen Warren 366896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4 367896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT) 368ef280d39SStephen Warren 369896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0 370896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT) 371ef280d39SStephen Warren 372896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16 373896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT) 374ef280d39SStephen Warren 375896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0 376896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT) 377ef280d39SStephen Warren 378896637acSStephen Warren /* Fields in TEGRA20_SPDIF_DATA_IN */ 379ef280d39SStephen Warren 380ef280d39SStephen Warren /* 381ef280d39SStephen Warren * This register has 5 different formats: 382ef280d39SStephen Warren * 16-bit (BIT_MODE=00, PACK=0) 383ef280d39SStephen Warren * 20-bit (BIT_MODE=01, PACK=0) 384ef280d39SStephen Warren * 24-bit (BIT_MODE=10, PACK=0) 385ef280d39SStephen Warren * raw (BIT_MODE=11, PACK=0) 386ef280d39SStephen Warren * 16-bit packed (BIT_MODE=00, PACK=1) 387ef280d39SStephen Warren * 388ef280d39SStephen Warren * Bits 31:24 are common to all modes except 16-bit packed 389ef280d39SStephen Warren */ 390ef280d39SStephen Warren 391896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31) 392896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30) 393896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29) 394896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28) 395ef280d39SStephen Warren 396896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24 397896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT) 398ef280d39SStephen Warren 399896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0 400896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT) 401ef280d39SStephen Warren 402896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0 403896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT) 404ef280d39SStephen Warren 405896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0 406896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT) 407ef280d39SStephen Warren 408896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8 409896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT) 410ef280d39SStephen Warren 411896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4 412896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT) 413ef280d39SStephen Warren 414896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0 415896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT) 416ef280d39SStephen Warren 417896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16 418896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT) 419ef280d39SStephen Warren 420896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0 421896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT) 422ef280d39SStephen Warren 423896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_A */ 424896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_B */ 425896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_C */ 426896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_D */ 427896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_E */ 428896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_F */ 429ef280d39SStephen Warren 430ef280d39SStephen Warren /* 431ef280d39SStephen Warren * The 6-word receive channel data page buffer holds a block (192 frames) of 432ef280d39SStephen Warren * channel status information. The order of receive is from LSB to MSB 433ef280d39SStephen Warren * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A. 434ef280d39SStephen Warren */ 435ef280d39SStephen Warren 436896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_A */ 437896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_B */ 438896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_C */ 439896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_D */ 440896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_E */ 441896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_F */ 442ef280d39SStephen Warren 443ef280d39SStephen Warren /* 444ef280d39SStephen Warren * The 6-word transmit channel data page buffer holds a block (192 frames) of 445ef280d39SStephen Warren * channel status information. The order of transmission is from LSB to MSB 446ef280d39SStephen Warren * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A. 447ef280d39SStephen Warren */ 448ef280d39SStephen Warren 449896637acSStephen Warren /* Fields in TEGRA20_SPDIF_USR_STA_RX_A */ 450ef280d39SStephen Warren 451ef280d39SStephen Warren /* 452ef280d39SStephen Warren * This 4-word deep FIFO receives user FIFO field information. The order of 453ef280d39SStephen Warren * receive is from LSB to MSB bit. 454ef280d39SStephen Warren */ 455ef280d39SStephen Warren 456896637acSStephen Warren /* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */ 457ef280d39SStephen Warren 458ef280d39SStephen Warren /* 459ef280d39SStephen Warren * This 4-word deep FIFO transmits user FIFO field information. The order of 460ef280d39SStephen Warren * transmission is from LSB to MSB bit. 461ef280d39SStephen Warren */ 462ef280d39SStephen Warren 463896637acSStephen Warren struct tegra20_spdif { 464ef280d39SStephen Warren struct clk *clk_spdif_out; 465ef280d39SStephen Warren struct tegra_pcm_dma_params capture_dma_data; 466ef280d39SStephen Warren struct tegra_pcm_dma_params playback_dma_data; 4675939ae74SStephen Warren struct regmap *regmap; 468ef280d39SStephen Warren u32 reg_ctrl; 469ef280d39SStephen Warren }; 470ef280d39SStephen Warren 471ef280d39SStephen Warren #endif 472