12b27bdccSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ef280d39SStephen Warren /* 3ef280d39SStephen Warren * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver 4ef280d39SStephen Warren * 5ef280d39SStephen Warren * Author: Stephen Warren <swarren@nvidia.com> 6ef280d39SStephen Warren * Copyright (C) 2011 - NVIDIA, Inc. 7ef280d39SStephen Warren * 8ef280d39SStephen Warren * Based on code copyright/by: 9ef280d39SStephen Warren * Copyright (c) 2008-2009, NVIDIA Corporation 10ef280d39SStephen Warren */ 11ef280d39SStephen Warren 12896637acSStephen Warren #ifndef __TEGRA20_SPDIF_H__ 13896637acSStephen Warren #define __TEGRA20_SPDIF_H__ 14ef280d39SStephen Warren 15ef280d39SStephen Warren #include "tegra_pcm.h" 16ef280d39SStephen Warren 17896637acSStephen Warren /* Offsets from TEGRA20_SPDIF_BASE */ 18ef280d39SStephen Warren 19896637acSStephen Warren #define TEGRA20_SPDIF_CTRL 0x0 20896637acSStephen Warren #define TEGRA20_SPDIF_STATUS 0x4 21896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL 0x8 22896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C 23896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT 0x40 24896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN 0x80 25896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_A 0x100 26896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_B 0x104 27896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_C 0x108 28896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_D 0x10C 29896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_E 0x110 30896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_RX_F 0x114 31896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_A 0x140 32896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_B 0x144 33896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_C 0x148 34896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_D 0x14C 35896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_E 0x150 36896637acSStephen Warren #define TEGRA20_SPDIF_CH_STA_TX_F 0x154 37896637acSStephen Warren #define TEGRA20_SPDIF_USR_STA_RX_A 0x180 38896637acSStephen Warren #define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0 39ef280d39SStephen Warren 40896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CTRL */ 41ef280d39SStephen Warren 42ef280d39SStephen Warren /* Start capturing from 0=right, 1=left channel */ 43896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30) 44ef280d39SStephen Warren 45ef280d39SStephen Warren /* SPDIF receiver(RX) enable */ 46896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29) 47ef280d39SStephen Warren 48ef280d39SStephen Warren /* SPDIF Transmitter(TX) enable */ 49896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28) 50ef280d39SStephen Warren 51ef280d39SStephen Warren /* Transmit Channel status */ 52896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27) 53ef280d39SStephen Warren 54ef280d39SStephen Warren /* Transmit user Data */ 55896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26) 56ef280d39SStephen Warren 57ef280d39SStephen Warren /* Interrupt on transmit error */ 58896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25) 59ef280d39SStephen Warren 60ef280d39SStephen Warren /* Interrupt on receive error */ 61896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24) 62ef280d39SStephen Warren 63ef280d39SStephen Warren /* Interrupt on invalid preamble */ 64896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_P (1 << 23) 65ef280d39SStephen Warren 66ef280d39SStephen Warren /* Interrupt on "B" preamble */ 67896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_B (1 << 22) 68ef280d39SStephen Warren 69ef280d39SStephen Warren /* Interrupt when block of channel status received */ 70896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_C (1 << 21) 71ef280d39SStephen Warren 72ef280d39SStephen Warren /* Interrupt when a valid information unit (IU) is received */ 73896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_IE_U (1 << 20) 74ef280d39SStephen Warren 75ef280d39SStephen Warren /* Interrupt when RX user FIFO attention level is reached */ 76896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19) 77ef280d39SStephen Warren 78ef280d39SStephen Warren /* Interrupt when TX user FIFO attention level is reached */ 79896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18) 80ef280d39SStephen Warren 81ef280d39SStephen Warren /* Interrupt when RX data FIFO attention level is reached */ 82896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17) 83ef280d39SStephen Warren 84ef280d39SStephen Warren /* Interrupt when TX data FIFO attention level is reached */ 85896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16) 86ef280d39SStephen Warren 87ef280d39SStephen Warren /* Loopback test mode enable */ 88896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15) 89ef280d39SStephen Warren 90ef280d39SStephen Warren /* 91ef280d39SStephen Warren * Pack data mode: 92ef280d39SStephen Warren * 0 = Single data (16 bit needs to be padded to match the 93ef280d39SStephen Warren * interface data bit size). 94ef280d39SStephen Warren * 1 = Packeted left/right channel data into a single word. 95ef280d39SStephen Warren */ 96896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_PACK (1 << 14) 97ef280d39SStephen Warren 98ef280d39SStephen Warren /* 99ef280d39SStephen Warren * 00 = 16bit data 100ef280d39SStephen Warren * 01 = 20bit data 101ef280d39SStephen Warren * 10 = 24bit data 102ef280d39SStephen Warren * 11 = raw data 103ef280d39SStephen Warren */ 104896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_16BIT 0 105896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_20BIT 1 106896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_24BIT 2 107896637acSStephen Warren #define TEGRA20_SPDIF_BIT_MODE_RAW 3 108ef280d39SStephen Warren 109896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12 110896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 111896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 112896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 113896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 114896637acSStephen Warren #define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) 115ef280d39SStephen Warren 116896637acSStephen Warren /* Fields in TEGRA20_SPDIF_STATUS */ 117ef280d39SStephen Warren 118ef280d39SStephen Warren /* 119ef280d39SStephen Warren * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must 120ef280d39SStephen Warren * write a 1 to the corresponding bit location to clear the status. 121ef280d39SStephen Warren */ 122ef280d39SStephen Warren 123ef280d39SStephen Warren /* 124ef280d39SStephen Warren * Receiver(RX) shifter is busy receiving data. 125ef280d39SStephen Warren * This bit is asserted when the receiver first locked onto the 126ef280d39SStephen Warren * preamble of the data stream after RX_EN is asserted. This bit is 127ef280d39SStephen Warren * deasserted when either, 128ef280d39SStephen Warren * (a) the end of a frame is reached after RX_EN is deeasserted, or 129ef280d39SStephen Warren * (b) the SPDIF data stream becomes inactive. 130ef280d39SStephen Warren */ 131896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29) 132ef280d39SStephen Warren 133ef280d39SStephen Warren /* 134ef280d39SStephen Warren * Transmitter(TX) shifter is busy transmitting data. 135ef280d39SStephen Warren * This bit is asserted when TX_EN is asserted. 136ef280d39SStephen Warren * This bit is deasserted when the end of a frame is reached after 137ef280d39SStephen Warren * TX_EN is deasserted. 138ef280d39SStephen Warren */ 139896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28) 140ef280d39SStephen Warren 141ef280d39SStephen Warren /* 142ef280d39SStephen Warren * TX is busy shifting out channel status. 143ef280d39SStephen Warren * This bit is asserted when both TX_EN and TC_EN are asserted and 144ef280d39SStephen Warren * data from CH_STA_TX_A register is loaded into the internal shifter. 145ef280d39SStephen Warren * This bit is deasserted when either, 146ef280d39SStephen Warren * (a) the end of a frame is reached after TX_EN is deasserted, or 147ef280d39SStephen Warren * (b) CH_STA_TX_F register is loaded into the internal shifter. 148ef280d39SStephen Warren */ 149896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27) 150ef280d39SStephen Warren 151ef280d39SStephen Warren /* 152ef280d39SStephen Warren * TX User data FIFO busy. 153ef280d39SStephen Warren * This bit is asserted when TX_EN and TXU_EN are asserted and 154ef280d39SStephen Warren * there's data in the TX user FIFO. This bit is deassert when either, 155ef280d39SStephen Warren * (a) the end of a frame is reached after TX_EN is deasserted, or 156ef280d39SStephen Warren * (b) there's no data left in the TX user FIFO. 157ef280d39SStephen Warren */ 158896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26) 159ef280d39SStephen Warren 160ef280d39SStephen Warren /* TX FIFO Underrun error status */ 161896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25) 162ef280d39SStephen Warren 163ef280d39SStephen Warren /* RX FIFO Overrun error status */ 164896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24) 165ef280d39SStephen Warren 166ef280d39SStephen Warren /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */ 167896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_P (1 << 23) 168ef280d39SStephen Warren 169ef280d39SStephen Warren /* B-preamble detection status: 0=not detected, 1=B-preamble detected */ 170896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_B (1 << 22) 171ef280d39SStephen Warren 172ef280d39SStephen Warren /* 173ef280d39SStephen Warren * RX channel block data receive status: 174ef280d39SStephen Warren * 0=entire block not recieved yet. 175ef280d39SStephen Warren * 1=received entire block of channel status, 176ef280d39SStephen Warren */ 177896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_C (1 << 21) 178ef280d39SStephen Warren 179ef280d39SStephen Warren /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */ 180896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_IS_U (1 << 20) 181ef280d39SStephen Warren 182ef280d39SStephen Warren /* 183ef280d39SStephen Warren * RX User FIFO Status: 184ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 185ef280d39SStephen Warren */ 186896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19) 187ef280d39SStephen Warren 188ef280d39SStephen Warren /* 189ef280d39SStephen Warren * TX User FIFO Status: 190ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 191ef280d39SStephen Warren */ 192896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18) 193ef280d39SStephen Warren 194ef280d39SStephen Warren /* 195ef280d39SStephen Warren * RX Data FIFO Status: 196ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 197ef280d39SStephen Warren */ 198896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17) 199ef280d39SStephen Warren 200ef280d39SStephen Warren /* 201ef280d39SStephen Warren * TX Data FIFO Status: 202ef280d39SStephen Warren * 1=attention level reached, 0=attention level not reached. 203ef280d39SStephen Warren */ 204896637acSStephen Warren #define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16) 205ef280d39SStephen Warren 206896637acSStephen Warren /* Fields in TEGRA20_SPDIF_STROBE_CTRL */ 207ef280d39SStephen Warren 208ef280d39SStephen Warren /* 209ef280d39SStephen Warren * Indicates the approximate number of detected SPDIFIN clocks within a 210ef280d39SStephen Warren * bi-phase period. 211ef280d39SStephen Warren */ 212896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16 213896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT) 214ef280d39SStephen Warren 215ef280d39SStephen Warren /* Data strobe mode: 0=Auto-locked 1=Manual locked */ 216896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15) 217ef280d39SStephen Warren 218ef280d39SStephen Warren /* 219ef280d39SStephen Warren * Manual data strobe time within the bi-phase clock period (in terms of 220ef280d39SStephen Warren * the number of over-sampling clocks). 221ef280d39SStephen Warren */ 222896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8 223896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT) 224ef280d39SStephen Warren 225ef280d39SStephen Warren /* 226ef280d39SStephen Warren * Manual SPDIFIN bi-phase clock period (in terms of the number of 227ef280d39SStephen Warren * over-sampling clocks). 228ef280d39SStephen Warren */ 229896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0 230896637acSStephen Warren #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT) 231ef280d39SStephen Warren 232ef280d39SStephen Warren /* Fields in SPDIF_DATA_FIFO_CSR */ 233ef280d39SStephen Warren 234ef280d39SStephen Warren /* Clear Receiver User FIFO (RX USR.FIFO) */ 235896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31) 236ef280d39SStephen Warren 237896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0 238896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1 239896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2 240896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3 241ef280d39SStephen Warren 242ef280d39SStephen Warren /* RU FIFO attention level */ 243896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29 244896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \ 245896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 246896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \ 247896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 248896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \ 249896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 250896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \ 251896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 252896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \ 253896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 254ef280d39SStephen Warren 255ef280d39SStephen Warren /* Number of RX USR.FIFO levels with valid data. */ 256896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24 257896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT) 258ef280d39SStephen Warren 259ef280d39SStephen Warren /* Clear Transmitter User FIFO (TX USR.FIFO) */ 260896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23) 261ef280d39SStephen Warren 262ef280d39SStephen Warren /* TU FIFO attention level */ 263896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21 264896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \ 265896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 266896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \ 267896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 268896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \ 269896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 270896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \ 271896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 272896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \ 273896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 274ef280d39SStephen Warren 275ef280d39SStephen Warren /* Number of TX USR.FIFO levels that could be filled. */ 276896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16 277896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT) 278ef280d39SStephen Warren 279ef280d39SStephen Warren /* Clear Receiver Data FIFO (RX DATA.FIFO) */ 280896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15) 281ef280d39SStephen Warren 282896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0 283896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1 284896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2 285896637acSStephen Warren #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3 286ef280d39SStephen Warren 287ef280d39SStephen Warren /* RU FIFO attention level */ 288896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13 289896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \ 290896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 291896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \ 292896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 293896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \ 294896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 295896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \ 296896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 297896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \ 298896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 299ef280d39SStephen Warren 300ef280d39SStephen Warren /* Number of RX DATA.FIFO levels with valid data. */ 301896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8 302896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT) 303ef280d39SStephen Warren 304ef280d39SStephen Warren /* Clear Transmitter Data FIFO (TX DATA.FIFO) */ 305896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7) 306ef280d39SStephen Warren 307ef280d39SStephen Warren /* TU FIFO attention level */ 308896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5 309896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \ 310896637acSStephen Warren (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 311896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \ 312896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 313896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \ 314896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 315896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \ 316896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 317896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \ 318896637acSStephen Warren (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 319ef280d39SStephen Warren 320ef280d39SStephen Warren /* Number of TX DATA.FIFO levels that could be filled. */ 321896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0 322896637acSStephen Warren #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT) 323ef280d39SStephen Warren 324896637acSStephen Warren /* Fields in TEGRA20_SPDIF_DATA_OUT */ 325ef280d39SStephen Warren 326ef280d39SStephen Warren /* 327ef280d39SStephen Warren * This register has 5 different formats: 328ef280d39SStephen Warren * 16-bit (BIT_MODE=00, PACK=0) 329ef280d39SStephen Warren * 20-bit (BIT_MODE=01, PACK=0) 330ef280d39SStephen Warren * 24-bit (BIT_MODE=10, PACK=0) 331ef280d39SStephen Warren * raw (BIT_MODE=11, PACK=0) 332ef280d39SStephen Warren * 16-bit packed (BIT_MODE=00, PACK=1) 333ef280d39SStephen Warren */ 334ef280d39SStephen Warren 335896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0 336896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT) 337ef280d39SStephen Warren 338896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0 339896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT) 340ef280d39SStephen Warren 341896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0 342896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT) 343ef280d39SStephen Warren 344896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31) 345896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30) 346896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29) 347896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28) 348ef280d39SStephen Warren 349896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8 350896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT) 351ef280d39SStephen Warren 352896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4 353896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT) 354ef280d39SStephen Warren 355896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0 356896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT) 357ef280d39SStephen Warren 358896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16 359896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT) 360ef280d39SStephen Warren 361896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0 362896637acSStephen Warren #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT) 363ef280d39SStephen Warren 364896637acSStephen Warren /* Fields in TEGRA20_SPDIF_DATA_IN */ 365ef280d39SStephen Warren 366ef280d39SStephen Warren /* 367ef280d39SStephen Warren * This register has 5 different formats: 368ef280d39SStephen Warren * 16-bit (BIT_MODE=00, PACK=0) 369ef280d39SStephen Warren * 20-bit (BIT_MODE=01, PACK=0) 370ef280d39SStephen Warren * 24-bit (BIT_MODE=10, PACK=0) 371ef280d39SStephen Warren * raw (BIT_MODE=11, PACK=0) 372ef280d39SStephen Warren * 16-bit packed (BIT_MODE=00, PACK=1) 373ef280d39SStephen Warren * 374ef280d39SStephen Warren * Bits 31:24 are common to all modes except 16-bit packed 375ef280d39SStephen Warren */ 376ef280d39SStephen Warren 377896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31) 378896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30) 379896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29) 380896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28) 381ef280d39SStephen Warren 382896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24 383896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT) 384ef280d39SStephen Warren 385896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0 386896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT) 387ef280d39SStephen Warren 388896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0 389896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT) 390ef280d39SStephen Warren 391896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0 392896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT) 393ef280d39SStephen Warren 394896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8 395896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT) 396ef280d39SStephen Warren 397896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4 398896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT) 399ef280d39SStephen Warren 400896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0 401896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT) 402ef280d39SStephen Warren 403896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16 404896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT) 405ef280d39SStephen Warren 406896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0 407896637acSStephen Warren #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT) 408ef280d39SStephen Warren 409896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_A */ 410896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_B */ 411896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_C */ 412896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_D */ 413896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_E */ 414896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_RX_F */ 415ef280d39SStephen Warren 416ef280d39SStephen Warren /* 417ef280d39SStephen Warren * The 6-word receive channel data page buffer holds a block (192 frames) of 418ef280d39SStephen Warren * channel status information. The order of receive is from LSB to MSB 419ef280d39SStephen Warren * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A. 420ef280d39SStephen Warren */ 421ef280d39SStephen Warren 422896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_A */ 423896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_B */ 424896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_C */ 425896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_D */ 426896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_E */ 427896637acSStephen Warren /* Fields in TEGRA20_SPDIF_CH_STA_TX_F */ 428ef280d39SStephen Warren 429ef280d39SStephen Warren /* 430ef280d39SStephen Warren * The 6-word transmit channel data page buffer holds a block (192 frames) of 431ef280d39SStephen Warren * channel status information. The order of transmission is from LSB to MSB 432ef280d39SStephen Warren * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A. 433ef280d39SStephen Warren */ 434ef280d39SStephen Warren 435896637acSStephen Warren /* Fields in TEGRA20_SPDIF_USR_STA_RX_A */ 436ef280d39SStephen Warren 437ef280d39SStephen Warren /* 438ef280d39SStephen Warren * This 4-word deep FIFO receives user FIFO field information. The order of 439ef280d39SStephen Warren * receive is from LSB to MSB bit. 440ef280d39SStephen Warren */ 441ef280d39SStephen Warren 442896637acSStephen Warren /* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */ 443ef280d39SStephen Warren 444ef280d39SStephen Warren /* 445ef280d39SStephen Warren * This 4-word deep FIFO transmits user FIFO field information. The order of 446ef280d39SStephen Warren * transmission is from LSB to MSB bit. 447ef280d39SStephen Warren */ 448ef280d39SStephen Warren 449896637acSStephen Warren struct tegra20_spdif { 450ef280d39SStephen Warren struct clk *clk_spdif_out; 4513489d506SLars-Peter Clausen struct snd_dmaengine_dai_dma_data capture_dma_data; 4523489d506SLars-Peter Clausen struct snd_dmaengine_dai_dma_data playback_dma_data; 4535939ae74SStephen Warren struct regmap *regmap; 454*ec1b4545SDmitry Osipenko struct reset_control *reset; 455ef280d39SStephen Warren }; 456ef280d39SStephen Warren 457ef280d39SStephen Warren #endif 458