1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tegra20_ac97.c - Tegra20 AC97 platform driver 4 * 5 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de> 6 * 7 * Partly based on code copyright/by: 8 * 9 * Copyright (c) 2011,2012 Toradex Inc. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio.h> 16 #include <linux/io.h> 17 #include <linux/jiffies.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/slab.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/dmaengine_pcm.h> 31 32 #include "tegra20_ac97.h" 33 34 #define DRV_NAME "tegra20-ac97" 35 36 static struct tegra20_ac97 *workdata; 37 38 static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97) 39 { 40 u32 readback; 41 unsigned long timeout; 42 43 /* reset line is not driven by DAC pad group, have to toggle GPIO */ 44 gpio_set_value(workdata->reset_gpio, 0); 45 udelay(2); 46 47 gpio_set_value(workdata->reset_gpio, 1); 48 udelay(2); 49 50 timeout = jiffies + msecs_to_jiffies(100); 51 52 do { 53 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); 54 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY) 55 break; 56 usleep_range(1000, 2000); 57 } while (!time_after(jiffies, timeout)); 58 } 59 60 static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97) 61 { 62 u32 readback; 63 unsigned long timeout; 64 65 /* 66 * although sync line is driven by the DAC pad group warm reset using 67 * the controller cmd is not working, have to toggle sync line 68 * manually. 69 */ 70 gpio_request(workdata->sync_gpio, "codec-sync"); 71 72 gpio_direction_output(workdata->sync_gpio, 1); 73 74 udelay(2); 75 gpio_set_value(workdata->sync_gpio, 0); 76 udelay(2); 77 gpio_free(workdata->sync_gpio); 78 79 timeout = jiffies + msecs_to_jiffies(100); 80 81 do { 82 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); 83 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY) 84 break; 85 usleep_range(1000, 2000); 86 } while (!time_after(jiffies, timeout)); 87 } 88 89 static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd, 90 unsigned short reg) 91 { 92 u32 readback; 93 unsigned long timeout; 94 95 regmap_write(workdata->regmap, TEGRA20_AC97_CMD, 96 (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) & 97 TEGRA20_AC97_CMD_CMD_ADDR_MASK) | 98 TEGRA20_AC97_CMD_BUSY); 99 100 timeout = jiffies + msecs_to_jiffies(100); 101 102 do { 103 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); 104 if (readback & TEGRA20_AC97_STATUS1_STA_VALID1) 105 break; 106 usleep_range(1000, 2000); 107 } while (!time_after(jiffies, timeout)); 108 109 return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >> 110 TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT); 111 } 112 113 static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd, 114 unsigned short reg, unsigned short val) 115 { 116 u32 readback; 117 unsigned long timeout; 118 119 regmap_write(workdata->regmap, TEGRA20_AC97_CMD, 120 ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) & 121 TEGRA20_AC97_CMD_CMD_ADDR_MASK) | 122 ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) & 123 TEGRA20_AC97_CMD_CMD_DATA_MASK) | 124 TEGRA20_AC97_CMD_BUSY); 125 126 timeout = jiffies + msecs_to_jiffies(100); 127 128 do { 129 regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback); 130 if (!(readback & TEGRA20_AC97_CMD_BUSY)) 131 break; 132 usleep_range(1000, 2000); 133 } while (!time_after(jiffies, timeout)); 134 } 135 136 static struct snd_ac97_bus_ops tegra20_ac97_ops = { 137 .read = tegra20_ac97_codec_read, 138 .write = tegra20_ac97_codec_write, 139 .reset = tegra20_ac97_codec_reset, 140 .warm_reset = tegra20_ac97_codec_warm_reset, 141 }; 142 143 static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97) 144 { 145 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, 146 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 147 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN); 148 149 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL, 150 TEGRA20_AC97_CTRL_PCM_DAC_EN | 151 TEGRA20_AC97_CTRL_STM_EN, 152 TEGRA20_AC97_CTRL_PCM_DAC_EN | 153 TEGRA20_AC97_CTRL_STM_EN); 154 } 155 156 static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97) 157 { 158 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, 159 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0); 160 161 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL, 162 TEGRA20_AC97_CTRL_PCM_DAC_EN, 0); 163 } 164 165 static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97) 166 { 167 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, 168 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 169 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN); 170 } 171 172 static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97) 173 { 174 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, 175 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0); 176 } 177 178 static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd, 179 struct snd_soc_dai *dai) 180 { 181 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai); 182 183 switch (cmd) { 184 case SNDRV_PCM_TRIGGER_START: 185 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 186 case SNDRV_PCM_TRIGGER_RESUME: 187 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 188 tegra20_ac97_start_playback(ac97); 189 else 190 tegra20_ac97_start_capture(ac97); 191 break; 192 case SNDRV_PCM_TRIGGER_STOP: 193 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 194 case SNDRV_PCM_TRIGGER_SUSPEND: 195 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 196 tegra20_ac97_stop_playback(ac97); 197 else 198 tegra20_ac97_stop_capture(ac97); 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 return 0; 205 } 206 207 static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = { 208 .trigger = tegra20_ac97_trigger, 209 }; 210 211 static int tegra20_ac97_probe(struct snd_soc_dai *dai) 212 { 213 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai); 214 215 dai->capture_dma_data = &ac97->capture_dma_data; 216 dai->playback_dma_data = &ac97->playback_dma_data; 217 218 return 0; 219 } 220 221 static struct snd_soc_dai_driver tegra20_ac97_dai = { 222 .name = "tegra-ac97-pcm", 223 .probe = tegra20_ac97_probe, 224 .playback = { 225 .stream_name = "PCM Playback", 226 .channels_min = 2, 227 .channels_max = 2, 228 .rates = SNDRV_PCM_RATE_8000_48000, 229 .formats = SNDRV_PCM_FMTBIT_S16_LE, 230 }, 231 .capture = { 232 .stream_name = "PCM Capture", 233 .channels_min = 2, 234 .channels_max = 2, 235 .rates = SNDRV_PCM_RATE_8000_48000, 236 .formats = SNDRV_PCM_FMTBIT_S16_LE, 237 }, 238 .ops = &tegra20_ac97_dai_ops, 239 }; 240 241 static const struct snd_soc_component_driver tegra20_ac97_component = { 242 .name = DRV_NAME, 243 .legacy_dai_naming = 1, 244 }; 245 246 static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg) 247 { 248 switch (reg) { 249 case TEGRA20_AC97_CTRL: 250 case TEGRA20_AC97_CMD: 251 case TEGRA20_AC97_STATUS1: 252 case TEGRA20_AC97_FIFO1_SCR: 253 case TEGRA20_AC97_FIFO_TX1: 254 case TEGRA20_AC97_FIFO_RX1: 255 return true; 256 default: 257 break; 258 } 259 260 return false; 261 } 262 263 static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg) 264 { 265 switch (reg) { 266 case TEGRA20_AC97_STATUS1: 267 case TEGRA20_AC97_FIFO1_SCR: 268 case TEGRA20_AC97_FIFO_TX1: 269 case TEGRA20_AC97_FIFO_RX1: 270 return true; 271 default: 272 break; 273 } 274 275 return false; 276 } 277 278 static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg) 279 { 280 switch (reg) { 281 case TEGRA20_AC97_FIFO_TX1: 282 case TEGRA20_AC97_FIFO_RX1: 283 return true; 284 default: 285 break; 286 } 287 288 return false; 289 } 290 291 static const struct regmap_config tegra20_ac97_regmap_config = { 292 .reg_bits = 32, 293 .reg_stride = 4, 294 .val_bits = 32, 295 .max_register = TEGRA20_AC97_FIFO_RX1, 296 .writeable_reg = tegra20_ac97_wr_rd_reg, 297 .readable_reg = tegra20_ac97_wr_rd_reg, 298 .volatile_reg = tegra20_ac97_volatile_reg, 299 .precious_reg = tegra20_ac97_precious_reg, 300 .cache_type = REGCACHE_FLAT, 301 }; 302 303 static int tegra20_ac97_platform_probe(struct platform_device *pdev) 304 { 305 struct tegra20_ac97 *ac97; 306 struct resource *mem; 307 void __iomem *regs; 308 int ret = 0; 309 310 ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97), 311 GFP_KERNEL); 312 if (!ac97) { 313 ret = -ENOMEM; 314 goto err; 315 } 316 dev_set_drvdata(&pdev->dev, ac97); 317 318 ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97"); 319 if (IS_ERR(ac97->reset)) { 320 dev_err(&pdev->dev, "Can't retrieve ac97 reset\n"); 321 return PTR_ERR(ac97->reset); 322 } 323 324 ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL); 325 if (IS_ERR(ac97->clk_ac97)) { 326 dev_err(&pdev->dev, "Can't retrieve ac97 clock\n"); 327 ret = PTR_ERR(ac97->clk_ac97); 328 goto err; 329 } 330 331 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 332 regs = devm_ioremap_resource(&pdev->dev, mem); 333 if (IS_ERR(regs)) { 334 ret = PTR_ERR(regs); 335 goto err_clk_put; 336 } 337 338 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 339 &tegra20_ac97_regmap_config); 340 if (IS_ERR(ac97->regmap)) { 341 dev_err(&pdev->dev, "regmap init failed\n"); 342 ret = PTR_ERR(ac97->regmap); 343 goto err_clk_put; 344 } 345 346 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node, 347 "nvidia,codec-reset-gpio", 0); 348 if (gpio_is_valid(ac97->reset_gpio)) { 349 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio, 350 GPIOF_OUT_INIT_HIGH, "codec-reset"); 351 if (ret) { 352 dev_err(&pdev->dev, "could not get codec-reset GPIO\n"); 353 goto err_clk_put; 354 } 355 } else { 356 dev_err(&pdev->dev, "no codec-reset GPIO supplied\n"); 357 ret = -EINVAL; 358 goto err_clk_put; 359 } 360 361 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node, 362 "nvidia,codec-sync-gpio", 0); 363 if (!gpio_is_valid(ac97->sync_gpio)) { 364 dev_err(&pdev->dev, "no codec-sync GPIO supplied\n"); 365 ret = -EINVAL; 366 goto err_clk_put; 367 } 368 369 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1; 370 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 371 ac97->capture_dma_data.maxburst = 4; 372 373 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1; 374 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 375 ac97->playback_dma_data.maxburst = 4; 376 377 ret = reset_control_assert(ac97->reset); 378 if (ret) { 379 dev_err(&pdev->dev, "Failed to assert AC'97 reset: %d\n", ret); 380 goto err_clk_put; 381 } 382 383 ret = clk_prepare_enable(ac97->clk_ac97); 384 if (ret) { 385 dev_err(&pdev->dev, "clk_enable failed: %d\n", ret); 386 goto err_clk_put; 387 } 388 389 usleep_range(10, 100); 390 391 ret = reset_control_deassert(ac97->reset); 392 if (ret) { 393 dev_err(&pdev->dev, "Failed to deassert AC'97 reset: %d\n", ret); 394 goto err_clk_disable_unprepare; 395 } 396 397 ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops); 398 if (ret) { 399 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret); 400 goto err_clk_disable_unprepare; 401 } 402 403 ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component, 404 &tegra20_ac97_dai, 1); 405 if (ret) { 406 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); 407 ret = -ENOMEM; 408 goto err_clk_disable_unprepare; 409 } 410 411 ret = tegra_pcm_platform_register(&pdev->dev); 412 if (ret) { 413 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); 414 goto err_unregister_component; 415 } 416 417 /* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */ 418 workdata = ac97; 419 420 return 0; 421 422 err_unregister_component: 423 snd_soc_unregister_component(&pdev->dev); 424 err_clk_disable_unprepare: 425 clk_disable_unprepare(ac97->clk_ac97); 426 err_clk_put: 427 err: 428 snd_soc_set_ac97_ops(NULL); 429 return ret; 430 } 431 432 static int tegra20_ac97_platform_remove(struct platform_device *pdev) 433 { 434 struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev); 435 436 tegra_pcm_platform_unregister(&pdev->dev); 437 snd_soc_unregister_component(&pdev->dev); 438 439 clk_disable_unprepare(ac97->clk_ac97); 440 441 snd_soc_set_ac97_ops(NULL); 442 443 return 0; 444 } 445 446 static const struct of_device_id tegra20_ac97_of_match[] = { 447 { .compatible = "nvidia,tegra20-ac97", }, 448 {}, 449 }; 450 451 static struct platform_driver tegra20_ac97_driver = { 452 .driver = { 453 .name = DRV_NAME, 454 .of_match_table = tegra20_ac97_of_match, 455 }, 456 .probe = tegra20_ac97_platform_probe, 457 .remove = tegra20_ac97_platform_remove, 458 }; 459 module_platform_driver(tegra20_ac97_driver); 460 461 MODULE_AUTHOR("Lucas Stach"); 462 MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver"); 463 MODULE_LICENSE("GPL v2"); 464 MODULE_ALIAS("platform:" DRV_NAME); 465 MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match); 466