1327ef647SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2327ef647SSameer Pujar /* 3327ef647SSameer Pujar * tegra186_dspk.h - Definitions for Tegra186 DSPK driver 4327ef647SSameer Pujar * 5327ef647SSameer Pujar * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6327ef647SSameer Pujar * 7327ef647SSameer Pujar */ 8327ef647SSameer Pujar 9327ef647SSameer Pujar #ifndef __TEGRA186_DSPK_H__ 10327ef647SSameer Pujar #define __TEGRA186_DSPK_H__ 11327ef647SSameer Pujar 12327ef647SSameer Pujar /* Register offsets from DSPK BASE */ 13327ef647SSameer Pujar #define TEGRA186_DSPK_RX_STATUS 0x0c 14327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_STATUS 0x10 15327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_MASK 0x14 16327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_SET 0x18 17327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_CLEAR 0x1c 18327ef647SSameer Pujar #define TEGRA186_DSPK_RX_CIF_CTRL 0x20 19327ef647SSameer Pujar #define TEGRA186_DSPK_ENABLE 0x40 20327ef647SSameer Pujar #define TEGRA186_DSPK_SOFT_RESET 0x44 21327ef647SSameer Pujar #define TEGRA186_DSPK_CG 0x48 22327ef647SSameer Pujar #define TEGRA186_DSPK_STATUS 0x4c 23327ef647SSameer Pujar #define TEGRA186_DSPK_INT_STATUS 0x50 24327ef647SSameer Pujar #define TEGRA186_DSPK_CORE_CTRL 0x60 25327ef647SSameer Pujar #define TEGRA186_DSPK_CODEC_CTRL 0x64 26327ef647SSameer Pujar 27327ef647SSameer Pujar /* DSPK CORE CONTROL fields */ 28327ef647SSameer Pujar #define CH_SEL_SHIFT 8 29327ef647SSameer Pujar #define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT) 30327ef647SSameer Pujar #define DSPK_OSR_SHIFT 4 31327ef647SSameer Pujar #define TEGRA186_DSPK_OSR_MASK (0x3 << DSPK_OSR_SHIFT) 32327ef647SSameer Pujar #define LRSEL_POL_SHIFT 0 33327ef647SSameer Pujar #define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT) 34327ef647SSameer Pujar #define TEGRA186_DSPK_RX_FIFO_DEPTH 64 35327ef647SSameer Pujar 36327ef647SSameer Pujar #define DSPK_OSR_FACTOR 32 37327ef647SSameer Pujar 38327ef647SSameer Pujar /* DSPK interface clock ratio */ 39327ef647SSameer Pujar #define DSPK_CLK_RATIO 4 40327ef647SSameer Pujar 41327ef647SSameer Pujar enum tegra_dspk_osr { 42327ef647SSameer Pujar DSPK_OSR_32, 43327ef647SSameer Pujar DSPK_OSR_64, 44327ef647SSameer Pujar DSPK_OSR_128, 45327ef647SSameer Pujar DSPK_OSR_256, 46327ef647SSameer Pujar }; 47327ef647SSameer Pujar 48327ef647SSameer Pujar enum tegra_dspk_ch_sel { 49327ef647SSameer Pujar DSPK_CH_SELECT_LEFT, 50327ef647SSameer Pujar DSPK_CH_SELECT_RIGHT, 51327ef647SSameer Pujar DSPK_CH_SELECT_STEREO, 52327ef647SSameer Pujar }; 53327ef647SSameer Pujar 54327ef647SSameer Pujar enum tegra_dspk_lrsel { 55327ef647SSameer Pujar DSPK_LRSEL_LEFT, 56327ef647SSameer Pujar DSPK_LRSEL_RIGHT, 57327ef647SSameer Pujar }; 58327ef647SSameer Pujar 59327ef647SSameer Pujar struct tegra186_dspk { 60327ef647SSameer Pujar unsigned int rx_fifo_th; 61327ef647SSameer Pujar unsigned int osr_val; 62327ef647SSameer Pujar unsigned int lrsel; 63327ef647SSameer Pujar unsigned int ch_sel; 64327ef647SSameer Pujar unsigned int mono_to_stereo; 65327ef647SSameer Pujar unsigned int stereo_to_mono; 66327ef647SSameer Pujar struct clk *clk_dspk; 67327ef647SSameer Pujar struct regmap *regmap; 68327ef647SSameer Pujar }; 69327ef647SSameer Pujar 70327ef647SSameer Pujar #endif 71