1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA SoC SPDIF Audio Layer 4 * 5 * Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it> 6 * Copyright 2015 Marcus Cooper <codekipper@gmail.com> 7 * 8 * Based on the Allwinner SDK driver, released under the GPL. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/regmap.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/ioport.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/reset.h> 24 #include <sound/dmaengine_pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 28 #define SUN4I_SPDIF_CTL (0x00) 29 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */ 30 #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2) 31 #define SUN4I_SPDIF_CTL_GEN BIT(1) 32 #define SUN4I_SPDIF_CTL_RESET BIT(0) 33 34 #define SUN4I_SPDIF_TXCFG (0x04) 35 #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31) 36 #define SUN4I_SPDIF_TXCFG_ASS BIT(17) 37 #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16) 38 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4) 39 #define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4) 40 #define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2) 41 #define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2) 42 #define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2) 43 #define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2) 44 #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1) 45 #define SUN4I_SPDIF_TXCFG_TXEN BIT(0) 46 47 #define SUN4I_SPDIF_RXCFG (0x08) 48 #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4) 49 #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3) 50 #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1) 51 #define SUN4I_SPDIF_RXCFG_RXEN BIT(0) 52 53 #define SUN4I_SPDIF_TXFIFO (0x0C) 54 55 #define SUN4I_SPDIF_RXFIFO (0x10) 56 57 #define SUN4I_SPDIF_FCTL (0x14) 58 #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31) 59 #define SUN4I_SPDIF_FCTL_FTX BIT(17) 60 #define SUN4I_SPDIF_FCTL_FRX BIT(16) 61 #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8) 62 #define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8) 63 #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3) 64 #define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3) 65 #define SUN4I_SPDIF_FCTL_TXIM BIT(2) 66 #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0) 67 #define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0) 68 69 #define SUN4I_SPDIF_FSTA (0x18) 70 #define SUN4I_SPDIF_FSTA_TXE BIT(14) 71 #define SUN4I_SPDIF_FSTA_TXECNTSHT (8) 72 #define SUN4I_SPDIF_FSTA_RXA BIT(6) 73 #define SUN4I_SPDIF_FSTA_RXACNTSHT (0) 74 75 #define SUN4I_SPDIF_INT (0x1C) 76 #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18) 77 #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17) 78 #define SUN4I_SPDIF_INT_RXPARERREN BIT(16) 79 #define SUN4I_SPDIF_INT_TXDRQEN BIT(7) 80 #define SUN4I_SPDIF_INT_TXUIEN BIT(6) 81 #define SUN4I_SPDIF_INT_TXOIEN BIT(5) 82 #define SUN4I_SPDIF_INT_TXEIEN BIT(4) 83 #define SUN4I_SPDIF_INT_RXDRQEN BIT(2) 84 #define SUN4I_SPDIF_INT_RXOIEN BIT(1) 85 #define SUN4I_SPDIF_INT_RXAIEN BIT(0) 86 87 #define SUN4I_SPDIF_ISTA (0x20) 88 #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18) 89 #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17) 90 #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16) 91 #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6) 92 #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5) 93 #define SUN4I_SPDIF_ISTA_TXESTA BIT(4) 94 #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1) 95 #define SUN4I_SPDIF_ISTA_RXASTA BIT(0) 96 97 #define SUN8I_SPDIF_TXFIFO (0x20) 98 99 #define SUN4I_SPDIF_TXCNT (0x24) 100 101 #define SUN4I_SPDIF_RXCNT (0x28) 102 103 #define SUN4I_SPDIF_TXCHSTA0 (0x2C) 104 #define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28) 105 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24) 106 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24) 107 #define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20) 108 #define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20) 109 #define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16) 110 #define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8) 111 #define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6) 112 #define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3) 113 #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2) 114 #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1) 115 #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0) 116 117 #define SUN4I_SPDIF_TXCHSTA1 (0x30) 118 #define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8) 119 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4) 120 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4) 121 #define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1) 122 #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0) 123 124 #define SUN4I_SPDIF_RXCHSTA0 (0x34) 125 #define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28) 126 #define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24) 127 #define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20) 128 #define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16) 129 #define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8) 130 #define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6) 131 #define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3) 132 #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2) 133 #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1) 134 #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0) 135 136 #define SUN4I_SPDIF_RXCHSTA1 (0x38) 137 #define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8) 138 #define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4) 139 #define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1) 140 #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0) 141 142 /* Defines for Sampling Frequency */ 143 #define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0 144 #define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1 145 #define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2 146 #define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3 147 #define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4 148 #define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6 149 #define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8 150 #define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9 151 #define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa 152 #define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc 153 #define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe 154 155 struct sun4i_spdif_dev { 156 struct platform_device *pdev; 157 struct clk *spdif_clk; 158 struct clk *apb_clk; 159 struct reset_control *rst; 160 struct snd_soc_dai_driver cpu_dai_drv; 161 struct regmap *regmap; 162 struct snd_dmaengine_dai_dma_data dma_params_tx; 163 }; 164 165 static void sun4i_spdif_configure(struct sun4i_spdif_dev *host) 166 { 167 /* soft reset SPDIF */ 168 regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET); 169 170 /* flush TX FIFO */ 171 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL, 172 SUN4I_SPDIF_FCTL_FTX, SUN4I_SPDIF_FCTL_FTX); 173 174 /* clear TX counter */ 175 regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0); 176 } 177 178 static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream, 179 struct sun4i_spdif_dev *host) 180 { 181 if (substream->runtime->channels == 1) 182 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG, 183 SUN4I_SPDIF_TXCFG_SINGLEMOD, 184 SUN4I_SPDIF_TXCFG_SINGLEMOD); 185 186 /* SPDIF TX ENABLE */ 187 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG, 188 SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN); 189 190 /* DRQ ENABLE */ 191 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT, 192 SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN); 193 194 /* Global enable */ 195 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL, 196 SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN); 197 } 198 199 static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream, 200 struct sun4i_spdif_dev *host) 201 { 202 /* SPDIF TX DISABLE */ 203 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG, 204 SUN4I_SPDIF_TXCFG_TXEN, 0); 205 206 /* DRQ DISABLE */ 207 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT, 208 SUN4I_SPDIF_INT_TXDRQEN, 0); 209 210 /* Global disable */ 211 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL, 212 SUN4I_SPDIF_CTL_GEN, 0); 213 } 214 215 static int sun4i_spdif_startup(struct snd_pcm_substream *substream, 216 struct snd_soc_dai *cpu_dai) 217 { 218 struct snd_soc_pcm_runtime *rtd = substream->private_data; 219 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(rtd->cpu_dai); 220 221 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 222 return -EINVAL; 223 224 sun4i_spdif_configure(host); 225 226 return 0; 227 } 228 229 static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, 230 struct snd_pcm_hw_params *params, 231 struct snd_soc_dai *cpu_dai) 232 { 233 int ret = 0; 234 int fmt; 235 unsigned long rate = params_rate(params); 236 u32 mclk_div = 0; 237 unsigned int mclk = 0; 238 u32 reg_val; 239 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai); 240 struct platform_device *pdev = host->pdev; 241 242 /* Add the PCM and raw data select interface */ 243 switch (params_channels(params)) { 244 case 1: /* PCM mode */ 245 case 2: 246 fmt = 0; 247 break; 248 case 4: /* raw data mode */ 249 fmt = SUN4I_SPDIF_TXCFG_NONAUDIO; 250 break; 251 default: 252 return -EINVAL; 253 } 254 255 switch (params_format(params)) { 256 case SNDRV_PCM_FORMAT_S16_LE: 257 fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT; 258 break; 259 case SNDRV_PCM_FORMAT_S20_3LE: 260 fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT; 261 break; 262 case SNDRV_PCM_FORMAT_S24_LE: 263 fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT; 264 break; 265 default: 266 return -EINVAL; 267 } 268 269 switch (rate) { 270 case 22050: 271 case 44100: 272 case 88200: 273 case 176400: 274 mclk = 22579200; 275 break; 276 case 24000: 277 case 32000: 278 case 48000: 279 case 96000: 280 case 192000: 281 mclk = 24576000; 282 break; 283 default: 284 return -EINVAL; 285 } 286 287 ret = clk_set_rate(host->spdif_clk, mclk); 288 if (ret < 0) { 289 dev_err(&pdev->dev, 290 "Setting SPDIF clock rate for %d Hz failed!\n", mclk); 291 return ret; 292 } 293 294 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL, 295 SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM); 296 297 switch (rate) { 298 case 22050: 299 case 24000: 300 mclk_div = 8; 301 break; 302 case 32000: 303 mclk_div = 6; 304 break; 305 case 44100: 306 case 48000: 307 mclk_div = 4; 308 break; 309 case 88200: 310 case 96000: 311 mclk_div = 2; 312 break; 313 case 176400: 314 case 192000: 315 mclk_div = 1; 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 reg_val = 0; 322 reg_val |= SUN4I_SPDIF_TXCFG_ASS; 323 reg_val |= fmt; /* set non audio and bit depth */ 324 reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE; 325 reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1); 326 regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val); 327 328 return 0; 329 } 330 331 static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd, 332 struct snd_soc_dai *dai) 333 { 334 int ret = 0; 335 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai); 336 337 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 338 return -EINVAL; 339 340 switch (cmd) { 341 case SNDRV_PCM_TRIGGER_START: 342 case SNDRV_PCM_TRIGGER_RESUME: 343 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 344 sun4i_snd_txctrl_on(substream, host); 345 break; 346 347 case SNDRV_PCM_TRIGGER_STOP: 348 case SNDRV_PCM_TRIGGER_SUSPEND: 349 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 350 sun4i_snd_txctrl_off(substream, host); 351 break; 352 353 default: 354 ret = -EINVAL; 355 break; 356 } 357 return ret; 358 } 359 360 static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai) 361 { 362 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai); 363 364 snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL); 365 return 0; 366 } 367 368 static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = { 369 .startup = sun4i_spdif_startup, 370 .trigger = sun4i_spdif_trigger, 371 .hw_params = sun4i_spdif_hw_params, 372 }; 373 374 static const struct regmap_config sun4i_spdif_regmap_config = { 375 .reg_bits = 32, 376 .reg_stride = 4, 377 .val_bits = 32, 378 .max_register = SUN4I_SPDIF_RXCHSTA1, 379 }; 380 381 #define SUN4I_RATES SNDRV_PCM_RATE_8000_192000 382 383 #define SUN4I_FORMATS (SNDRV_PCM_FORMAT_S16_LE | \ 384 SNDRV_PCM_FORMAT_S20_3LE | \ 385 SNDRV_PCM_FORMAT_S24_LE) 386 387 static struct snd_soc_dai_driver sun4i_spdif_dai = { 388 .playback = { 389 .channels_min = 1, 390 .channels_max = 2, 391 .rates = SUN4I_RATES, 392 .formats = SUN4I_FORMATS, 393 }, 394 .probe = sun4i_spdif_soc_dai_probe, 395 .ops = &sun4i_spdif_dai_ops, 396 .name = "spdif", 397 }; 398 399 struct sun4i_spdif_quirks { 400 unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ 401 bool has_reset; 402 }; 403 404 static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = { 405 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO, 406 }; 407 408 static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = { 409 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO, 410 .has_reset = true, 411 }; 412 413 static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = { 414 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO, 415 .has_reset = true, 416 }; 417 418 static const struct of_device_id sun4i_spdif_of_match[] = { 419 { 420 .compatible = "allwinner,sun4i-a10-spdif", 421 .data = &sun4i_a10_spdif_quirks, 422 }, 423 { 424 .compatible = "allwinner,sun6i-a31-spdif", 425 .data = &sun6i_a31_spdif_quirks, 426 }, 427 { 428 .compatible = "allwinner,sun8i-h3-spdif", 429 .data = &sun8i_h3_spdif_quirks, 430 }, 431 { /* sentinel */ } 432 }; 433 MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match); 434 435 static const struct snd_soc_component_driver sun4i_spdif_component = { 436 .name = "sun4i-spdif", 437 }; 438 439 static int sun4i_spdif_runtime_suspend(struct device *dev) 440 { 441 struct sun4i_spdif_dev *host = dev_get_drvdata(dev); 442 443 clk_disable_unprepare(host->spdif_clk); 444 clk_disable_unprepare(host->apb_clk); 445 446 return 0; 447 } 448 449 static int sun4i_spdif_runtime_resume(struct device *dev) 450 { 451 struct sun4i_spdif_dev *host = dev_get_drvdata(dev); 452 int ret; 453 454 ret = clk_prepare_enable(host->spdif_clk); 455 if (ret) 456 return ret; 457 ret = clk_prepare_enable(host->apb_clk); 458 if (ret) 459 clk_disable_unprepare(host->spdif_clk); 460 461 return ret; 462 } 463 464 static int sun4i_spdif_probe(struct platform_device *pdev) 465 { 466 struct sun4i_spdif_dev *host; 467 struct resource *res; 468 const struct sun4i_spdif_quirks *quirks; 469 int ret; 470 void __iomem *base; 471 472 dev_dbg(&pdev->dev, "Entered %s\n", __func__); 473 474 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 475 if (!host) 476 return -ENOMEM; 477 478 host->pdev = pdev; 479 480 /* Initialize this copy of the CPU DAI driver structure */ 481 memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai)); 482 host->cpu_dai_drv.name = dev_name(&pdev->dev); 483 484 /* Get the addresses */ 485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 486 base = devm_ioremap_resource(&pdev->dev, res); 487 if (IS_ERR(base)) 488 return PTR_ERR(base); 489 490 quirks = of_device_get_match_data(&pdev->dev); 491 if (quirks == NULL) { 492 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 493 return -ENODEV; 494 } 495 496 host->regmap = devm_regmap_init_mmio(&pdev->dev, base, 497 &sun4i_spdif_regmap_config); 498 499 /* Clocks */ 500 host->apb_clk = devm_clk_get(&pdev->dev, "apb"); 501 if (IS_ERR(host->apb_clk)) { 502 dev_err(&pdev->dev, "failed to get a apb clock.\n"); 503 return PTR_ERR(host->apb_clk); 504 } 505 506 host->spdif_clk = devm_clk_get(&pdev->dev, "spdif"); 507 if (IS_ERR(host->spdif_clk)) { 508 dev_err(&pdev->dev, "failed to get a spdif clock.\n"); 509 return PTR_ERR(host->spdif_clk); 510 } 511 512 host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata; 513 host->dma_params_tx.maxburst = 8; 514 host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 515 516 platform_set_drvdata(pdev, host); 517 518 if (quirks->has_reset) { 519 host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 520 NULL); 521 if (IS_ERR(host->rst) && PTR_ERR(host->rst) == -EPROBE_DEFER) { 522 ret = -EPROBE_DEFER; 523 dev_err(&pdev->dev, "Failed to get reset: %d\n", ret); 524 return ret; 525 } 526 if (!IS_ERR(host->rst)) 527 reset_control_deassert(host->rst); 528 } 529 530 ret = devm_snd_soc_register_component(&pdev->dev, 531 &sun4i_spdif_component, &sun4i_spdif_dai, 1); 532 if (ret) 533 return ret; 534 535 pm_runtime_enable(&pdev->dev); 536 if (!pm_runtime_enabled(&pdev->dev)) { 537 ret = sun4i_spdif_runtime_resume(&pdev->dev); 538 if (ret) 539 goto err_unregister; 540 } 541 542 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 543 if (ret) 544 goto err_suspend; 545 return 0; 546 err_suspend: 547 if (!pm_runtime_status_suspended(&pdev->dev)) 548 sun4i_spdif_runtime_suspend(&pdev->dev); 549 err_unregister: 550 pm_runtime_disable(&pdev->dev); 551 return ret; 552 } 553 554 static int sun4i_spdif_remove(struct platform_device *pdev) 555 { 556 pm_runtime_disable(&pdev->dev); 557 if (!pm_runtime_status_suspended(&pdev->dev)) 558 sun4i_spdif_runtime_suspend(&pdev->dev); 559 560 return 0; 561 } 562 563 static const struct dev_pm_ops sun4i_spdif_pm = { 564 SET_RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend, 565 sun4i_spdif_runtime_resume, NULL) 566 }; 567 568 static struct platform_driver sun4i_spdif_driver = { 569 .driver = { 570 .name = "sun4i-spdif", 571 .of_match_table = of_match_ptr(sun4i_spdif_of_match), 572 .pm = &sun4i_spdif_pm, 573 }, 574 .probe = sun4i_spdif_probe, 575 .remove = sun4i_spdif_remove, 576 }; 577 578 module_platform_driver(sun4i_spdif_driver); 579 580 MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>"); 581 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>"); 582 MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface"); 583 MODULE_LICENSE("GPL"); 584 MODULE_ALIAS("platform:sun4i-spdif"); 585