1 /* 2 * Copyright (C) 2015 Andrea Venturi 3 * Andrea Venturi <be17068@iperbole.bo.it> 4 * 5 * Copyright (C) 2016 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/dmaengine.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 23 #include <sound/dmaengine_pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dai.h> 27 28 #define SUN4I_I2S_CTRL_REG 0x00 29 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8) 30 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) 31 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5) 32 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5) 33 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5) 34 #define SUN4I_I2S_CTRL_TX_EN BIT(2) 35 #define SUN4I_I2S_CTRL_RX_EN BIT(1) 36 #define SUN4I_I2S_CTRL_GL_EN BIT(0) 37 38 #define SUN4I_I2S_FMT0_REG 0x04 39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7) 40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7) 41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7) 42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6) 43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6) 44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6) 45 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4) 46 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4) 47 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2) 48 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2) 49 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0) 50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) 51 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) 52 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) 53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED (1) 54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL (0) 55 56 #define SUN4I_I2S_FMT1_REG 0x08 57 #define SUN4I_I2S_FIFO_TX_REG 0x0c 58 #define SUN4I_I2S_FIFO_RX_REG 0x10 59 60 #define SUN4I_I2S_FIFO_CTRL_REG 0x14 61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25) 62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24) 63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2) 64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2) 65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0) 66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode) 67 68 #define SUN4I_I2S_FIFO_STA_REG 0x18 69 70 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c 71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7) 72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3) 73 74 #define SUN4I_I2S_INT_STA_REG 0x20 75 76 #define SUN4I_I2S_CLK_DIV_REG 0x24 77 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) 78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) 79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) 80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) 81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) 82 83 #define SUN4I_I2S_RX_CNT_REG 0x28 84 #define SUN4I_I2S_TX_CNT_REG 0x2c 85 86 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 87 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) 88 89 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) 91 92 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 93 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c 94 95 /* Defines required for sun8i-h3 support */ 96 #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) 97 #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) 98 99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) 101 102 #define SUN8I_I2S_INT_STA_REG 0x0c 103 #define SUN8I_I2S_FIFO_TX_REG 0x20 104 105 #define SUN8I_I2S_CHAN_CFG_REG 0x30 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) (chan - 1) 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) 110 111 #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 112 #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 11) 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) 115 #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) 117 118 #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 119 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 120 121 /** 122 * struct sun4i_i2s_quirks - Differences between SoC variants. 123 * 124 * @has_reset: SoC needs reset deasserted. 125 * @has_slave_select_bit: SoC has a bit to enable slave mode. 126 * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. 127 * @has_chcfg: tx and rx slot number need to be set. 128 * @has_chsel_tx_chen: SoC requires that the tx channels are enabled. 129 * @has_chsel_offset: SoC uses offset for selecting dai operational mode. 130 * @reg_offset_txdata: offset of the tx fifo. 131 * @sun4i_i2s_regmap: regmap config to use. 132 * @mclk_offset: Value by which mclkdiv needs to be adjusted. 133 * @bclk_offset: Value by which bclkdiv needs to be adjusted. 134 * @fmt_offset: Value by which wss and sr needs to be adjusted. 135 * @field_clkdiv_mclk_en: regmap field to enable mclk output. 136 * @field_fmt_wss: regmap field to set word select size. 137 * @field_fmt_sr: regmap field to set sample resolution. 138 * @field_fmt_bclk: regmap field to set clk polarity. 139 * @field_fmt_lrclk: regmap field to set frame polarity. 140 * @field_fmt_mode: regmap field to set the operational mode. 141 * @field_txchanmap: location of the tx channel mapping register. 142 * @field_rxchanmap: location of the rx channel mapping register. 143 * @field_txchansel: location of the tx channel select bit fields. 144 * @field_rxchansel: location of the rx channel select bit fields. 145 */ 146 struct sun4i_i2s_quirks { 147 bool has_reset; 148 bool has_slave_select_bit; 149 bool has_fmt_set_lrck_period; 150 bool has_chcfg; 151 bool has_chsel_tx_chen; 152 bool has_chsel_offset; 153 unsigned int reg_offset_txdata; /* TX FIFO */ 154 const struct regmap_config *sun4i_i2s_regmap; 155 unsigned int mclk_offset; 156 unsigned int bclk_offset; 157 unsigned int fmt_offset; 158 159 /* Register fields for i2s */ 160 struct reg_field field_clkdiv_mclk_en; 161 struct reg_field field_fmt_wss; 162 struct reg_field field_fmt_sr; 163 struct reg_field field_fmt_bclk; 164 struct reg_field field_fmt_lrclk; 165 struct reg_field field_fmt_mode; 166 struct reg_field field_txchanmap; 167 struct reg_field field_rxchanmap; 168 struct reg_field field_txchansel; 169 struct reg_field field_rxchansel; 170 }; 171 172 struct sun4i_i2s { 173 struct clk *bus_clk; 174 struct clk *mod_clk; 175 struct regmap *regmap; 176 struct reset_control *rst; 177 178 unsigned int mclk_freq; 179 180 struct snd_dmaengine_dai_dma_data capture_dma_data; 181 struct snd_dmaengine_dai_dma_data playback_dma_data; 182 183 /* Register fields for i2s */ 184 struct regmap_field *field_clkdiv_mclk_en; 185 struct regmap_field *field_fmt_wss; 186 struct regmap_field *field_fmt_sr; 187 struct regmap_field *field_fmt_bclk; 188 struct regmap_field *field_fmt_lrclk; 189 struct regmap_field *field_fmt_mode; 190 struct regmap_field *field_txchanmap; 191 struct regmap_field *field_rxchanmap; 192 struct regmap_field *field_txchansel; 193 struct regmap_field *field_rxchansel; 194 195 const struct sun4i_i2s_quirks *variant; 196 }; 197 198 struct sun4i_i2s_clk_div { 199 u8 div; 200 u8 val; 201 }; 202 203 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = { 204 { .div = 2, .val = 0 }, 205 { .div = 4, .val = 1 }, 206 { .div = 6, .val = 2 }, 207 { .div = 8, .val = 3 }, 208 { .div = 12, .val = 4 }, 209 { .div = 16, .val = 5 }, 210 /* TODO - extend divide ratio supported by newer SoCs */ 211 }; 212 213 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { 214 { .div = 1, .val = 0 }, 215 { .div = 2, .val = 1 }, 216 { .div = 4, .val = 2 }, 217 { .div = 6, .val = 3 }, 218 { .div = 8, .val = 4 }, 219 { .div = 12, .val = 5 }, 220 { .div = 16, .val = 6 }, 221 { .div = 24, .val = 7 }, 222 /* TODO - extend divide ratio supported by newer SoCs */ 223 }; 224 225 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, 226 unsigned int oversample_rate, 227 unsigned int word_size) 228 { 229 int div = oversample_rate / word_size / 2; 230 int i; 231 232 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) { 233 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i]; 234 235 if (bdiv->div == div) 236 return bdiv->val; 237 } 238 239 return -EINVAL; 240 } 241 242 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, 243 unsigned int oversample_rate, 244 unsigned int module_rate, 245 unsigned int sampling_rate) 246 { 247 int div = module_rate / sampling_rate / oversample_rate; 248 int i; 249 250 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) { 251 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i]; 252 253 if (mdiv->div == div) 254 return mdiv->val; 255 } 256 257 return -EINVAL; 258 } 259 260 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 }; 261 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) 262 { 263 int i; 264 265 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) 266 if (sun4i_i2s_oversample_rates[i] == oversample) 267 return true; 268 269 return false; 270 } 271 272 static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s, 273 unsigned int rate, 274 unsigned int word_size) 275 { 276 unsigned int oversample_rate, clk_rate; 277 int bclk_div, mclk_div; 278 int ret; 279 280 switch (rate) { 281 case 176400: 282 case 88200: 283 case 44100: 284 case 22050: 285 case 11025: 286 clk_rate = 22579200; 287 break; 288 289 case 192000: 290 case 128000: 291 case 96000: 292 case 64000: 293 case 48000: 294 case 32000: 295 case 24000: 296 case 16000: 297 case 12000: 298 case 8000: 299 clk_rate = 24576000; 300 break; 301 302 default: 303 return -EINVAL; 304 } 305 306 ret = clk_set_rate(i2s->mod_clk, clk_rate); 307 if (ret) 308 return ret; 309 310 oversample_rate = i2s->mclk_freq / rate; 311 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) 312 return -EINVAL; 313 314 bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate, 315 word_size); 316 if (bclk_div < 0) 317 return -EINVAL; 318 319 mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, 320 clk_rate, rate); 321 if (mclk_div < 0) 322 return -EINVAL; 323 324 /* Adjust the clock division values if needed */ 325 bclk_div += i2s->variant->bclk_offset; 326 mclk_div += i2s->variant->mclk_offset; 327 328 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, 329 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | 330 SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); 331 332 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); 333 334 /* Set sync period */ 335 if (i2s->variant->has_fmt_set_lrck_period) 336 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 337 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, 338 SUN8I_I2S_FMT0_LRCK_PERIOD(32)); 339 340 return 0; 341 } 342 343 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, 344 struct snd_pcm_hw_params *params, 345 struct snd_soc_dai *dai) 346 { 347 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 348 int sr, wss, channels; 349 u32 width; 350 351 channels = params_channels(params); 352 if (channels != 2) 353 return -EINVAL; 354 355 if (i2s->variant->has_chcfg) { 356 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 357 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, 358 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); 359 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 360 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, 361 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); 362 } 363 364 /* Map the channels for playback and capture */ 365 regmap_field_write(i2s->field_txchanmap, 0x76543210); 366 regmap_field_write(i2s->field_rxchanmap, 0x00003210); 367 368 /* Configure the channels */ 369 regmap_field_write(i2s->field_txchansel, 370 SUN4I_I2S_CHAN_SEL(params_channels(params))); 371 372 regmap_field_write(i2s->field_rxchansel, 373 SUN4I_I2S_CHAN_SEL(params_channels(params))); 374 375 if (i2s->variant->has_chsel_tx_chen) 376 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 377 SUN8I_I2S_TX_CHAN_EN_MASK, 378 SUN8I_I2S_TX_CHAN_EN(channels)); 379 380 switch (params_physical_width(params)) { 381 case 16: 382 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 383 break; 384 default: 385 return -EINVAL; 386 } 387 i2s->playback_dma_data.addr_width = width; 388 389 switch (params_width(params)) { 390 case 16: 391 sr = 0; 392 wss = 0; 393 break; 394 395 default: 396 return -EINVAL; 397 } 398 399 regmap_field_write(i2s->field_fmt_wss, 400 wss + i2s->variant->fmt_offset); 401 regmap_field_write(i2s->field_fmt_sr, 402 sr + i2s->variant->fmt_offset); 403 404 return sun4i_i2s_set_clk_rate(i2s, params_rate(params), 405 params_width(params)); 406 } 407 408 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 409 { 410 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 411 u32 val; 412 u32 offset = 0; 413 u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; 414 u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; 415 416 /* DAI Mode */ 417 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 418 case SND_SOC_DAIFMT_I2S: 419 val = SUN4I_I2S_FMT0_FMT_I2S; 420 offset = 1; 421 break; 422 case SND_SOC_DAIFMT_LEFT_J: 423 val = SUN4I_I2S_FMT0_FMT_LEFT_J; 424 break; 425 case SND_SOC_DAIFMT_RIGHT_J: 426 val = SUN4I_I2S_FMT0_FMT_RIGHT_J; 427 break; 428 default: 429 return -EINVAL; 430 } 431 432 if (i2s->variant->has_chsel_offset) { 433 /* 434 * offset being set indicates that we're connected to an i2s 435 * device, however offset is only used on the sun8i block and 436 * i2s shares the same setting with the LJ format. Increment 437 * val so that the bit to value to write is correct. 438 */ 439 if (offset > 0) 440 val++; 441 /* blck offset determines whether i2s or LJ */ 442 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 443 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 444 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 445 } 446 447 regmap_field_write(i2s->field_fmt_mode, val); 448 449 /* DAI clock polarity */ 450 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 451 case SND_SOC_DAIFMT_IB_IF: 452 /* Invert both clocks */ 453 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 454 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 455 break; 456 case SND_SOC_DAIFMT_IB_NF: 457 /* Invert bit clock */ 458 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 459 break; 460 case SND_SOC_DAIFMT_NB_IF: 461 /* Invert frame clock */ 462 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 463 break; 464 case SND_SOC_DAIFMT_NB_NF: 465 break; 466 default: 467 return -EINVAL; 468 } 469 470 regmap_field_write(i2s->field_fmt_bclk, bclk_polarity); 471 regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity); 472 473 if (i2s->variant->has_slave_select_bit) { 474 /* DAI clock master masks */ 475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 476 case SND_SOC_DAIFMT_CBS_CFS: 477 /* BCLK and LRCLK master */ 478 val = SUN4I_I2S_CTRL_MODE_MASTER; 479 break; 480 case SND_SOC_DAIFMT_CBM_CFM: 481 /* BCLK and LRCLK slave */ 482 val = SUN4I_I2S_CTRL_MODE_SLAVE; 483 break; 484 default: 485 return -EINVAL; 486 } 487 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 488 SUN4I_I2S_CTRL_MODE_MASK, 489 val); 490 } else { 491 /* 492 * The newer i2s block does not have a slave select bit, 493 * instead the clk pins are configured as inputs. 494 */ 495 /* DAI clock master masks */ 496 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 497 case SND_SOC_DAIFMT_CBS_CFS: 498 /* BCLK and LRCLK master */ 499 val = SUN8I_I2S_CTRL_BCLK_OUT | 500 SUN8I_I2S_CTRL_LRCK_OUT; 501 break; 502 case SND_SOC_DAIFMT_CBM_CFM: 503 /* BCLK and LRCLK slave */ 504 val = 0; 505 break; 506 default: 507 return -EINVAL; 508 } 509 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 510 SUN8I_I2S_CTRL_BCLK_OUT | 511 SUN8I_I2S_CTRL_LRCK_OUT, 512 val); 513 } 514 515 /* Set significant bits in our FIFOs */ 516 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 517 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | 518 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, 519 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | 520 SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); 521 return 0; 522 } 523 524 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) 525 { 526 /* Flush RX FIFO */ 527 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 528 SUN4I_I2S_FIFO_CTRL_FLUSH_RX, 529 SUN4I_I2S_FIFO_CTRL_FLUSH_RX); 530 531 /* Clear RX counter */ 532 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); 533 534 /* Enable RX Block */ 535 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 536 SUN4I_I2S_CTRL_RX_EN, 537 SUN4I_I2S_CTRL_RX_EN); 538 539 /* Enable RX DRQ */ 540 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 541 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 542 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN); 543 } 544 545 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) 546 { 547 /* Flush TX FIFO */ 548 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 549 SUN4I_I2S_FIFO_CTRL_FLUSH_TX, 550 SUN4I_I2S_FIFO_CTRL_FLUSH_TX); 551 552 /* Clear TX counter */ 553 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); 554 555 /* Enable TX Block */ 556 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 557 SUN4I_I2S_CTRL_TX_EN, 558 SUN4I_I2S_CTRL_TX_EN); 559 560 /* Enable TX DRQ */ 561 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 562 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 563 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN); 564 } 565 566 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s) 567 { 568 /* Disable RX Block */ 569 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 570 SUN4I_I2S_CTRL_RX_EN, 571 0); 572 573 /* Disable RX DRQ */ 574 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 575 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 576 0); 577 } 578 579 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s) 580 { 581 /* Disable TX Block */ 582 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 583 SUN4I_I2S_CTRL_TX_EN, 584 0); 585 586 /* Disable TX DRQ */ 587 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 588 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 589 0); 590 } 591 592 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 593 struct snd_soc_dai *dai) 594 { 595 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 596 597 switch (cmd) { 598 case SNDRV_PCM_TRIGGER_START: 599 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 600 case SNDRV_PCM_TRIGGER_RESUME: 601 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 602 sun4i_i2s_start_playback(i2s); 603 else 604 sun4i_i2s_start_capture(i2s); 605 break; 606 607 case SNDRV_PCM_TRIGGER_STOP: 608 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 609 case SNDRV_PCM_TRIGGER_SUSPEND: 610 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 611 sun4i_i2s_stop_playback(i2s); 612 else 613 sun4i_i2s_stop_capture(i2s); 614 break; 615 616 default: 617 return -EINVAL; 618 } 619 620 return 0; 621 } 622 623 static int sun4i_i2s_startup(struct snd_pcm_substream *substream, 624 struct snd_soc_dai *dai) 625 { 626 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 627 628 /* Enable the whole hardware block */ 629 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 630 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN); 631 632 /* Enable the first output line */ 633 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 634 SUN4I_I2S_CTRL_SDO_EN_MASK, 635 SUN4I_I2S_CTRL_SDO_EN(0)); 636 637 638 return clk_prepare_enable(i2s->mod_clk); 639 } 640 641 static void sun4i_i2s_shutdown(struct snd_pcm_substream *substream, 642 struct snd_soc_dai *dai) 643 { 644 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 645 646 clk_disable_unprepare(i2s->mod_clk); 647 648 /* Disable our output lines */ 649 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 650 SUN4I_I2S_CTRL_SDO_EN_MASK, 0); 651 652 /* Disable the whole hardware block */ 653 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 654 SUN4I_I2S_CTRL_GL_EN, 0); 655 } 656 657 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 658 unsigned int freq, int dir) 659 { 660 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 661 662 if (clk_id != 0) 663 return -EINVAL; 664 665 i2s->mclk_freq = freq; 666 667 return 0; 668 } 669 670 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { 671 .hw_params = sun4i_i2s_hw_params, 672 .set_fmt = sun4i_i2s_set_fmt, 673 .set_sysclk = sun4i_i2s_set_sysclk, 674 .shutdown = sun4i_i2s_shutdown, 675 .startup = sun4i_i2s_startup, 676 .trigger = sun4i_i2s_trigger, 677 }; 678 679 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) 680 { 681 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 682 683 snd_soc_dai_init_dma_data(dai, 684 &i2s->playback_dma_data, 685 &i2s->capture_dma_data); 686 687 snd_soc_dai_set_drvdata(dai, i2s); 688 689 return 0; 690 } 691 692 static struct snd_soc_dai_driver sun4i_i2s_dai = { 693 .probe = sun4i_i2s_dai_probe, 694 .capture = { 695 .stream_name = "Capture", 696 .channels_min = 2, 697 .channels_max = 2, 698 .rates = SNDRV_PCM_RATE_8000_192000, 699 .formats = SNDRV_PCM_FMTBIT_S16_LE, 700 }, 701 .playback = { 702 .stream_name = "Playback", 703 .channels_min = 2, 704 .channels_max = 2, 705 .rates = SNDRV_PCM_RATE_8000_192000, 706 .formats = SNDRV_PCM_FMTBIT_S16_LE, 707 }, 708 .ops = &sun4i_i2s_dai_ops, 709 .symmetric_rates = 1, 710 }; 711 712 static const struct snd_soc_component_driver sun4i_i2s_component = { 713 .name = "sun4i-dai", 714 }; 715 716 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) 717 { 718 switch (reg) { 719 case SUN4I_I2S_FIFO_TX_REG: 720 return false; 721 722 default: 723 return true; 724 } 725 } 726 727 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg) 728 { 729 switch (reg) { 730 case SUN4I_I2S_FIFO_RX_REG: 731 case SUN4I_I2S_FIFO_STA_REG: 732 return false; 733 734 default: 735 return true; 736 } 737 } 738 739 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) 740 { 741 switch (reg) { 742 case SUN4I_I2S_FIFO_RX_REG: 743 case SUN4I_I2S_INT_STA_REG: 744 case SUN4I_I2S_RX_CNT_REG: 745 case SUN4I_I2S_TX_CNT_REG: 746 return true; 747 748 default: 749 return false; 750 } 751 } 752 753 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) 754 { 755 switch (reg) { 756 case SUN8I_I2S_FIFO_TX_REG: 757 return false; 758 759 default: 760 return true; 761 } 762 } 763 764 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) 765 { 766 if (reg == SUN8I_I2S_INT_STA_REG) 767 return true; 768 if (reg == SUN8I_I2S_FIFO_TX_REG) 769 return false; 770 771 return sun4i_i2s_volatile_reg(dev, reg); 772 } 773 774 static const struct reg_default sun4i_i2s_reg_defaults[] = { 775 { SUN4I_I2S_CTRL_REG, 0x00000000 }, 776 { SUN4I_I2S_FMT0_REG, 0x0000000c }, 777 { SUN4I_I2S_FMT1_REG, 0x00004020 }, 778 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 779 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 780 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 781 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 }, 782 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 }, 783 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 }, 784 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, 785 }; 786 787 static const struct reg_default sun8i_i2s_reg_defaults[] = { 788 { SUN4I_I2S_CTRL_REG, 0x00060000 }, 789 { SUN4I_I2S_FMT0_REG, 0x00000033 }, 790 { SUN4I_I2S_FMT1_REG, 0x00000030 }, 791 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 792 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 793 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 794 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, 795 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, 796 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 }, 797 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, 798 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, 799 }; 800 801 static const struct regmap_config sun4i_i2s_regmap_config = { 802 .reg_bits = 32, 803 .reg_stride = 4, 804 .val_bits = 32, 805 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG, 806 807 .cache_type = REGCACHE_FLAT, 808 .reg_defaults = sun4i_i2s_reg_defaults, 809 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults), 810 .writeable_reg = sun4i_i2s_wr_reg, 811 .readable_reg = sun4i_i2s_rd_reg, 812 .volatile_reg = sun4i_i2s_volatile_reg, 813 }; 814 815 static const struct regmap_config sun8i_i2s_regmap_config = { 816 .reg_bits = 32, 817 .reg_stride = 4, 818 .val_bits = 32, 819 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG, 820 .cache_type = REGCACHE_FLAT, 821 .reg_defaults = sun8i_i2s_reg_defaults, 822 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults), 823 .writeable_reg = sun4i_i2s_wr_reg, 824 .readable_reg = sun8i_i2s_rd_reg, 825 .volatile_reg = sun8i_i2s_volatile_reg, 826 }; 827 828 static int sun4i_i2s_runtime_resume(struct device *dev) 829 { 830 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 831 int ret; 832 833 ret = clk_prepare_enable(i2s->bus_clk); 834 if (ret) { 835 dev_err(dev, "Failed to enable bus clock\n"); 836 return ret; 837 } 838 839 regcache_cache_only(i2s->regmap, false); 840 regcache_mark_dirty(i2s->regmap); 841 842 ret = regcache_sync(i2s->regmap); 843 if (ret) { 844 dev_err(dev, "Failed to sync regmap cache\n"); 845 goto err_disable_clk; 846 } 847 848 return 0; 849 850 err_disable_clk: 851 clk_disable_unprepare(i2s->bus_clk); 852 return ret; 853 } 854 855 static int sun4i_i2s_runtime_suspend(struct device *dev) 856 { 857 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 858 859 regcache_cache_only(i2s->regmap, true); 860 861 clk_disable_unprepare(i2s->bus_clk); 862 863 return 0; 864 } 865 866 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { 867 .has_reset = false, 868 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 869 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 870 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 871 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 872 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 873 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 874 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 875 .has_slave_select_bit = true, 876 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 877 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 878 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 879 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 880 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 881 }; 882 883 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { 884 .has_reset = true, 885 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 886 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 887 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 888 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 889 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 890 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 891 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 892 .has_slave_select_bit = true, 893 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 894 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 895 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 896 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 897 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 898 }; 899 900 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { 901 .has_reset = true, 902 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 903 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, 904 .mclk_offset = 1, 905 .bclk_offset = 2, 906 .fmt_offset = 3, 907 .has_fmt_set_lrck_period = true, 908 .has_chcfg = true, 909 .has_chsel_tx_chen = true, 910 .has_chsel_offset = true, 911 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 912 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 913 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 914 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 915 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), 916 .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), 917 .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), 918 .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), 919 .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), 920 .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2), 921 }; 922 923 static int sun4i_i2s_init_regmap_fields(struct device *dev, 924 struct sun4i_i2s *i2s) 925 { 926 i2s->field_clkdiv_mclk_en = 927 devm_regmap_field_alloc(dev, i2s->regmap, 928 i2s->variant->field_clkdiv_mclk_en); 929 if (IS_ERR(i2s->field_clkdiv_mclk_en)) 930 return PTR_ERR(i2s->field_clkdiv_mclk_en); 931 932 i2s->field_fmt_wss = 933 devm_regmap_field_alloc(dev, i2s->regmap, 934 i2s->variant->field_fmt_wss); 935 if (IS_ERR(i2s->field_fmt_wss)) 936 return PTR_ERR(i2s->field_fmt_wss); 937 938 i2s->field_fmt_sr = 939 devm_regmap_field_alloc(dev, i2s->regmap, 940 i2s->variant->field_fmt_sr); 941 if (IS_ERR(i2s->field_fmt_sr)) 942 return PTR_ERR(i2s->field_fmt_sr); 943 944 i2s->field_fmt_bclk = 945 devm_regmap_field_alloc(dev, i2s->regmap, 946 i2s->variant->field_fmt_bclk); 947 if (IS_ERR(i2s->field_fmt_bclk)) 948 return PTR_ERR(i2s->field_fmt_bclk); 949 950 i2s->field_fmt_lrclk = 951 devm_regmap_field_alloc(dev, i2s->regmap, 952 i2s->variant->field_fmt_lrclk); 953 if (IS_ERR(i2s->field_fmt_lrclk)) 954 return PTR_ERR(i2s->field_fmt_lrclk); 955 956 i2s->field_fmt_mode = 957 devm_regmap_field_alloc(dev, i2s->regmap, 958 i2s->variant->field_fmt_mode); 959 if (IS_ERR(i2s->field_fmt_mode)) 960 return PTR_ERR(i2s->field_fmt_mode); 961 962 i2s->field_txchanmap = 963 devm_regmap_field_alloc(dev, i2s->regmap, 964 i2s->variant->field_txchanmap); 965 if (IS_ERR(i2s->field_txchanmap)) 966 return PTR_ERR(i2s->field_txchanmap); 967 968 i2s->field_rxchanmap = 969 devm_regmap_field_alloc(dev, i2s->regmap, 970 i2s->variant->field_rxchanmap); 971 if (IS_ERR(i2s->field_rxchanmap)) 972 return PTR_ERR(i2s->field_rxchanmap); 973 974 i2s->field_txchansel = 975 devm_regmap_field_alloc(dev, i2s->regmap, 976 i2s->variant->field_txchansel); 977 if (IS_ERR(i2s->field_txchansel)) 978 return PTR_ERR(i2s->field_txchansel); 979 980 i2s->field_rxchansel = 981 devm_regmap_field_alloc(dev, i2s->regmap, 982 i2s->variant->field_rxchansel); 983 return PTR_ERR_OR_ZERO(i2s->field_rxchansel); 984 } 985 986 static int sun4i_i2s_probe(struct platform_device *pdev) 987 { 988 struct sun4i_i2s *i2s; 989 struct resource *res; 990 void __iomem *regs; 991 int irq, ret; 992 993 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 994 if (!i2s) 995 return -ENOMEM; 996 platform_set_drvdata(pdev, i2s); 997 998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 999 regs = devm_ioremap_resource(&pdev->dev, res); 1000 if (IS_ERR(regs)) 1001 return PTR_ERR(regs); 1002 1003 irq = platform_get_irq(pdev, 0); 1004 if (irq < 0) { 1005 dev_err(&pdev->dev, "Can't retrieve our interrupt\n"); 1006 return irq; 1007 } 1008 1009 i2s->variant = of_device_get_match_data(&pdev->dev); 1010 if (!i2s->variant) { 1011 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1012 return -ENODEV; 1013 } 1014 1015 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); 1016 if (IS_ERR(i2s->bus_clk)) { 1017 dev_err(&pdev->dev, "Can't get our bus clock\n"); 1018 return PTR_ERR(i2s->bus_clk); 1019 } 1020 1021 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1022 i2s->variant->sun4i_i2s_regmap); 1023 if (IS_ERR(i2s->regmap)) { 1024 dev_err(&pdev->dev, "Regmap initialisation failed\n"); 1025 return PTR_ERR(i2s->regmap); 1026 } 1027 1028 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); 1029 if (IS_ERR(i2s->mod_clk)) { 1030 dev_err(&pdev->dev, "Can't get our mod clock\n"); 1031 return PTR_ERR(i2s->mod_clk); 1032 } 1033 1034 if (i2s->variant->has_reset) { 1035 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1036 if (IS_ERR(i2s->rst)) { 1037 dev_err(&pdev->dev, "Failed to get reset control\n"); 1038 return PTR_ERR(i2s->rst); 1039 } 1040 } 1041 1042 if (!IS_ERR(i2s->rst)) { 1043 ret = reset_control_deassert(i2s->rst); 1044 if (ret) { 1045 dev_err(&pdev->dev, 1046 "Failed to deassert the reset control\n"); 1047 return -EINVAL; 1048 } 1049 } 1050 1051 i2s->playback_dma_data.addr = res->start + 1052 i2s->variant->reg_offset_txdata; 1053 i2s->playback_dma_data.maxburst = 8; 1054 1055 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; 1056 i2s->capture_dma_data.maxburst = 8; 1057 1058 pm_runtime_enable(&pdev->dev); 1059 if (!pm_runtime_enabled(&pdev->dev)) { 1060 ret = sun4i_i2s_runtime_resume(&pdev->dev); 1061 if (ret) 1062 goto err_pm_disable; 1063 } 1064 1065 ret = devm_snd_soc_register_component(&pdev->dev, 1066 &sun4i_i2s_component, 1067 &sun4i_i2s_dai, 1); 1068 if (ret) { 1069 dev_err(&pdev->dev, "Could not register DAI\n"); 1070 goto err_suspend; 1071 } 1072 1073 ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1074 if (ret) { 1075 dev_err(&pdev->dev, "Could not register PCM\n"); 1076 goto err_suspend; 1077 } 1078 1079 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); 1080 if (ret) { 1081 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); 1082 goto err_suspend; 1083 } 1084 1085 return 0; 1086 1087 err_suspend: 1088 if (!pm_runtime_status_suspended(&pdev->dev)) 1089 sun4i_i2s_runtime_suspend(&pdev->dev); 1090 err_pm_disable: 1091 pm_runtime_disable(&pdev->dev); 1092 if (!IS_ERR(i2s->rst)) 1093 reset_control_assert(i2s->rst); 1094 1095 return ret; 1096 } 1097 1098 static int sun4i_i2s_remove(struct platform_device *pdev) 1099 { 1100 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); 1101 1102 snd_dmaengine_pcm_unregister(&pdev->dev); 1103 1104 pm_runtime_disable(&pdev->dev); 1105 if (!pm_runtime_status_suspended(&pdev->dev)) 1106 sun4i_i2s_runtime_suspend(&pdev->dev); 1107 1108 if (!IS_ERR(i2s->rst)) 1109 reset_control_assert(i2s->rst); 1110 1111 return 0; 1112 } 1113 1114 static const struct of_device_id sun4i_i2s_match[] = { 1115 { 1116 .compatible = "allwinner,sun4i-a10-i2s", 1117 .data = &sun4i_a10_i2s_quirks, 1118 }, 1119 { 1120 .compatible = "allwinner,sun6i-a31-i2s", 1121 .data = &sun6i_a31_i2s_quirks, 1122 }, 1123 { 1124 .compatible = "allwinner,sun8i-h3-i2s", 1125 .data = &sun8i_h3_i2s_quirks, 1126 }, 1127 {} 1128 }; 1129 MODULE_DEVICE_TABLE(of, sun4i_i2s_match); 1130 1131 static const struct dev_pm_ops sun4i_i2s_pm_ops = { 1132 .runtime_resume = sun4i_i2s_runtime_resume, 1133 .runtime_suspend = sun4i_i2s_runtime_suspend, 1134 }; 1135 1136 static struct platform_driver sun4i_i2s_driver = { 1137 .probe = sun4i_i2s_probe, 1138 .remove = sun4i_i2s_remove, 1139 .driver = { 1140 .name = "sun4i-i2s", 1141 .of_match_table = sun4i_i2s_match, 1142 .pm = &sun4i_i2s_pm_ops, 1143 }, 1144 }; 1145 module_platform_driver(sun4i_i2s_driver); 1146 1147 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>"); 1148 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1149 MODULE_DESCRIPTION("Allwinner A10 I2S driver"); 1150 MODULE_LICENSE("GPL"); 1151