1 /* 2 * Copyright (C) 2015 Andrea Venturi 3 * Andrea Venturi <be17068@iperbole.bo.it> 4 * 5 * Copyright (C) 2016 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/dmaengine.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 23 #include <sound/dmaengine_pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dai.h> 27 28 #define SUN4I_I2S_CTRL_REG 0x00 29 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8) 30 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) 31 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5) 32 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5) 33 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5) 34 #define SUN4I_I2S_CTRL_TX_EN BIT(2) 35 #define SUN4I_I2S_CTRL_RX_EN BIT(1) 36 #define SUN4I_I2S_CTRL_GL_EN BIT(0) 37 38 #define SUN4I_I2S_FMT0_REG 0x04 39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7) 40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7) 41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7) 42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6) 43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6) 44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6) 45 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4) 46 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4) 47 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2) 48 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2) 49 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0) 50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) 51 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) 52 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) 53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED (1) 54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL (0) 55 56 #define SUN4I_I2S_FMT1_REG 0x08 57 #define SUN4I_I2S_FIFO_TX_REG 0x0c 58 #define SUN4I_I2S_FIFO_RX_REG 0x10 59 60 #define SUN4I_I2S_FIFO_CTRL_REG 0x14 61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25) 62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24) 63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2) 64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2) 65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0) 66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode) 67 68 #define SUN4I_I2S_FIFO_STA_REG 0x18 69 70 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c 71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7) 72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3) 73 74 #define SUN4I_I2S_INT_STA_REG 0x20 75 76 #define SUN4I_I2S_CLK_DIV_REG 0x24 77 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) 78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) 79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) 80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) 81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) 82 83 #define SUN4I_I2S_RX_CNT_REG 0x28 84 #define SUN4I_I2S_TX_CNT_REG 0x2c 85 86 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 87 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) 88 89 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) 91 92 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 93 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c 94 95 /* Defines required for sun8i-h3 support */ 96 #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) 97 #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) 98 99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) 101 102 #define SUN8I_I2S_INT_STA_REG 0x0c 103 #define SUN8I_I2S_FIFO_TX_REG 0x20 104 105 #define SUN8I_I2S_CHAN_CFG_REG 0x30 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4) 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) 110 111 #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 112 #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 11) 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) 115 #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) 117 118 #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 119 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 120 121 /** 122 * struct sun4i_i2s_quirks - Differences between SoC variants. 123 * 124 * @has_reset: SoC needs reset deasserted. 125 * @has_slave_select_bit: SoC has a bit to enable slave mode. 126 * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. 127 * @has_chcfg: tx and rx slot number need to be set. 128 * @has_chsel_tx_chen: SoC requires that the tx channels are enabled. 129 * @has_chsel_offset: SoC uses offset for selecting dai operational mode. 130 * @reg_offset_txdata: offset of the tx fifo. 131 * @sun4i_i2s_regmap: regmap config to use. 132 * @mclk_offset: Value by which mclkdiv needs to be adjusted. 133 * @bclk_offset: Value by which bclkdiv needs to be adjusted. 134 * @fmt_offset: Value by which wss and sr needs to be adjusted. 135 * @field_clkdiv_mclk_en: regmap field to enable mclk output. 136 * @field_fmt_wss: regmap field to set word select size. 137 * @field_fmt_sr: regmap field to set sample resolution. 138 * @field_fmt_bclk: regmap field to set clk polarity. 139 * @field_fmt_lrclk: regmap field to set frame polarity. 140 * @field_fmt_mode: regmap field to set the operational mode. 141 * @field_txchanmap: location of the tx channel mapping register. 142 * @field_rxchanmap: location of the rx channel mapping register. 143 * @field_txchansel: location of the tx channel select bit fields. 144 * @field_rxchansel: location of the rx channel select bit fields. 145 */ 146 struct sun4i_i2s_quirks { 147 bool has_reset; 148 bool has_slave_select_bit; 149 bool has_fmt_set_lrck_period; 150 bool has_chcfg; 151 bool has_chsel_tx_chen; 152 bool has_chsel_offset; 153 unsigned int reg_offset_txdata; /* TX FIFO */ 154 const struct regmap_config *sun4i_i2s_regmap; 155 unsigned int mclk_offset; 156 unsigned int bclk_offset; 157 unsigned int fmt_offset; 158 159 /* Register fields for i2s */ 160 struct reg_field field_clkdiv_mclk_en; 161 struct reg_field field_fmt_wss; 162 struct reg_field field_fmt_sr; 163 struct reg_field field_fmt_bclk; 164 struct reg_field field_fmt_lrclk; 165 struct reg_field field_fmt_mode; 166 struct reg_field field_txchanmap; 167 struct reg_field field_rxchanmap; 168 struct reg_field field_txchansel; 169 struct reg_field field_rxchansel; 170 }; 171 172 struct sun4i_i2s { 173 struct clk *bus_clk; 174 struct clk *mod_clk; 175 struct regmap *regmap; 176 struct reset_control *rst; 177 178 unsigned int mclk_freq; 179 180 struct snd_dmaengine_dai_dma_data capture_dma_data; 181 struct snd_dmaengine_dai_dma_data playback_dma_data; 182 183 /* Register fields for i2s */ 184 struct regmap_field *field_clkdiv_mclk_en; 185 struct regmap_field *field_fmt_wss; 186 struct regmap_field *field_fmt_sr; 187 struct regmap_field *field_fmt_bclk; 188 struct regmap_field *field_fmt_lrclk; 189 struct regmap_field *field_fmt_mode; 190 struct regmap_field *field_txchanmap; 191 struct regmap_field *field_rxchanmap; 192 struct regmap_field *field_txchansel; 193 struct regmap_field *field_rxchansel; 194 195 const struct sun4i_i2s_quirks *variant; 196 }; 197 198 struct sun4i_i2s_clk_div { 199 u8 div; 200 u8 val; 201 }; 202 203 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = { 204 { .div = 2, .val = 0 }, 205 { .div = 4, .val = 1 }, 206 { .div = 6, .val = 2 }, 207 { .div = 8, .val = 3 }, 208 { .div = 12, .val = 4 }, 209 { .div = 16, .val = 5 }, 210 /* TODO - extend divide ratio supported by newer SoCs */ 211 }; 212 213 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { 214 { .div = 1, .val = 0 }, 215 { .div = 2, .val = 1 }, 216 { .div = 4, .val = 2 }, 217 { .div = 6, .val = 3 }, 218 { .div = 8, .val = 4 }, 219 { .div = 12, .val = 5 }, 220 { .div = 16, .val = 6 }, 221 { .div = 24, .val = 7 }, 222 /* TODO - extend divide ratio supported by newer SoCs */ 223 }; 224 225 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, 226 unsigned int oversample_rate, 227 unsigned int word_size) 228 { 229 int div = oversample_rate / word_size / 2; 230 int i; 231 232 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) { 233 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i]; 234 235 if (bdiv->div == div) 236 return bdiv->val; 237 } 238 239 return -EINVAL; 240 } 241 242 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, 243 unsigned int oversample_rate, 244 unsigned int module_rate, 245 unsigned int sampling_rate) 246 { 247 int div = module_rate / sampling_rate / oversample_rate; 248 int i; 249 250 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) { 251 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i]; 252 253 if (mdiv->div == div) 254 return mdiv->val; 255 } 256 257 return -EINVAL; 258 } 259 260 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 }; 261 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) 262 { 263 int i; 264 265 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) 266 if (sun4i_i2s_oversample_rates[i] == oversample) 267 return true; 268 269 return false; 270 } 271 272 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, 273 unsigned int rate, 274 unsigned int word_size) 275 { 276 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 277 unsigned int oversample_rate, clk_rate; 278 int bclk_div, mclk_div; 279 int ret; 280 281 switch (rate) { 282 case 176400: 283 case 88200: 284 case 44100: 285 case 22050: 286 case 11025: 287 clk_rate = 22579200; 288 break; 289 290 case 192000: 291 case 128000: 292 case 96000: 293 case 64000: 294 case 48000: 295 case 32000: 296 case 24000: 297 case 16000: 298 case 12000: 299 case 8000: 300 clk_rate = 24576000; 301 break; 302 303 default: 304 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); 305 return -EINVAL; 306 } 307 308 ret = clk_set_rate(i2s->mod_clk, clk_rate); 309 if (ret) 310 return ret; 311 312 oversample_rate = i2s->mclk_freq / rate; 313 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) { 314 dev_err(dai->dev, "Unsupported oversample rate: %d\n", 315 oversample_rate); 316 return -EINVAL; 317 } 318 319 bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate, 320 word_size); 321 if (bclk_div < 0) { 322 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); 323 return -EINVAL; 324 } 325 326 mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, 327 clk_rate, rate); 328 if (mclk_div < 0) { 329 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); 330 return -EINVAL; 331 } 332 333 /* Adjust the clock division values if needed */ 334 bclk_div += i2s->variant->bclk_offset; 335 mclk_div += i2s->variant->mclk_offset; 336 337 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, 338 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | 339 SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); 340 341 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); 342 343 /* Set sync period */ 344 if (i2s->variant->has_fmt_set_lrck_period) 345 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 346 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, 347 SUN8I_I2S_FMT0_LRCK_PERIOD(32)); 348 349 return 0; 350 } 351 352 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, 353 struct snd_pcm_hw_params *params, 354 struct snd_soc_dai *dai) 355 { 356 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 357 int sr, wss, channels; 358 u32 width; 359 360 channels = params_channels(params); 361 if (channels != 2) { 362 dev_err(dai->dev, "Unsupported number of channels: %d\n", 363 channels); 364 return -EINVAL; 365 } 366 367 if (i2s->variant->has_chcfg) { 368 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 369 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, 370 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); 371 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 372 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, 373 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); 374 } 375 376 /* Map the channels for playback and capture */ 377 regmap_field_write(i2s->field_txchanmap, 0x76543210); 378 regmap_field_write(i2s->field_rxchanmap, 0x00003210); 379 380 /* Configure the channels */ 381 regmap_field_write(i2s->field_txchansel, 382 SUN4I_I2S_CHAN_SEL(params_channels(params))); 383 384 regmap_field_write(i2s->field_rxchansel, 385 SUN4I_I2S_CHAN_SEL(params_channels(params))); 386 387 if (i2s->variant->has_chsel_tx_chen) 388 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 389 SUN8I_I2S_TX_CHAN_EN_MASK, 390 SUN8I_I2S_TX_CHAN_EN(channels)); 391 392 switch (params_physical_width(params)) { 393 case 16: 394 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 395 break; 396 default: 397 dev_err(dai->dev, "Unsupported physical sample width: %d\n", 398 params_physical_width(params)); 399 return -EINVAL; 400 } 401 i2s->playback_dma_data.addr_width = width; 402 403 switch (params_width(params)) { 404 case 16: 405 sr = 0; 406 wss = 0; 407 break; 408 409 default: 410 dev_err(dai->dev, "Unsupported sample width: %d\n", 411 params_width(params)); 412 return -EINVAL; 413 } 414 415 regmap_field_write(i2s->field_fmt_wss, 416 wss + i2s->variant->fmt_offset); 417 regmap_field_write(i2s->field_fmt_sr, 418 sr + i2s->variant->fmt_offset); 419 420 return sun4i_i2s_set_clk_rate(dai, params_rate(params), 421 params_width(params)); 422 } 423 424 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 425 { 426 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 427 u32 val; 428 u32 offset = 0; 429 u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; 430 u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; 431 432 /* DAI Mode */ 433 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 434 case SND_SOC_DAIFMT_I2S: 435 val = SUN4I_I2S_FMT0_FMT_I2S; 436 offset = 1; 437 break; 438 case SND_SOC_DAIFMT_LEFT_J: 439 val = SUN4I_I2S_FMT0_FMT_LEFT_J; 440 break; 441 case SND_SOC_DAIFMT_RIGHT_J: 442 val = SUN4I_I2S_FMT0_FMT_RIGHT_J; 443 break; 444 default: 445 dev_err(dai->dev, "Unsupported format: %d\n", 446 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 447 return -EINVAL; 448 } 449 450 if (i2s->variant->has_chsel_offset) { 451 /* 452 * offset being set indicates that we're connected to an i2s 453 * device, however offset is only used on the sun8i block and 454 * i2s shares the same setting with the LJ format. Increment 455 * val so that the bit to value to write is correct. 456 */ 457 if (offset > 0) 458 val++; 459 /* blck offset determines whether i2s or LJ */ 460 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 461 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 462 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 463 } 464 465 regmap_field_write(i2s->field_fmt_mode, val); 466 467 /* DAI clock polarity */ 468 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 469 case SND_SOC_DAIFMT_IB_IF: 470 /* Invert both clocks */ 471 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 472 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 473 break; 474 case SND_SOC_DAIFMT_IB_NF: 475 /* Invert bit clock */ 476 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 477 break; 478 case SND_SOC_DAIFMT_NB_IF: 479 /* Invert frame clock */ 480 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 481 break; 482 case SND_SOC_DAIFMT_NB_NF: 483 break; 484 default: 485 dev_err(dai->dev, "Unsupported clock polarity: %d\n", 486 fmt & SND_SOC_DAIFMT_INV_MASK); 487 return -EINVAL; 488 } 489 490 regmap_field_write(i2s->field_fmt_bclk, bclk_polarity); 491 regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity); 492 493 if (i2s->variant->has_slave_select_bit) { 494 /* DAI clock master masks */ 495 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 496 case SND_SOC_DAIFMT_CBS_CFS: 497 /* BCLK and LRCLK master */ 498 val = SUN4I_I2S_CTRL_MODE_MASTER; 499 break; 500 case SND_SOC_DAIFMT_CBM_CFM: 501 /* BCLK and LRCLK slave */ 502 val = SUN4I_I2S_CTRL_MODE_SLAVE; 503 break; 504 default: 505 dev_err(dai->dev, "Unsupported slave setting: %d\n", 506 fmt & SND_SOC_DAIFMT_MASTER_MASK); 507 return -EINVAL; 508 } 509 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 510 SUN4I_I2S_CTRL_MODE_MASK, 511 val); 512 } else { 513 /* 514 * The newer i2s block does not have a slave select bit, 515 * instead the clk pins are configured as inputs. 516 */ 517 /* DAI clock master masks */ 518 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 519 case SND_SOC_DAIFMT_CBS_CFS: 520 /* BCLK and LRCLK master */ 521 val = SUN8I_I2S_CTRL_BCLK_OUT | 522 SUN8I_I2S_CTRL_LRCK_OUT; 523 break; 524 case SND_SOC_DAIFMT_CBM_CFM: 525 /* BCLK and LRCLK slave */ 526 val = 0; 527 break; 528 default: 529 dev_err(dai->dev, "Unsupported slave setting: %d\n", 530 fmt & SND_SOC_DAIFMT_MASTER_MASK); 531 return -EINVAL; 532 } 533 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 534 SUN8I_I2S_CTRL_BCLK_OUT | 535 SUN8I_I2S_CTRL_LRCK_OUT, 536 val); 537 } 538 539 /* Set significant bits in our FIFOs */ 540 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 541 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | 542 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, 543 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | 544 SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); 545 return 0; 546 } 547 548 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) 549 { 550 /* Flush RX FIFO */ 551 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 552 SUN4I_I2S_FIFO_CTRL_FLUSH_RX, 553 SUN4I_I2S_FIFO_CTRL_FLUSH_RX); 554 555 /* Clear RX counter */ 556 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); 557 558 /* Enable RX Block */ 559 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 560 SUN4I_I2S_CTRL_RX_EN, 561 SUN4I_I2S_CTRL_RX_EN); 562 563 /* Enable RX DRQ */ 564 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 565 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 566 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN); 567 } 568 569 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) 570 { 571 /* Flush TX FIFO */ 572 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 573 SUN4I_I2S_FIFO_CTRL_FLUSH_TX, 574 SUN4I_I2S_FIFO_CTRL_FLUSH_TX); 575 576 /* Clear TX counter */ 577 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); 578 579 /* Enable TX Block */ 580 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 581 SUN4I_I2S_CTRL_TX_EN, 582 SUN4I_I2S_CTRL_TX_EN); 583 584 /* Enable TX DRQ */ 585 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 586 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 587 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN); 588 } 589 590 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s) 591 { 592 /* Disable RX Block */ 593 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 594 SUN4I_I2S_CTRL_RX_EN, 595 0); 596 597 /* Disable RX DRQ */ 598 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 599 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 600 0); 601 } 602 603 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s) 604 { 605 /* Disable TX Block */ 606 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 607 SUN4I_I2S_CTRL_TX_EN, 608 0); 609 610 /* Disable TX DRQ */ 611 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 612 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 613 0); 614 } 615 616 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 617 struct snd_soc_dai *dai) 618 { 619 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 620 621 switch (cmd) { 622 case SNDRV_PCM_TRIGGER_START: 623 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 624 case SNDRV_PCM_TRIGGER_RESUME: 625 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 626 sun4i_i2s_start_playback(i2s); 627 else 628 sun4i_i2s_start_capture(i2s); 629 break; 630 631 case SNDRV_PCM_TRIGGER_STOP: 632 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 633 case SNDRV_PCM_TRIGGER_SUSPEND: 634 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 635 sun4i_i2s_stop_playback(i2s); 636 else 637 sun4i_i2s_stop_capture(i2s); 638 break; 639 640 default: 641 return -EINVAL; 642 } 643 644 return 0; 645 } 646 647 static int sun4i_i2s_startup(struct snd_pcm_substream *substream, 648 struct snd_soc_dai *dai) 649 { 650 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 651 652 /* Enable the whole hardware block */ 653 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 654 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN); 655 656 /* Enable the first output line */ 657 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 658 SUN4I_I2S_CTRL_SDO_EN_MASK, 659 SUN4I_I2S_CTRL_SDO_EN(0)); 660 661 662 return clk_prepare_enable(i2s->mod_clk); 663 } 664 665 static void sun4i_i2s_shutdown(struct snd_pcm_substream *substream, 666 struct snd_soc_dai *dai) 667 { 668 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 669 670 clk_disable_unprepare(i2s->mod_clk); 671 672 /* Disable our output lines */ 673 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 674 SUN4I_I2S_CTRL_SDO_EN_MASK, 0); 675 676 /* Disable the whole hardware block */ 677 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 678 SUN4I_I2S_CTRL_GL_EN, 0); 679 } 680 681 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 682 unsigned int freq, int dir) 683 { 684 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 685 686 if (clk_id != 0) 687 return -EINVAL; 688 689 i2s->mclk_freq = freq; 690 691 return 0; 692 } 693 694 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { 695 .hw_params = sun4i_i2s_hw_params, 696 .set_fmt = sun4i_i2s_set_fmt, 697 .set_sysclk = sun4i_i2s_set_sysclk, 698 .shutdown = sun4i_i2s_shutdown, 699 .startup = sun4i_i2s_startup, 700 .trigger = sun4i_i2s_trigger, 701 }; 702 703 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) 704 { 705 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 706 707 snd_soc_dai_init_dma_data(dai, 708 &i2s->playback_dma_data, 709 &i2s->capture_dma_data); 710 711 snd_soc_dai_set_drvdata(dai, i2s); 712 713 return 0; 714 } 715 716 static struct snd_soc_dai_driver sun4i_i2s_dai = { 717 .probe = sun4i_i2s_dai_probe, 718 .capture = { 719 .stream_name = "Capture", 720 .channels_min = 2, 721 .channels_max = 2, 722 .rates = SNDRV_PCM_RATE_8000_192000, 723 .formats = SNDRV_PCM_FMTBIT_S16_LE, 724 }, 725 .playback = { 726 .stream_name = "Playback", 727 .channels_min = 2, 728 .channels_max = 2, 729 .rates = SNDRV_PCM_RATE_8000_192000, 730 .formats = SNDRV_PCM_FMTBIT_S16_LE, 731 }, 732 .ops = &sun4i_i2s_dai_ops, 733 .symmetric_rates = 1, 734 }; 735 736 static const struct snd_soc_component_driver sun4i_i2s_component = { 737 .name = "sun4i-dai", 738 }; 739 740 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) 741 { 742 switch (reg) { 743 case SUN4I_I2S_FIFO_TX_REG: 744 return false; 745 746 default: 747 return true; 748 } 749 } 750 751 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg) 752 { 753 switch (reg) { 754 case SUN4I_I2S_FIFO_RX_REG: 755 case SUN4I_I2S_FIFO_STA_REG: 756 return false; 757 758 default: 759 return true; 760 } 761 } 762 763 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) 764 { 765 switch (reg) { 766 case SUN4I_I2S_FIFO_RX_REG: 767 case SUN4I_I2S_INT_STA_REG: 768 case SUN4I_I2S_RX_CNT_REG: 769 case SUN4I_I2S_TX_CNT_REG: 770 return true; 771 772 default: 773 return false; 774 } 775 } 776 777 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) 778 { 779 switch (reg) { 780 case SUN8I_I2S_FIFO_TX_REG: 781 return false; 782 783 default: 784 return true; 785 } 786 } 787 788 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) 789 { 790 if (reg == SUN8I_I2S_INT_STA_REG) 791 return true; 792 if (reg == SUN8I_I2S_FIFO_TX_REG) 793 return false; 794 795 return sun4i_i2s_volatile_reg(dev, reg); 796 } 797 798 static const struct reg_default sun4i_i2s_reg_defaults[] = { 799 { SUN4I_I2S_CTRL_REG, 0x00000000 }, 800 { SUN4I_I2S_FMT0_REG, 0x0000000c }, 801 { SUN4I_I2S_FMT1_REG, 0x00004020 }, 802 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 803 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 804 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 805 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 }, 806 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 }, 807 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 }, 808 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, 809 }; 810 811 static const struct reg_default sun8i_i2s_reg_defaults[] = { 812 { SUN4I_I2S_CTRL_REG, 0x00060000 }, 813 { SUN4I_I2S_FMT0_REG, 0x00000033 }, 814 { SUN4I_I2S_FMT1_REG, 0x00000030 }, 815 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 816 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 817 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 818 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, 819 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, 820 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 }, 821 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, 822 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, 823 }; 824 825 static const struct regmap_config sun4i_i2s_regmap_config = { 826 .reg_bits = 32, 827 .reg_stride = 4, 828 .val_bits = 32, 829 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG, 830 831 .cache_type = REGCACHE_FLAT, 832 .reg_defaults = sun4i_i2s_reg_defaults, 833 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults), 834 .writeable_reg = sun4i_i2s_wr_reg, 835 .readable_reg = sun4i_i2s_rd_reg, 836 .volatile_reg = sun4i_i2s_volatile_reg, 837 }; 838 839 static const struct regmap_config sun8i_i2s_regmap_config = { 840 .reg_bits = 32, 841 .reg_stride = 4, 842 .val_bits = 32, 843 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG, 844 .cache_type = REGCACHE_FLAT, 845 .reg_defaults = sun8i_i2s_reg_defaults, 846 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults), 847 .writeable_reg = sun4i_i2s_wr_reg, 848 .readable_reg = sun8i_i2s_rd_reg, 849 .volatile_reg = sun8i_i2s_volatile_reg, 850 }; 851 852 static int sun4i_i2s_runtime_resume(struct device *dev) 853 { 854 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 855 int ret; 856 857 ret = clk_prepare_enable(i2s->bus_clk); 858 if (ret) { 859 dev_err(dev, "Failed to enable bus clock\n"); 860 return ret; 861 } 862 863 regcache_cache_only(i2s->regmap, false); 864 regcache_mark_dirty(i2s->regmap); 865 866 ret = regcache_sync(i2s->regmap); 867 if (ret) { 868 dev_err(dev, "Failed to sync regmap cache\n"); 869 goto err_disable_clk; 870 } 871 872 return 0; 873 874 err_disable_clk: 875 clk_disable_unprepare(i2s->bus_clk); 876 return ret; 877 } 878 879 static int sun4i_i2s_runtime_suspend(struct device *dev) 880 { 881 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 882 883 regcache_cache_only(i2s->regmap, true); 884 885 clk_disable_unprepare(i2s->bus_clk); 886 887 return 0; 888 } 889 890 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { 891 .has_reset = false, 892 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 893 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 894 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 895 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 896 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 897 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 898 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 899 .has_slave_select_bit = true, 900 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 901 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 902 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 903 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 904 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 905 }; 906 907 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { 908 .has_reset = true, 909 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 910 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 911 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 912 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 913 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 914 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 915 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 916 .has_slave_select_bit = true, 917 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 918 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 919 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 920 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 921 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 922 }; 923 924 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { 925 .has_reset = true, 926 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 927 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 928 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 929 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 930 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 931 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 932 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 933 .has_slave_select_bit = true, 934 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 935 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 936 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 937 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 938 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 939 }; 940 941 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { 942 .has_reset = true, 943 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 944 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, 945 .mclk_offset = 1, 946 .bclk_offset = 2, 947 .fmt_offset = 3, 948 .has_fmt_set_lrck_period = true, 949 .has_chcfg = true, 950 .has_chsel_tx_chen = true, 951 .has_chsel_offset = true, 952 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 953 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 954 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 955 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 956 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), 957 .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), 958 .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), 959 .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), 960 .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), 961 .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2), 962 }; 963 964 static int sun4i_i2s_init_regmap_fields(struct device *dev, 965 struct sun4i_i2s *i2s) 966 { 967 i2s->field_clkdiv_mclk_en = 968 devm_regmap_field_alloc(dev, i2s->regmap, 969 i2s->variant->field_clkdiv_mclk_en); 970 if (IS_ERR(i2s->field_clkdiv_mclk_en)) 971 return PTR_ERR(i2s->field_clkdiv_mclk_en); 972 973 i2s->field_fmt_wss = 974 devm_regmap_field_alloc(dev, i2s->regmap, 975 i2s->variant->field_fmt_wss); 976 if (IS_ERR(i2s->field_fmt_wss)) 977 return PTR_ERR(i2s->field_fmt_wss); 978 979 i2s->field_fmt_sr = 980 devm_regmap_field_alloc(dev, i2s->regmap, 981 i2s->variant->field_fmt_sr); 982 if (IS_ERR(i2s->field_fmt_sr)) 983 return PTR_ERR(i2s->field_fmt_sr); 984 985 i2s->field_fmt_bclk = 986 devm_regmap_field_alloc(dev, i2s->regmap, 987 i2s->variant->field_fmt_bclk); 988 if (IS_ERR(i2s->field_fmt_bclk)) 989 return PTR_ERR(i2s->field_fmt_bclk); 990 991 i2s->field_fmt_lrclk = 992 devm_regmap_field_alloc(dev, i2s->regmap, 993 i2s->variant->field_fmt_lrclk); 994 if (IS_ERR(i2s->field_fmt_lrclk)) 995 return PTR_ERR(i2s->field_fmt_lrclk); 996 997 i2s->field_fmt_mode = 998 devm_regmap_field_alloc(dev, i2s->regmap, 999 i2s->variant->field_fmt_mode); 1000 if (IS_ERR(i2s->field_fmt_mode)) 1001 return PTR_ERR(i2s->field_fmt_mode); 1002 1003 i2s->field_txchanmap = 1004 devm_regmap_field_alloc(dev, i2s->regmap, 1005 i2s->variant->field_txchanmap); 1006 if (IS_ERR(i2s->field_txchanmap)) 1007 return PTR_ERR(i2s->field_txchanmap); 1008 1009 i2s->field_rxchanmap = 1010 devm_regmap_field_alloc(dev, i2s->regmap, 1011 i2s->variant->field_rxchanmap); 1012 if (IS_ERR(i2s->field_rxchanmap)) 1013 return PTR_ERR(i2s->field_rxchanmap); 1014 1015 i2s->field_txchansel = 1016 devm_regmap_field_alloc(dev, i2s->regmap, 1017 i2s->variant->field_txchansel); 1018 if (IS_ERR(i2s->field_txchansel)) 1019 return PTR_ERR(i2s->field_txchansel); 1020 1021 i2s->field_rxchansel = 1022 devm_regmap_field_alloc(dev, i2s->regmap, 1023 i2s->variant->field_rxchansel); 1024 return PTR_ERR_OR_ZERO(i2s->field_rxchansel); 1025 } 1026 1027 static int sun4i_i2s_probe(struct platform_device *pdev) 1028 { 1029 struct sun4i_i2s *i2s; 1030 struct resource *res; 1031 void __iomem *regs; 1032 int irq, ret; 1033 1034 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 1035 if (!i2s) 1036 return -ENOMEM; 1037 platform_set_drvdata(pdev, i2s); 1038 1039 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1040 regs = devm_ioremap_resource(&pdev->dev, res); 1041 if (IS_ERR(regs)) 1042 return PTR_ERR(regs); 1043 1044 irq = platform_get_irq(pdev, 0); 1045 if (irq < 0) { 1046 dev_err(&pdev->dev, "Can't retrieve our interrupt\n"); 1047 return irq; 1048 } 1049 1050 i2s->variant = of_device_get_match_data(&pdev->dev); 1051 if (!i2s->variant) { 1052 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1053 return -ENODEV; 1054 } 1055 1056 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); 1057 if (IS_ERR(i2s->bus_clk)) { 1058 dev_err(&pdev->dev, "Can't get our bus clock\n"); 1059 return PTR_ERR(i2s->bus_clk); 1060 } 1061 1062 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1063 i2s->variant->sun4i_i2s_regmap); 1064 if (IS_ERR(i2s->regmap)) { 1065 dev_err(&pdev->dev, "Regmap initialisation failed\n"); 1066 return PTR_ERR(i2s->regmap); 1067 } 1068 1069 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); 1070 if (IS_ERR(i2s->mod_clk)) { 1071 dev_err(&pdev->dev, "Can't get our mod clock\n"); 1072 return PTR_ERR(i2s->mod_clk); 1073 } 1074 1075 if (i2s->variant->has_reset) { 1076 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1077 if (IS_ERR(i2s->rst)) { 1078 dev_err(&pdev->dev, "Failed to get reset control\n"); 1079 return PTR_ERR(i2s->rst); 1080 } 1081 } 1082 1083 if (!IS_ERR(i2s->rst)) { 1084 ret = reset_control_deassert(i2s->rst); 1085 if (ret) { 1086 dev_err(&pdev->dev, 1087 "Failed to deassert the reset control\n"); 1088 return -EINVAL; 1089 } 1090 } 1091 1092 i2s->playback_dma_data.addr = res->start + 1093 i2s->variant->reg_offset_txdata; 1094 i2s->playback_dma_data.maxburst = 8; 1095 1096 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; 1097 i2s->capture_dma_data.maxburst = 8; 1098 1099 pm_runtime_enable(&pdev->dev); 1100 if (!pm_runtime_enabled(&pdev->dev)) { 1101 ret = sun4i_i2s_runtime_resume(&pdev->dev); 1102 if (ret) 1103 goto err_pm_disable; 1104 } 1105 1106 ret = devm_snd_soc_register_component(&pdev->dev, 1107 &sun4i_i2s_component, 1108 &sun4i_i2s_dai, 1); 1109 if (ret) { 1110 dev_err(&pdev->dev, "Could not register DAI\n"); 1111 goto err_suspend; 1112 } 1113 1114 ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1115 if (ret) { 1116 dev_err(&pdev->dev, "Could not register PCM\n"); 1117 goto err_suspend; 1118 } 1119 1120 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); 1121 if (ret) { 1122 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); 1123 goto err_suspend; 1124 } 1125 1126 return 0; 1127 1128 err_suspend: 1129 if (!pm_runtime_status_suspended(&pdev->dev)) 1130 sun4i_i2s_runtime_suspend(&pdev->dev); 1131 err_pm_disable: 1132 pm_runtime_disable(&pdev->dev); 1133 if (!IS_ERR(i2s->rst)) 1134 reset_control_assert(i2s->rst); 1135 1136 return ret; 1137 } 1138 1139 static int sun4i_i2s_remove(struct platform_device *pdev) 1140 { 1141 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); 1142 1143 snd_dmaengine_pcm_unregister(&pdev->dev); 1144 1145 pm_runtime_disable(&pdev->dev); 1146 if (!pm_runtime_status_suspended(&pdev->dev)) 1147 sun4i_i2s_runtime_suspend(&pdev->dev); 1148 1149 if (!IS_ERR(i2s->rst)) 1150 reset_control_assert(i2s->rst); 1151 1152 return 0; 1153 } 1154 1155 static const struct of_device_id sun4i_i2s_match[] = { 1156 { 1157 .compatible = "allwinner,sun4i-a10-i2s", 1158 .data = &sun4i_a10_i2s_quirks, 1159 }, 1160 { 1161 .compatible = "allwinner,sun6i-a31-i2s", 1162 .data = &sun6i_a31_i2s_quirks, 1163 }, 1164 { 1165 .compatible = "allwinner,sun8i-a83t-i2s", 1166 .data = &sun8i_a83t_i2s_quirks, 1167 }, 1168 { 1169 .compatible = "allwinner,sun8i-h3-i2s", 1170 .data = &sun8i_h3_i2s_quirks, 1171 }, 1172 {} 1173 }; 1174 MODULE_DEVICE_TABLE(of, sun4i_i2s_match); 1175 1176 static const struct dev_pm_ops sun4i_i2s_pm_ops = { 1177 .runtime_resume = sun4i_i2s_runtime_resume, 1178 .runtime_suspend = sun4i_i2s_runtime_suspend, 1179 }; 1180 1181 static struct platform_driver sun4i_i2s_driver = { 1182 .probe = sun4i_i2s_probe, 1183 .remove = sun4i_i2s_remove, 1184 .driver = { 1185 .name = "sun4i-i2s", 1186 .of_match_table = sun4i_i2s_match, 1187 .pm = &sun4i_i2s_pm_ops, 1188 }, 1189 }; 1190 module_platform_driver(sun4i_i2s_driver); 1191 1192 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>"); 1193 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1194 MODULE_DESCRIPTION("Allwinner A10 I2S driver"); 1195 MODULE_LICENSE("GPL"); 1196