1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Andrea Venturi 4 * Andrea Venturi <be17068@iperbole.bo.it> 5 * 6 * Copyright (C) 2016 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/dmaengine.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dai.h> 23 24 #define SUN4I_I2S_CTRL_REG 0x00 25 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8) 26 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) 27 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5) 28 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5) 29 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5) 30 #define SUN4I_I2S_CTRL_TX_EN BIT(2) 31 #define SUN4I_I2S_CTRL_RX_EN BIT(1) 32 #define SUN4I_I2S_CTRL_GL_EN BIT(0) 33 34 #define SUN4I_I2S_FMT0_REG 0x04 35 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7) 36 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7) 37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7) 38 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6) 39 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6) 40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6) 41 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4) 42 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4) 43 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2) 44 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2) 45 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0) 46 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) 47 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) 48 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) 49 #define SUN4I_I2S_FMT0_POLARITY_INVERTED (1) 50 #define SUN4I_I2S_FMT0_POLARITY_NORMAL (0) 51 52 #define SUN4I_I2S_FMT1_REG 0x08 53 #define SUN4I_I2S_FIFO_TX_REG 0x0c 54 #define SUN4I_I2S_FIFO_RX_REG 0x10 55 56 #define SUN4I_I2S_FIFO_CTRL_REG 0x14 57 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25) 58 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24) 59 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2) 60 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2) 61 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0) 62 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode) 63 64 #define SUN4I_I2S_FIFO_STA_REG 0x18 65 66 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c 67 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7) 68 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3) 69 70 #define SUN4I_I2S_INT_STA_REG 0x20 71 72 #define SUN4I_I2S_CLK_DIV_REG 0x24 73 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) 74 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) 75 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) 76 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) 77 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) 78 79 #define SUN4I_I2S_RX_CNT_REG 0x28 80 #define SUN4I_I2S_TX_CNT_REG 0x2c 81 82 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 83 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) 84 85 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 86 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) 87 88 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 89 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c 90 91 /* Defines required for sun8i-h3 support */ 92 #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) 93 #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) 94 95 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) 96 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) 97 98 #define SUN8I_I2S_INT_STA_REG 0x0c 99 #define SUN8I_I2S_FIFO_TX_REG 0x20 100 101 #define SUN8I_I2S_CHAN_CFG_REG 0x30 102 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) 103 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4) 104 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) 105 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) 106 107 #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 108 #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 109 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12) 110 #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) 111 #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) 112 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) 113 114 #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 115 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 116 117 struct sun4i_i2s; 118 119 /** 120 * struct sun4i_i2s_quirks - Differences between SoC variants. 121 * 122 * @has_reset: SoC needs reset deasserted. 123 * @has_slave_select_bit: SoC has a bit to enable slave mode. 124 * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. 125 * @has_chcfg: tx and rx slot number need to be set. 126 * @has_chsel_tx_chen: SoC requires that the tx channels are enabled. 127 * @has_chsel_offset: SoC uses offset for selecting dai operational mode. 128 * @reg_offset_txdata: offset of the tx fifo. 129 * @sun4i_i2s_regmap: regmap config to use. 130 * @mclk_offset: Value by which mclkdiv needs to be adjusted. 131 * @bclk_offset: Value by which bclkdiv needs to be adjusted. 132 * @field_clkdiv_mclk_en: regmap field to enable mclk output. 133 * @field_fmt_wss: regmap field to set word select size. 134 * @field_fmt_sr: regmap field to set sample resolution. 135 * @field_fmt_bclk: regmap field to set clk polarity. 136 * @field_fmt_lrclk: regmap field to set frame polarity. 137 * @field_fmt_mode: regmap field to set the operational mode. 138 * @field_txchanmap: location of the tx channel mapping register. 139 * @field_rxchanmap: location of the rx channel mapping register. 140 * @field_txchansel: location of the tx channel select bit fields. 141 * @field_rxchansel: location of the rx channel select bit fields. 142 */ 143 struct sun4i_i2s_quirks { 144 bool has_reset; 145 bool has_slave_select_bit; 146 bool has_fmt_set_lrck_period; 147 bool has_chcfg; 148 bool has_chsel_tx_chen; 149 bool has_chsel_offset; 150 unsigned int reg_offset_txdata; /* TX FIFO */ 151 const struct regmap_config *sun4i_i2s_regmap; 152 unsigned int mclk_offset; 153 unsigned int bclk_offset; 154 155 /* Register fields for i2s */ 156 struct reg_field field_clkdiv_mclk_en; 157 struct reg_field field_fmt_wss; 158 struct reg_field field_fmt_sr; 159 struct reg_field field_fmt_bclk; 160 struct reg_field field_fmt_lrclk; 161 struct reg_field field_fmt_mode; 162 struct reg_field field_txchanmap; 163 struct reg_field field_rxchanmap; 164 struct reg_field field_txchansel; 165 struct reg_field field_rxchansel; 166 167 s8 (*get_sr)(const struct sun4i_i2s *, int); 168 s8 (*get_wss)(const struct sun4i_i2s *, int); 169 }; 170 171 struct sun4i_i2s { 172 struct clk *bus_clk; 173 struct clk *mod_clk; 174 struct regmap *regmap; 175 struct reset_control *rst; 176 177 unsigned int mclk_freq; 178 179 struct snd_dmaengine_dai_dma_data capture_dma_data; 180 struct snd_dmaengine_dai_dma_data playback_dma_data; 181 182 /* Register fields for i2s */ 183 struct regmap_field *field_clkdiv_mclk_en; 184 struct regmap_field *field_fmt_wss; 185 struct regmap_field *field_fmt_sr; 186 struct regmap_field *field_fmt_bclk; 187 struct regmap_field *field_fmt_lrclk; 188 struct regmap_field *field_fmt_mode; 189 struct regmap_field *field_txchanmap; 190 struct regmap_field *field_rxchanmap; 191 struct regmap_field *field_txchansel; 192 struct regmap_field *field_rxchansel; 193 194 const struct sun4i_i2s_quirks *variant; 195 }; 196 197 struct sun4i_i2s_clk_div { 198 u8 div; 199 u8 val; 200 }; 201 202 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = { 203 { .div = 2, .val = 0 }, 204 { .div = 4, .val = 1 }, 205 { .div = 6, .val = 2 }, 206 { .div = 8, .val = 3 }, 207 { .div = 12, .val = 4 }, 208 { .div = 16, .val = 5 }, 209 /* TODO - extend divide ratio supported by newer SoCs */ 210 }; 211 212 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { 213 { .div = 1, .val = 0 }, 214 { .div = 2, .val = 1 }, 215 { .div = 4, .val = 2 }, 216 { .div = 6, .val = 3 }, 217 { .div = 8, .val = 4 }, 218 { .div = 12, .val = 5 }, 219 { .div = 16, .val = 6 }, 220 { .div = 24, .val = 7 }, 221 /* TODO - extend divide ratio supported by newer SoCs */ 222 }; 223 224 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, 225 unsigned int oversample_rate, 226 unsigned int word_size) 227 { 228 int div = oversample_rate / word_size / 2; 229 int i; 230 231 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) { 232 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i]; 233 234 if (bdiv->div == div) 235 return bdiv->val; 236 } 237 238 return -EINVAL; 239 } 240 241 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, 242 unsigned int oversample_rate, 243 unsigned int module_rate, 244 unsigned int sampling_rate) 245 { 246 int div = module_rate / sampling_rate / oversample_rate; 247 int i; 248 249 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) { 250 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i]; 251 252 if (mdiv->div == div) 253 return mdiv->val; 254 } 255 256 return -EINVAL; 257 } 258 259 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 }; 260 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) 261 { 262 int i; 263 264 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) 265 if (sun4i_i2s_oversample_rates[i] == oversample) 266 return true; 267 268 return false; 269 } 270 271 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, 272 unsigned int rate, 273 unsigned int word_size) 274 { 275 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 276 unsigned int oversample_rate, clk_rate; 277 int bclk_div, mclk_div; 278 int ret; 279 280 switch (rate) { 281 case 176400: 282 case 88200: 283 case 44100: 284 case 22050: 285 case 11025: 286 clk_rate = 22579200; 287 break; 288 289 case 192000: 290 case 128000: 291 case 96000: 292 case 64000: 293 case 48000: 294 case 32000: 295 case 24000: 296 case 16000: 297 case 12000: 298 case 8000: 299 clk_rate = 24576000; 300 break; 301 302 default: 303 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); 304 return -EINVAL; 305 } 306 307 ret = clk_set_rate(i2s->mod_clk, clk_rate); 308 if (ret) 309 return ret; 310 311 oversample_rate = i2s->mclk_freq / rate; 312 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) { 313 dev_err(dai->dev, "Unsupported oversample rate: %d\n", 314 oversample_rate); 315 return -EINVAL; 316 } 317 318 bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate, 319 word_size); 320 if (bclk_div < 0) { 321 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); 322 return -EINVAL; 323 } 324 325 mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, 326 clk_rate, rate); 327 if (mclk_div < 0) { 328 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); 329 return -EINVAL; 330 } 331 332 /* Adjust the clock division values if needed */ 333 bclk_div += i2s->variant->bclk_offset; 334 mclk_div += i2s->variant->mclk_offset; 335 336 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, 337 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | 338 SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); 339 340 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); 341 342 /* Set sync period */ 343 if (i2s->variant->has_fmt_set_lrck_period) 344 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 345 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, 346 SUN8I_I2S_FMT0_LRCK_PERIOD(32)); 347 348 return 0; 349 } 350 351 static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width) 352 { 353 if (width < 16 || width > 24) 354 return -EINVAL; 355 356 if (width % 4) 357 return -EINVAL; 358 359 return (width - 16) / 4; 360 } 361 362 static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width) 363 { 364 if (width < 16 || width > 32) 365 return -EINVAL; 366 367 if (width % 4) 368 return -EINVAL; 369 370 return (width - 16) / 4; 371 } 372 373 static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width) 374 { 375 if (width % 4) 376 return -EINVAL; 377 378 if (width < 8 || width > 32) 379 return -EINVAL; 380 381 return (width - 8) / 4 + 1; 382 } 383 384 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, 385 struct snd_pcm_hw_params *params, 386 struct snd_soc_dai *dai) 387 { 388 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 389 int sr, wss, channels; 390 u32 width; 391 392 channels = params_channels(params); 393 if (channels != 2) { 394 dev_err(dai->dev, "Unsupported number of channels: %d\n", 395 channels); 396 return -EINVAL; 397 } 398 399 if (i2s->variant->has_chcfg) { 400 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 401 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, 402 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); 403 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 404 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, 405 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); 406 } 407 408 /* Map the channels for playback and capture */ 409 regmap_field_write(i2s->field_txchanmap, 0x76543210); 410 regmap_field_write(i2s->field_rxchanmap, 0x00003210); 411 412 /* Configure the channels */ 413 regmap_field_write(i2s->field_txchansel, 414 SUN4I_I2S_CHAN_SEL(params_channels(params))); 415 416 regmap_field_write(i2s->field_rxchansel, 417 SUN4I_I2S_CHAN_SEL(params_channels(params))); 418 419 if (i2s->variant->has_chsel_tx_chen) 420 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 421 SUN8I_I2S_TX_CHAN_EN_MASK, 422 SUN8I_I2S_TX_CHAN_EN(channels)); 423 424 switch (params_physical_width(params)) { 425 case 16: 426 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 427 break; 428 default: 429 dev_err(dai->dev, "Unsupported physical sample width: %d\n", 430 params_physical_width(params)); 431 return -EINVAL; 432 } 433 i2s->playback_dma_data.addr_width = width; 434 435 sr = i2s->variant->get_sr(i2s, params_width(params)); 436 if (sr < 0) 437 return -EINVAL; 438 439 wss = i2s->variant->get_wss(i2s, params_width(params)); 440 if (wss < 0) 441 return -EINVAL; 442 443 regmap_field_write(i2s->field_fmt_wss, wss); 444 regmap_field_write(i2s->field_fmt_sr, sr); 445 446 return sun4i_i2s_set_clk_rate(dai, params_rate(params), 447 params_width(params)); 448 } 449 450 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 451 { 452 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 453 u32 val; 454 u32 offset = 0; 455 u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; 456 u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; 457 458 /* DAI Mode */ 459 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 460 case SND_SOC_DAIFMT_I2S: 461 val = SUN4I_I2S_FMT0_FMT_I2S; 462 offset = 1; 463 break; 464 case SND_SOC_DAIFMT_LEFT_J: 465 val = SUN4I_I2S_FMT0_FMT_LEFT_J; 466 break; 467 case SND_SOC_DAIFMT_RIGHT_J: 468 val = SUN4I_I2S_FMT0_FMT_RIGHT_J; 469 break; 470 default: 471 dev_err(dai->dev, "Unsupported format: %d\n", 472 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 473 return -EINVAL; 474 } 475 476 if (i2s->variant->has_chsel_offset) { 477 /* 478 * offset being set indicates that we're connected to an i2s 479 * device, however offset is only used on the sun8i block and 480 * i2s shares the same setting with the LJ format. Increment 481 * val so that the bit to value to write is correct. 482 */ 483 if (offset > 0) 484 val++; 485 /* blck offset determines whether i2s or LJ */ 486 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 487 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 488 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 489 490 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, 491 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 492 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 493 } 494 495 regmap_field_write(i2s->field_fmt_mode, val); 496 497 /* DAI clock polarity */ 498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 499 case SND_SOC_DAIFMT_IB_IF: 500 /* Invert both clocks */ 501 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 502 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 503 break; 504 case SND_SOC_DAIFMT_IB_NF: 505 /* Invert bit clock */ 506 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 507 break; 508 case SND_SOC_DAIFMT_NB_IF: 509 /* Invert frame clock */ 510 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; 511 break; 512 case SND_SOC_DAIFMT_NB_NF: 513 break; 514 default: 515 dev_err(dai->dev, "Unsupported clock polarity: %d\n", 516 fmt & SND_SOC_DAIFMT_INV_MASK); 517 return -EINVAL; 518 } 519 520 regmap_field_write(i2s->field_fmt_bclk, bclk_polarity); 521 regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity); 522 523 if (i2s->variant->has_slave_select_bit) { 524 /* DAI clock master masks */ 525 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 526 case SND_SOC_DAIFMT_CBS_CFS: 527 /* BCLK and LRCLK master */ 528 val = SUN4I_I2S_CTRL_MODE_MASTER; 529 break; 530 case SND_SOC_DAIFMT_CBM_CFM: 531 /* BCLK and LRCLK slave */ 532 val = SUN4I_I2S_CTRL_MODE_SLAVE; 533 break; 534 default: 535 dev_err(dai->dev, "Unsupported slave setting: %d\n", 536 fmt & SND_SOC_DAIFMT_MASTER_MASK); 537 return -EINVAL; 538 } 539 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 540 SUN4I_I2S_CTRL_MODE_MASK, 541 val); 542 } else { 543 /* 544 * The newer i2s block does not have a slave select bit, 545 * instead the clk pins are configured as inputs. 546 */ 547 /* DAI clock master masks */ 548 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 549 case SND_SOC_DAIFMT_CBS_CFS: 550 /* BCLK and LRCLK master */ 551 val = SUN8I_I2S_CTRL_BCLK_OUT | 552 SUN8I_I2S_CTRL_LRCK_OUT; 553 break; 554 case SND_SOC_DAIFMT_CBM_CFM: 555 /* BCLK and LRCLK slave */ 556 val = 0; 557 break; 558 default: 559 dev_err(dai->dev, "Unsupported slave setting: %d\n", 560 fmt & SND_SOC_DAIFMT_MASTER_MASK); 561 return -EINVAL; 562 } 563 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 564 SUN8I_I2S_CTRL_BCLK_OUT | 565 SUN8I_I2S_CTRL_LRCK_OUT, 566 val); 567 } 568 569 /* Set significant bits in our FIFOs */ 570 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 571 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | 572 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, 573 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | 574 SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); 575 return 0; 576 } 577 578 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) 579 { 580 /* Flush RX FIFO */ 581 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 582 SUN4I_I2S_FIFO_CTRL_FLUSH_RX, 583 SUN4I_I2S_FIFO_CTRL_FLUSH_RX); 584 585 /* Clear RX counter */ 586 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); 587 588 /* Enable RX Block */ 589 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 590 SUN4I_I2S_CTRL_RX_EN, 591 SUN4I_I2S_CTRL_RX_EN); 592 593 /* Enable RX DRQ */ 594 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 595 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 596 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN); 597 } 598 599 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) 600 { 601 /* Flush TX FIFO */ 602 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 603 SUN4I_I2S_FIFO_CTRL_FLUSH_TX, 604 SUN4I_I2S_FIFO_CTRL_FLUSH_TX); 605 606 /* Clear TX counter */ 607 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); 608 609 /* Enable TX Block */ 610 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 611 SUN4I_I2S_CTRL_TX_EN, 612 SUN4I_I2S_CTRL_TX_EN); 613 614 /* Enable TX DRQ */ 615 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 616 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 617 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN); 618 } 619 620 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s) 621 { 622 /* Disable RX Block */ 623 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 624 SUN4I_I2S_CTRL_RX_EN, 625 0); 626 627 /* Disable RX DRQ */ 628 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 629 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 630 0); 631 } 632 633 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s) 634 { 635 /* Disable TX Block */ 636 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 637 SUN4I_I2S_CTRL_TX_EN, 638 0); 639 640 /* Disable TX DRQ */ 641 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 642 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 643 0); 644 } 645 646 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 647 struct snd_soc_dai *dai) 648 { 649 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 650 651 switch (cmd) { 652 case SNDRV_PCM_TRIGGER_START: 653 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 654 case SNDRV_PCM_TRIGGER_RESUME: 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 656 sun4i_i2s_start_playback(i2s); 657 else 658 sun4i_i2s_start_capture(i2s); 659 break; 660 661 case SNDRV_PCM_TRIGGER_STOP: 662 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 663 case SNDRV_PCM_TRIGGER_SUSPEND: 664 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 665 sun4i_i2s_stop_playback(i2s); 666 else 667 sun4i_i2s_stop_capture(i2s); 668 break; 669 670 default: 671 return -EINVAL; 672 } 673 674 return 0; 675 } 676 677 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 678 unsigned int freq, int dir) 679 { 680 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 681 682 if (clk_id != 0) 683 return -EINVAL; 684 685 i2s->mclk_freq = freq; 686 687 return 0; 688 } 689 690 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { 691 .hw_params = sun4i_i2s_hw_params, 692 .set_fmt = sun4i_i2s_set_fmt, 693 .set_sysclk = sun4i_i2s_set_sysclk, 694 .trigger = sun4i_i2s_trigger, 695 }; 696 697 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) 698 { 699 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 700 701 snd_soc_dai_init_dma_data(dai, 702 &i2s->playback_dma_data, 703 &i2s->capture_dma_data); 704 705 snd_soc_dai_set_drvdata(dai, i2s); 706 707 return 0; 708 } 709 710 static struct snd_soc_dai_driver sun4i_i2s_dai = { 711 .probe = sun4i_i2s_dai_probe, 712 .capture = { 713 .stream_name = "Capture", 714 .channels_min = 2, 715 .channels_max = 2, 716 .rates = SNDRV_PCM_RATE_8000_192000, 717 .formats = SNDRV_PCM_FMTBIT_S16_LE, 718 }, 719 .playback = { 720 .stream_name = "Playback", 721 .channels_min = 2, 722 .channels_max = 2, 723 .rates = SNDRV_PCM_RATE_8000_192000, 724 .formats = SNDRV_PCM_FMTBIT_S16_LE, 725 }, 726 .ops = &sun4i_i2s_dai_ops, 727 .symmetric_rates = 1, 728 }; 729 730 static const struct snd_soc_component_driver sun4i_i2s_component = { 731 .name = "sun4i-dai", 732 }; 733 734 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) 735 { 736 switch (reg) { 737 case SUN4I_I2S_FIFO_TX_REG: 738 return false; 739 740 default: 741 return true; 742 } 743 } 744 745 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg) 746 { 747 switch (reg) { 748 case SUN4I_I2S_FIFO_RX_REG: 749 case SUN4I_I2S_FIFO_STA_REG: 750 return false; 751 752 default: 753 return true; 754 } 755 } 756 757 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) 758 { 759 switch (reg) { 760 case SUN4I_I2S_FIFO_RX_REG: 761 case SUN4I_I2S_INT_STA_REG: 762 case SUN4I_I2S_RX_CNT_REG: 763 case SUN4I_I2S_TX_CNT_REG: 764 return true; 765 766 default: 767 return false; 768 } 769 } 770 771 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) 772 { 773 switch (reg) { 774 case SUN8I_I2S_FIFO_TX_REG: 775 return false; 776 777 default: 778 return true; 779 } 780 } 781 782 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) 783 { 784 if (reg == SUN8I_I2S_INT_STA_REG) 785 return true; 786 if (reg == SUN8I_I2S_FIFO_TX_REG) 787 return false; 788 789 return sun4i_i2s_volatile_reg(dev, reg); 790 } 791 792 static const struct reg_default sun4i_i2s_reg_defaults[] = { 793 { SUN4I_I2S_CTRL_REG, 0x00000000 }, 794 { SUN4I_I2S_FMT0_REG, 0x0000000c }, 795 { SUN4I_I2S_FMT1_REG, 0x00004020 }, 796 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 797 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 798 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 799 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 }, 800 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 }, 801 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 }, 802 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, 803 }; 804 805 static const struct reg_default sun8i_i2s_reg_defaults[] = { 806 { SUN4I_I2S_CTRL_REG, 0x00060000 }, 807 { SUN4I_I2S_FMT0_REG, 0x00000033 }, 808 { SUN4I_I2S_FMT1_REG, 0x00000030 }, 809 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 810 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 811 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 812 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, 813 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, 814 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 }, 815 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, 816 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, 817 }; 818 819 static const struct regmap_config sun4i_i2s_regmap_config = { 820 .reg_bits = 32, 821 .reg_stride = 4, 822 .val_bits = 32, 823 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG, 824 825 .cache_type = REGCACHE_FLAT, 826 .reg_defaults = sun4i_i2s_reg_defaults, 827 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults), 828 .writeable_reg = sun4i_i2s_wr_reg, 829 .readable_reg = sun4i_i2s_rd_reg, 830 .volatile_reg = sun4i_i2s_volatile_reg, 831 }; 832 833 static const struct regmap_config sun8i_i2s_regmap_config = { 834 .reg_bits = 32, 835 .reg_stride = 4, 836 .val_bits = 32, 837 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG, 838 .cache_type = REGCACHE_FLAT, 839 .reg_defaults = sun8i_i2s_reg_defaults, 840 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults), 841 .writeable_reg = sun4i_i2s_wr_reg, 842 .readable_reg = sun8i_i2s_rd_reg, 843 .volatile_reg = sun8i_i2s_volatile_reg, 844 }; 845 846 static int sun4i_i2s_runtime_resume(struct device *dev) 847 { 848 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 849 int ret; 850 851 ret = clk_prepare_enable(i2s->bus_clk); 852 if (ret) { 853 dev_err(dev, "Failed to enable bus clock\n"); 854 return ret; 855 } 856 857 regcache_cache_only(i2s->regmap, false); 858 regcache_mark_dirty(i2s->regmap); 859 860 ret = regcache_sync(i2s->regmap); 861 if (ret) { 862 dev_err(dev, "Failed to sync regmap cache\n"); 863 goto err_disable_clk; 864 } 865 866 /* Enable the whole hardware block */ 867 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 868 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN); 869 870 /* Enable the first output line */ 871 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 872 SUN4I_I2S_CTRL_SDO_EN_MASK, 873 SUN4I_I2S_CTRL_SDO_EN(0)); 874 875 ret = clk_prepare_enable(i2s->mod_clk); 876 if (ret) { 877 dev_err(dev, "Failed to enable module clock\n"); 878 goto err_disable_clk; 879 } 880 881 return 0; 882 883 err_disable_clk: 884 clk_disable_unprepare(i2s->bus_clk); 885 return ret; 886 } 887 888 static int sun4i_i2s_runtime_suspend(struct device *dev) 889 { 890 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 891 892 clk_disable_unprepare(i2s->mod_clk); 893 894 /* Disable our output lines */ 895 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 896 SUN4I_I2S_CTRL_SDO_EN_MASK, 0); 897 898 /* Disable the whole hardware block */ 899 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 900 SUN4I_I2S_CTRL_GL_EN, 0); 901 902 regcache_cache_only(i2s->regmap, true); 903 904 clk_disable_unprepare(i2s->bus_clk); 905 906 return 0; 907 } 908 909 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { 910 .has_reset = false, 911 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 912 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 913 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 914 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 915 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 916 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 917 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 918 .has_slave_select_bit = true, 919 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 920 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 921 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 922 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 923 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 924 .get_sr = sun4i_i2s_get_sr, 925 .get_wss = sun4i_i2s_get_wss, 926 }; 927 928 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { 929 .has_reset = true, 930 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 931 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 932 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 933 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 934 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 935 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 936 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 937 .has_slave_select_bit = true, 938 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 939 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 940 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 941 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 942 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 943 .get_sr = sun4i_i2s_get_sr, 944 .get_wss = sun4i_i2s_get_wss, 945 }; 946 947 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { 948 .has_reset = true, 949 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 950 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 951 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 952 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 953 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 954 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 955 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 956 .has_slave_select_bit = true, 957 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 958 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 959 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 960 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 961 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 962 .get_sr = sun8i_i2s_get_sr_wss, 963 .get_wss = sun8i_i2s_get_sr_wss, 964 }; 965 966 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { 967 .has_reset = true, 968 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 969 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, 970 .mclk_offset = 1, 971 .bclk_offset = 2, 972 .has_fmt_set_lrck_period = true, 973 .has_chcfg = true, 974 .has_chsel_tx_chen = true, 975 .has_chsel_offset = true, 976 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 977 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 978 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 979 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 980 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), 981 .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), 982 .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), 983 .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), 984 .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), 985 .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2), 986 .get_sr = sun8i_i2s_get_sr_wss, 987 .get_wss = sun8i_i2s_get_sr_wss, 988 }; 989 990 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { 991 .has_reset = true, 992 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 993 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 994 .has_slave_select_bit = true, 995 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 996 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 997 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 998 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), 999 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), 1000 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), 1001 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), 1002 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), 1003 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), 1004 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), 1005 .get_sr = sun8i_i2s_get_sr_wss, 1006 .get_wss = sun8i_i2s_get_sr_wss, 1007 }; 1008 1009 static int sun4i_i2s_init_regmap_fields(struct device *dev, 1010 struct sun4i_i2s *i2s) 1011 { 1012 i2s->field_clkdiv_mclk_en = 1013 devm_regmap_field_alloc(dev, i2s->regmap, 1014 i2s->variant->field_clkdiv_mclk_en); 1015 if (IS_ERR(i2s->field_clkdiv_mclk_en)) 1016 return PTR_ERR(i2s->field_clkdiv_mclk_en); 1017 1018 i2s->field_fmt_wss = 1019 devm_regmap_field_alloc(dev, i2s->regmap, 1020 i2s->variant->field_fmt_wss); 1021 if (IS_ERR(i2s->field_fmt_wss)) 1022 return PTR_ERR(i2s->field_fmt_wss); 1023 1024 i2s->field_fmt_sr = 1025 devm_regmap_field_alloc(dev, i2s->regmap, 1026 i2s->variant->field_fmt_sr); 1027 if (IS_ERR(i2s->field_fmt_sr)) 1028 return PTR_ERR(i2s->field_fmt_sr); 1029 1030 i2s->field_fmt_bclk = 1031 devm_regmap_field_alloc(dev, i2s->regmap, 1032 i2s->variant->field_fmt_bclk); 1033 if (IS_ERR(i2s->field_fmt_bclk)) 1034 return PTR_ERR(i2s->field_fmt_bclk); 1035 1036 i2s->field_fmt_lrclk = 1037 devm_regmap_field_alloc(dev, i2s->regmap, 1038 i2s->variant->field_fmt_lrclk); 1039 if (IS_ERR(i2s->field_fmt_lrclk)) 1040 return PTR_ERR(i2s->field_fmt_lrclk); 1041 1042 i2s->field_fmt_mode = 1043 devm_regmap_field_alloc(dev, i2s->regmap, 1044 i2s->variant->field_fmt_mode); 1045 if (IS_ERR(i2s->field_fmt_mode)) 1046 return PTR_ERR(i2s->field_fmt_mode); 1047 1048 i2s->field_txchanmap = 1049 devm_regmap_field_alloc(dev, i2s->regmap, 1050 i2s->variant->field_txchanmap); 1051 if (IS_ERR(i2s->field_txchanmap)) 1052 return PTR_ERR(i2s->field_txchanmap); 1053 1054 i2s->field_rxchanmap = 1055 devm_regmap_field_alloc(dev, i2s->regmap, 1056 i2s->variant->field_rxchanmap); 1057 if (IS_ERR(i2s->field_rxchanmap)) 1058 return PTR_ERR(i2s->field_rxchanmap); 1059 1060 i2s->field_txchansel = 1061 devm_regmap_field_alloc(dev, i2s->regmap, 1062 i2s->variant->field_txchansel); 1063 if (IS_ERR(i2s->field_txchansel)) 1064 return PTR_ERR(i2s->field_txchansel); 1065 1066 i2s->field_rxchansel = 1067 devm_regmap_field_alloc(dev, i2s->regmap, 1068 i2s->variant->field_rxchansel); 1069 return PTR_ERR_OR_ZERO(i2s->field_rxchansel); 1070 } 1071 1072 static int sun4i_i2s_probe(struct platform_device *pdev) 1073 { 1074 struct sun4i_i2s *i2s; 1075 struct resource *res; 1076 void __iomem *regs; 1077 int irq, ret; 1078 1079 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 1080 if (!i2s) 1081 return -ENOMEM; 1082 platform_set_drvdata(pdev, i2s); 1083 1084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1085 regs = devm_ioremap_resource(&pdev->dev, res); 1086 if (IS_ERR(regs)) 1087 return PTR_ERR(regs); 1088 1089 irq = platform_get_irq(pdev, 0); 1090 if (irq < 0) { 1091 dev_err(&pdev->dev, "Can't retrieve our interrupt\n"); 1092 return irq; 1093 } 1094 1095 i2s->variant = of_device_get_match_data(&pdev->dev); 1096 if (!i2s->variant) { 1097 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1098 return -ENODEV; 1099 } 1100 1101 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); 1102 if (IS_ERR(i2s->bus_clk)) { 1103 dev_err(&pdev->dev, "Can't get our bus clock\n"); 1104 return PTR_ERR(i2s->bus_clk); 1105 } 1106 1107 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1108 i2s->variant->sun4i_i2s_regmap); 1109 if (IS_ERR(i2s->regmap)) { 1110 dev_err(&pdev->dev, "Regmap initialisation failed\n"); 1111 return PTR_ERR(i2s->regmap); 1112 } 1113 1114 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); 1115 if (IS_ERR(i2s->mod_clk)) { 1116 dev_err(&pdev->dev, "Can't get our mod clock\n"); 1117 return PTR_ERR(i2s->mod_clk); 1118 } 1119 1120 if (i2s->variant->has_reset) { 1121 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1122 if (IS_ERR(i2s->rst)) { 1123 dev_err(&pdev->dev, "Failed to get reset control\n"); 1124 return PTR_ERR(i2s->rst); 1125 } 1126 } 1127 1128 if (!IS_ERR(i2s->rst)) { 1129 ret = reset_control_deassert(i2s->rst); 1130 if (ret) { 1131 dev_err(&pdev->dev, 1132 "Failed to deassert the reset control\n"); 1133 return -EINVAL; 1134 } 1135 } 1136 1137 i2s->playback_dma_data.addr = res->start + 1138 i2s->variant->reg_offset_txdata; 1139 i2s->playback_dma_data.maxburst = 8; 1140 1141 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; 1142 i2s->capture_dma_data.maxburst = 8; 1143 1144 pm_runtime_enable(&pdev->dev); 1145 if (!pm_runtime_enabled(&pdev->dev)) { 1146 ret = sun4i_i2s_runtime_resume(&pdev->dev); 1147 if (ret) 1148 goto err_pm_disable; 1149 } 1150 1151 ret = devm_snd_soc_register_component(&pdev->dev, 1152 &sun4i_i2s_component, 1153 &sun4i_i2s_dai, 1); 1154 if (ret) { 1155 dev_err(&pdev->dev, "Could not register DAI\n"); 1156 goto err_suspend; 1157 } 1158 1159 ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1160 if (ret) { 1161 dev_err(&pdev->dev, "Could not register PCM\n"); 1162 goto err_suspend; 1163 } 1164 1165 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); 1166 if (ret) { 1167 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); 1168 goto err_suspend; 1169 } 1170 1171 return 0; 1172 1173 err_suspend: 1174 if (!pm_runtime_status_suspended(&pdev->dev)) 1175 sun4i_i2s_runtime_suspend(&pdev->dev); 1176 err_pm_disable: 1177 pm_runtime_disable(&pdev->dev); 1178 if (!IS_ERR(i2s->rst)) 1179 reset_control_assert(i2s->rst); 1180 1181 return ret; 1182 } 1183 1184 static int sun4i_i2s_remove(struct platform_device *pdev) 1185 { 1186 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); 1187 1188 snd_dmaengine_pcm_unregister(&pdev->dev); 1189 1190 pm_runtime_disable(&pdev->dev); 1191 if (!pm_runtime_status_suspended(&pdev->dev)) 1192 sun4i_i2s_runtime_suspend(&pdev->dev); 1193 1194 if (!IS_ERR(i2s->rst)) 1195 reset_control_assert(i2s->rst); 1196 1197 return 0; 1198 } 1199 1200 static const struct of_device_id sun4i_i2s_match[] = { 1201 { 1202 .compatible = "allwinner,sun4i-a10-i2s", 1203 .data = &sun4i_a10_i2s_quirks, 1204 }, 1205 { 1206 .compatible = "allwinner,sun6i-a31-i2s", 1207 .data = &sun6i_a31_i2s_quirks, 1208 }, 1209 { 1210 .compatible = "allwinner,sun8i-a83t-i2s", 1211 .data = &sun8i_a83t_i2s_quirks, 1212 }, 1213 { 1214 .compatible = "allwinner,sun8i-h3-i2s", 1215 .data = &sun8i_h3_i2s_quirks, 1216 }, 1217 { 1218 .compatible = "allwinner,sun50i-a64-codec-i2s", 1219 .data = &sun50i_a64_codec_i2s_quirks, 1220 }, 1221 {} 1222 }; 1223 MODULE_DEVICE_TABLE(of, sun4i_i2s_match); 1224 1225 static const struct dev_pm_ops sun4i_i2s_pm_ops = { 1226 .runtime_resume = sun4i_i2s_runtime_resume, 1227 .runtime_suspend = sun4i_i2s_runtime_suspend, 1228 }; 1229 1230 static struct platform_driver sun4i_i2s_driver = { 1231 .probe = sun4i_i2s_probe, 1232 .remove = sun4i_i2s_remove, 1233 .driver = { 1234 .name = "sun4i-i2s", 1235 .of_match_table = sun4i_i2s_match, 1236 .pm = &sun4i_i2s_pm_ops, 1237 }, 1238 }; 1239 module_platform_driver(sun4i_i2s_driver); 1240 1241 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>"); 1242 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1243 MODULE_DESCRIPTION("Allwinner A10 I2S driver"); 1244 MODULE_LICENSE("GPL"); 1245