1 /* 2 * Copyright 2014 Emilio López <emilio@elopez.com.ar> 3 * Copyright 2014 Jon Smirl <jonsmirl@gmail.com> 4 * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com> 5 * Copyright 2015 Adam Sampson <ats@offog.org> 6 * Copyright 2016 Chen-Yu Tsai <wens@csie.org> 7 * 8 * Based on the Allwinner SDK driver, released under the GPL. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/clk.h> 32 #include <linux/regmap.h> 33 #include <linux/reset.h> 34 #include <linux/gpio/consumer.h> 35 36 #include <sound/core.h> 37 #include <sound/pcm.h> 38 #include <sound/pcm_params.h> 39 #include <sound/soc.h> 40 #include <sound/tlv.h> 41 #include <sound/initval.h> 42 #include <sound/dmaengine_pcm.h> 43 44 /* Codec DAC digital controls and FIFO registers */ 45 #define SUN4I_CODEC_DAC_DPC (0x00) 46 #define SUN4I_CODEC_DAC_DPC_EN_DA (31) 47 #define SUN4I_CODEC_DAC_DPC_DVOL (12) 48 #define SUN4I_CODEC_DAC_FIFOC (0x04) 49 #define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29) 50 #define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28) 51 #define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26) 52 #define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24) 53 #define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21) 54 #define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8) 55 #define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6) 56 #define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5) 57 #define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4) 58 #define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0) 59 #define SUN4I_CODEC_DAC_FIFOS (0x08) 60 #define SUN4I_CODEC_DAC_TXDATA (0x0c) 61 62 /* Codec DAC side analog signal controls */ 63 #define SUN4I_CODEC_DAC_ACTL (0x10) 64 #define SUN4I_CODEC_DAC_ACTL_DACAENR (31) 65 #define SUN4I_CODEC_DAC_ACTL_DACAENL (30) 66 #define SUN4I_CODEC_DAC_ACTL_MIXEN (29) 67 #define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15) 68 #define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14) 69 #define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13) 70 #define SUN4I_CODEC_DAC_ACTL_DACPAS (8) 71 #define SUN4I_CODEC_DAC_ACTL_MIXPAS (7) 72 #define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6) 73 #define SUN4I_CODEC_DAC_ACTL_PA_VOL (0) 74 #define SUN4I_CODEC_DAC_TUNE (0x14) 75 #define SUN4I_CODEC_DAC_DEBUG (0x18) 76 77 /* Codec ADC digital controls and FIFO registers */ 78 #define SUN4I_CODEC_ADC_FIFOC (0x1c) 79 #define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29) 80 #define SUN4I_CODEC_ADC_FIFOC_EN_AD (28) 81 #define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24) 82 #define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8) 83 #define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7) 84 #define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6) 85 #define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4) 86 #define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0) 87 #define SUN4I_CODEC_ADC_FIFOS (0x20) 88 #define SUN4I_CODEC_ADC_RXDATA (0x24) 89 90 /* Codec ADC side analog signal controls */ 91 #define SUN4I_CODEC_ADC_ACTL (0x28) 92 #define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31) 93 #define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30) 94 #define SUN4I_CODEC_ADC_ACTL_PREG1EN (29) 95 #define SUN4I_CODEC_ADC_ACTL_PREG2EN (28) 96 #define SUN4I_CODEC_ADC_ACTL_VMICEN (27) 97 #define SUN4I_CODEC_ADC_ACTL_VADCG (20) 98 #define SUN4I_CODEC_ADC_ACTL_ADCIS (17) 99 #define SUN4I_CODEC_ADC_ACTL_PA_EN (4) 100 #define SUN4I_CODEC_ADC_ACTL_DDE (3) 101 #define SUN4I_CODEC_ADC_DEBUG (0x2c) 102 103 /* FIFO counters */ 104 #define SUN4I_CODEC_DAC_TXCNT (0x30) 105 #define SUN4I_CODEC_ADC_RXCNT (0x34) 106 107 /* Calibration register (sun7i only) */ 108 #define SUN7I_CODEC_AC_DAC_CAL (0x38) 109 110 /* Microphone controls (sun7i only) */ 111 #define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c) 112 113 /* 114 * sun6i specific registers 115 * 116 * sun6i shares the same digital control and FIFO registers as sun4i, 117 * but only the DAC digital controls are at the same offset. The others 118 * have been moved around to accommodate extra analog controls. 119 */ 120 121 /* Codec DAC digital controls and FIFO registers */ 122 #define SUN6I_CODEC_ADC_FIFOC (0x10) 123 #define SUN6I_CODEC_ADC_FIFOC_EN_AD (28) 124 #define SUN6I_CODEC_ADC_FIFOS (0x14) 125 #define SUN6I_CODEC_ADC_RXDATA (0x18) 126 127 /* Output mixer and gain controls */ 128 #define SUN6I_CODEC_OM_DACA_CTRL (0x20) 129 #define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31) 130 #define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30) 131 #define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29) 132 #define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28) 133 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23) 134 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22) 135 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21) 136 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20) 137 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19) 138 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18) 139 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17) 140 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16) 141 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15) 142 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14) 143 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13) 144 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12) 145 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11) 146 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10) 147 #define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9) 148 #define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8) 149 #define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7) 150 #define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6) 151 #define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0) 152 #define SUN6I_CODEC_OM_PA_CTRL (0x24) 153 #define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31) 154 #define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29) 155 #define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28) 156 #define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15) 157 #define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12) 158 #define SUN6I_CODEC_OM_PA_CTRL_LINEING (9) 159 #define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6) 160 #define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3) 161 #define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0) 162 163 /* Microphone, line out and phone out controls */ 164 #define SUN6I_CODEC_MIC_CTRL (0x28) 165 #define SUN6I_CODEC_MIC_CTRL_HBIASEN (31) 166 #define SUN6I_CODEC_MIC_CTRL_MBIASEN (30) 167 #define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28) 168 #define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25) 169 #define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24) 170 #define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21) 171 #define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20) 172 #define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19) 173 #define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18) 174 #define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17) 175 #define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16) 176 #define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11) 177 #define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8) 178 179 /* ADC mixer controls */ 180 #define SUN6I_CODEC_ADC_ACTL (0x2c) 181 #define SUN6I_CODEC_ADC_ACTL_ADCREN (31) 182 #define SUN6I_CODEC_ADC_ACTL_ADCLEN (30) 183 #define SUN6I_CODEC_ADC_ACTL_ADCRG (27) 184 #define SUN6I_CODEC_ADC_ACTL_ADCLG (24) 185 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13) 186 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12) 187 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11) 188 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10) 189 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9) 190 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8) 191 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7) 192 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6) 193 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5) 194 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4) 195 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3) 196 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2) 197 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1) 198 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0) 199 200 /* Analog performance tuning controls */ 201 #define SUN6I_CODEC_ADDA_TUNE (0x30) 202 203 /* Calibration controls */ 204 #define SUN6I_CODEC_CALIBRATION (0x34) 205 206 /* FIFO counters */ 207 #define SUN6I_CODEC_DAC_TXCNT (0x40) 208 #define SUN6I_CODEC_ADC_RXCNT (0x44) 209 210 /* headset jack detection and button support registers */ 211 #define SUN6I_CODEC_HMIC_CTL (0x50) 212 #define SUN6I_CODEC_HMIC_DATA (0x54) 213 214 /* TODO sun6i DAP (Digital Audio Processing) bits */ 215 216 /* FIFO counters moved on A23 */ 217 #define SUN8I_A23_CODEC_DAC_TXCNT (0x1c) 218 #define SUN8I_A23_CODEC_ADC_RXCNT (0x20) 219 220 /* TX FIFO moved on H3 */ 221 #define SUN8I_H3_CODEC_DAC_TXDATA (0x20) 222 #define SUN8I_H3_CODEC_DAC_DBG (0x48) 223 #define SUN8I_H3_CODEC_ADC_DBG (0x4c) 224 225 /* TODO H3 DAP (Digital Audio Processing) bits */ 226 227 struct sun4i_codec { 228 struct device *dev; 229 struct regmap *regmap; 230 struct clk *clk_apb; 231 struct clk *clk_module; 232 struct reset_control *rst; 233 struct gpio_desc *gpio_pa; 234 235 /* ADC_FIFOC register is at different offset on different SoCs */ 236 struct regmap_field *reg_adc_fifoc; 237 238 struct snd_dmaengine_dai_dma_data capture_dma_data; 239 struct snd_dmaengine_dai_dma_data playback_dma_data; 240 }; 241 242 static void sun4i_codec_start_playback(struct sun4i_codec *scodec) 243 { 244 /* Flush TX FIFO */ 245 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 246 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH), 247 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); 248 249 /* Enable DAC DRQ */ 250 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 251 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN), 252 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); 253 } 254 255 static void sun4i_codec_stop_playback(struct sun4i_codec *scodec) 256 { 257 /* Disable DAC DRQ */ 258 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 259 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN), 260 0); 261 } 262 263 static void sun4i_codec_start_capture(struct sun4i_codec *scodec) 264 { 265 /* Enable ADC DRQ */ 266 regmap_field_update_bits(scodec->reg_adc_fifoc, 267 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 268 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); 269 } 270 271 static void sun4i_codec_stop_capture(struct sun4i_codec *scodec) 272 { 273 /* Disable ADC DRQ */ 274 regmap_field_update_bits(scodec->reg_adc_fifoc, 275 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 0); 276 } 277 278 static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd, 279 struct snd_soc_dai *dai) 280 { 281 struct snd_soc_pcm_runtime *rtd = substream->private_data; 282 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 283 284 switch (cmd) { 285 case SNDRV_PCM_TRIGGER_START: 286 case SNDRV_PCM_TRIGGER_RESUME: 287 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 288 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 289 sun4i_codec_start_playback(scodec); 290 else 291 sun4i_codec_start_capture(scodec); 292 break; 293 294 case SNDRV_PCM_TRIGGER_STOP: 295 case SNDRV_PCM_TRIGGER_SUSPEND: 296 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 297 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 298 sun4i_codec_stop_playback(scodec); 299 else 300 sun4i_codec_stop_capture(scodec); 301 break; 302 303 default: 304 return -EINVAL; 305 } 306 307 return 0; 308 } 309 310 static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream, 311 struct snd_soc_dai *dai) 312 { 313 struct snd_soc_pcm_runtime *rtd = substream->private_data; 314 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 315 316 317 /* Flush RX FIFO */ 318 regmap_field_update_bits(scodec->reg_adc_fifoc, 319 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH), 320 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH)); 321 322 323 /* Set RX FIFO trigger level */ 324 regmap_field_update_bits(scodec->reg_adc_fifoc, 325 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, 326 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL); 327 328 /* 329 * FIXME: Undocumented in the datasheet, but 330 * Allwinner's code mentions that it is related 331 * related to microphone gain 332 */ 333 if (of_device_is_compatible(scodec->dev->of_node, 334 "allwinner,sun4i-a10-codec") || 335 of_device_is_compatible(scodec->dev->of_node, 336 "allwinner,sun7i-a20-codec")) { 337 regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL, 338 0x3 << 25, 339 0x1 << 25); 340 } 341 342 if (of_device_is_compatible(scodec->dev->of_node, 343 "allwinner,sun7i-a20-codec")) 344 /* FIXME: Undocumented bits */ 345 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE, 346 0x3 << 8, 347 0x1 << 8); 348 349 return 0; 350 } 351 352 static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream, 353 struct snd_soc_dai *dai) 354 { 355 struct snd_soc_pcm_runtime *rtd = substream->private_data; 356 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 357 u32 val; 358 359 /* Flush the TX FIFO */ 360 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 361 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH), 362 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); 363 364 /* Set TX FIFO Empty Trigger Level */ 365 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 366 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL, 367 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL); 368 369 if (substream->runtime->rate > 32000) 370 /* Use 64 bits FIR filter */ 371 val = 0; 372 else 373 /* Use 32 bits FIR filter */ 374 val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); 375 376 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 377 BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), 378 val); 379 380 /* Send zeros when we have an underrun */ 381 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 382 BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT), 383 0); 384 385 return 0; 386 }; 387 388 static int sun4i_codec_prepare(struct snd_pcm_substream *substream, 389 struct snd_soc_dai *dai) 390 { 391 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 392 return sun4i_codec_prepare_playback(substream, dai); 393 394 return sun4i_codec_prepare_capture(substream, dai); 395 } 396 397 static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params) 398 { 399 unsigned int rate = params_rate(params); 400 401 switch (rate) { 402 case 176400: 403 case 88200: 404 case 44100: 405 case 33075: 406 case 22050: 407 case 14700: 408 case 11025: 409 case 7350: 410 return 22579200; 411 412 case 192000: 413 case 96000: 414 case 48000: 415 case 32000: 416 case 24000: 417 case 16000: 418 case 12000: 419 case 8000: 420 return 24576000; 421 422 default: 423 return 0; 424 } 425 } 426 427 static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params) 428 { 429 unsigned int rate = params_rate(params); 430 431 switch (rate) { 432 case 192000: 433 case 176400: 434 return 6; 435 436 case 96000: 437 case 88200: 438 return 7; 439 440 case 48000: 441 case 44100: 442 return 0; 443 444 case 32000: 445 case 33075: 446 return 1; 447 448 case 24000: 449 case 22050: 450 return 2; 451 452 case 16000: 453 case 14700: 454 return 3; 455 456 case 12000: 457 case 11025: 458 return 4; 459 460 case 8000: 461 case 7350: 462 return 5; 463 464 default: 465 return -EINVAL; 466 } 467 } 468 469 static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec, 470 struct snd_pcm_hw_params *params, 471 unsigned int hwrate) 472 { 473 /* Set ADC sample rate */ 474 regmap_field_update_bits(scodec->reg_adc_fifoc, 475 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS, 476 hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS); 477 478 /* Set the number of channels we want to use */ 479 if (params_channels(params) == 1) 480 regmap_field_update_bits(scodec->reg_adc_fifoc, 481 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), 482 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); 483 else 484 regmap_field_update_bits(scodec->reg_adc_fifoc, 485 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), 486 0); 487 488 /* Set the number of sample bits to either 16 or 24 bits */ 489 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { 490 regmap_field_update_bits(scodec->reg_adc_fifoc, 491 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS), 492 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); 493 494 regmap_field_update_bits(scodec->reg_adc_fifoc, 495 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE), 496 0); 497 498 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 499 } else { 500 regmap_field_update_bits(scodec->reg_adc_fifoc, 501 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS), 502 0); 503 504 /* Fill most significant bits with valid data MSB */ 505 regmap_field_update_bits(scodec->reg_adc_fifoc, 506 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE), 507 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); 508 509 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 510 } 511 512 return 0; 513 } 514 515 static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec, 516 struct snd_pcm_hw_params *params, 517 unsigned int hwrate) 518 { 519 u32 val; 520 521 /* Set DAC sample rate */ 522 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 523 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS, 524 hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS); 525 526 /* Set the number of channels we want to use */ 527 if (params_channels(params) == 1) 528 val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN); 529 else 530 val = 0; 531 532 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 533 BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), 534 val); 535 536 /* Set the number of sample bits to either 16 or 24 bits */ 537 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { 538 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 539 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS), 540 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); 541 542 /* Set TX FIFO mode to padding the LSBs with 0 */ 543 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 544 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE), 545 0); 546 547 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 548 } else { 549 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 550 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS), 551 0); 552 553 /* Set TX FIFO mode to repeat the MSB */ 554 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 555 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE), 556 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); 557 558 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 559 } 560 561 return 0; 562 } 563 564 static int sun4i_codec_hw_params(struct snd_pcm_substream *substream, 565 struct snd_pcm_hw_params *params, 566 struct snd_soc_dai *dai) 567 { 568 struct snd_soc_pcm_runtime *rtd = substream->private_data; 569 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 570 unsigned long clk_freq; 571 int ret, hwrate; 572 573 clk_freq = sun4i_codec_get_mod_freq(params); 574 if (!clk_freq) 575 return -EINVAL; 576 577 ret = clk_set_rate(scodec->clk_module, clk_freq); 578 if (ret) 579 return ret; 580 581 hwrate = sun4i_codec_get_hw_rate(params); 582 if (hwrate < 0) 583 return hwrate; 584 585 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 586 return sun4i_codec_hw_params_playback(scodec, params, 587 hwrate); 588 589 return sun4i_codec_hw_params_capture(scodec, params, 590 hwrate); 591 } 592 593 594 static unsigned int sun4i_codec_src_rates[] = { 595 8000, 11025, 12000, 16000, 22050, 24000, 32000, 596 44100, 48000, 96000, 192000 597 }; 598 599 600 static struct snd_pcm_hw_constraint_list sun4i_codec_constraints = { 601 .count = ARRAY_SIZE(sun4i_codec_src_rates), 602 .list = sun4i_codec_src_rates, 603 }; 604 605 606 static int sun4i_codec_startup(struct snd_pcm_substream *substream, 607 struct snd_soc_dai *dai) 608 { 609 struct snd_soc_pcm_runtime *rtd = substream->private_data; 610 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 611 612 snd_pcm_hw_constraint_list(substream->runtime, 0, 613 SNDRV_PCM_HW_PARAM_RATE, &sun4i_codec_constraints); 614 615 /* 616 * Stop issuing DRQ when we have room for less than 16 samples 617 * in our TX FIFO 618 */ 619 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 620 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT, 621 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT); 622 623 return clk_prepare_enable(scodec->clk_module); 624 } 625 626 static void sun4i_codec_shutdown(struct snd_pcm_substream *substream, 627 struct snd_soc_dai *dai) 628 { 629 struct snd_soc_pcm_runtime *rtd = substream->private_data; 630 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 631 632 clk_disable_unprepare(scodec->clk_module); 633 } 634 635 static const struct snd_soc_dai_ops sun4i_codec_dai_ops = { 636 .startup = sun4i_codec_startup, 637 .shutdown = sun4i_codec_shutdown, 638 .trigger = sun4i_codec_trigger, 639 .hw_params = sun4i_codec_hw_params, 640 .prepare = sun4i_codec_prepare, 641 }; 642 643 static struct snd_soc_dai_driver sun4i_codec_dai = { 644 .name = "Codec", 645 .ops = &sun4i_codec_dai_ops, 646 .playback = { 647 .stream_name = "Codec Playback", 648 .channels_min = 1, 649 .channels_max = 2, 650 .rate_min = 8000, 651 .rate_max = 192000, 652 .rates = SNDRV_PCM_RATE_CONTINUOUS, 653 .formats = SNDRV_PCM_FMTBIT_S16_LE | 654 SNDRV_PCM_FMTBIT_S32_LE, 655 .sig_bits = 24, 656 }, 657 .capture = { 658 .stream_name = "Codec Capture", 659 .channels_min = 1, 660 .channels_max = 2, 661 .rate_min = 8000, 662 .rate_max = 48000, 663 .rates = SNDRV_PCM_RATE_CONTINUOUS, 664 .formats = SNDRV_PCM_FMTBIT_S16_LE | 665 SNDRV_PCM_FMTBIT_S32_LE, 666 .sig_bits = 24, 667 }, 668 }; 669 670 /*** sun4i Codec ***/ 671 static const struct snd_kcontrol_new sun4i_codec_pa_mute = 672 SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL, 673 SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0); 674 675 static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1); 676 677 static const struct snd_kcontrol_new sun4i_codec_controls[] = { 678 SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL, 679 SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0, 680 sun4i_codec_pa_volume_scale), 681 }; 682 683 static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[] = { 684 SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 685 SUN4I_CODEC_DAC_ACTL_LDACLMIXS, 1, 0), 686 }; 687 688 static const struct snd_kcontrol_new sun4i_codec_right_mixer_controls[] = { 689 SOC_DAPM_SINGLE("Right DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 690 SUN4I_CODEC_DAC_ACTL_RDACRMIXS, 1, 0), 691 SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 692 SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0), 693 }; 694 695 static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = { 696 SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 697 SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0), 698 SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL, 699 SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0), 700 }; 701 702 static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = { 703 /* Digital parts of the ADCs */ 704 SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC, 705 SUN4I_CODEC_ADC_FIFOC_EN_AD, 0, 706 NULL, 0), 707 708 /* Digital parts of the DACs */ 709 SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC, 710 SUN4I_CODEC_DAC_DPC_EN_DA, 0, 711 NULL, 0), 712 713 /* Analog parts of the ADCs */ 714 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL, 715 SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0), 716 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL, 717 SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0), 718 719 /* Analog parts of the DACs */ 720 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL, 721 SUN4I_CODEC_DAC_ACTL_DACAENL, 0), 722 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL, 723 SUN4I_CODEC_DAC_ACTL_DACAENR, 0), 724 725 /* Mixers */ 726 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, 727 sun4i_codec_left_mixer_controls, 728 ARRAY_SIZE(sun4i_codec_left_mixer_controls)), 729 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, 730 sun4i_codec_right_mixer_controls, 731 ARRAY_SIZE(sun4i_codec_right_mixer_controls)), 732 733 /* Global Mixer Enable */ 734 SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL, 735 SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0), 736 737 /* VMIC */ 738 SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL, 739 SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0), 740 741 /* Mic Pre-Amplifiers */ 742 SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL, 743 SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0), 744 745 /* Power Amplifier */ 746 SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL, 747 SUN4I_CODEC_ADC_ACTL_PA_EN, 0, 748 sun4i_codec_pa_mixer_controls, 749 ARRAY_SIZE(sun4i_codec_pa_mixer_controls)), 750 SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0, 751 &sun4i_codec_pa_mute), 752 753 SND_SOC_DAPM_INPUT("Mic1"), 754 755 SND_SOC_DAPM_OUTPUT("HP Right"), 756 SND_SOC_DAPM_OUTPUT("HP Left"), 757 }; 758 759 static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = { 760 /* Left ADC / DAC Routes */ 761 { "Left ADC", NULL, "ADC" }, 762 { "Left DAC", NULL, "DAC" }, 763 764 /* Right ADC / DAC Routes */ 765 { "Right ADC", NULL, "ADC" }, 766 { "Right DAC", NULL, "DAC" }, 767 768 /* Right Mixer Routes */ 769 { "Right Mixer", NULL, "Mixer Enable" }, 770 { "Right Mixer", "Left DAC Playback Switch", "Left DAC" }, 771 { "Right Mixer", "Right DAC Playback Switch", "Right DAC" }, 772 773 /* Left Mixer Routes */ 774 { "Left Mixer", NULL, "Mixer Enable" }, 775 { "Left Mixer", "Left DAC Playback Switch", "Left DAC" }, 776 777 /* Power Amplifier Routes */ 778 { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" }, 779 { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" }, 780 { "Power Amplifier", "DAC Playback Switch", "Left DAC" }, 781 { "Power Amplifier", "DAC Playback Switch", "Right DAC" }, 782 783 /* Headphone Output Routes */ 784 { "Power Amplifier Mute", "Switch", "Power Amplifier" }, 785 { "HP Right", NULL, "Power Amplifier Mute" }, 786 { "HP Left", NULL, "Power Amplifier Mute" }, 787 788 /* Mic1 Routes */ 789 { "Left ADC", NULL, "MIC1 Pre-Amplifier" }, 790 { "Right ADC", NULL, "MIC1 Pre-Amplifier" }, 791 { "MIC1 Pre-Amplifier", NULL, "Mic1"}, 792 { "Mic1", NULL, "VMIC" }, 793 }; 794 795 static const struct snd_soc_component_driver sun4i_codec_codec = { 796 .controls = sun4i_codec_controls, 797 .num_controls = ARRAY_SIZE(sun4i_codec_controls), 798 .dapm_widgets = sun4i_codec_codec_dapm_widgets, 799 .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets), 800 .dapm_routes = sun4i_codec_codec_dapm_routes, 801 .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes), 802 .idle_bias_on = 1, 803 .use_pmdown_time = 1, 804 .endianness = 1, 805 .non_legacy_dai_naming = 1, 806 }; 807 808 /*** sun6i Codec ***/ 809 810 /* mixer controls */ 811 static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = { 812 SOC_DAPM_DOUBLE("DAC Playback Switch", 813 SUN6I_CODEC_OM_DACA_CTRL, 814 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL, 815 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0), 816 SOC_DAPM_DOUBLE("DAC Reversed Playback Switch", 817 SUN6I_CODEC_OM_DACA_CTRL, 818 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR, 819 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0), 820 SOC_DAPM_DOUBLE("Line In Playback Switch", 821 SUN6I_CODEC_OM_DACA_CTRL, 822 SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL, 823 SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0), 824 SOC_DAPM_DOUBLE("Mic1 Playback Switch", 825 SUN6I_CODEC_OM_DACA_CTRL, 826 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1, 827 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0), 828 SOC_DAPM_DOUBLE("Mic2 Playback Switch", 829 SUN6I_CODEC_OM_DACA_CTRL, 830 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2, 831 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0), 832 }; 833 834 /* ADC mixer controls */ 835 static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = { 836 SOC_DAPM_DOUBLE("Mixer Capture Switch", 837 SUN6I_CODEC_ADC_ACTL, 838 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL, 839 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0), 840 SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch", 841 SUN6I_CODEC_ADC_ACTL, 842 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR, 843 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0), 844 SOC_DAPM_DOUBLE("Line In Capture Switch", 845 SUN6I_CODEC_ADC_ACTL, 846 SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL, 847 SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0), 848 SOC_DAPM_DOUBLE("Mic1 Capture Switch", 849 SUN6I_CODEC_ADC_ACTL, 850 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1, 851 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0), 852 SOC_DAPM_DOUBLE("Mic2 Capture Switch", 853 SUN6I_CODEC_ADC_ACTL, 854 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2, 855 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0), 856 }; 857 858 /* headphone controls */ 859 static const char * const sun6i_codec_hp_src_enum_text[] = { 860 "DAC", "Mixer", 861 }; 862 863 static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum, 864 SUN6I_CODEC_OM_DACA_CTRL, 865 SUN6I_CODEC_OM_DACA_CTRL_LHPIS, 866 SUN6I_CODEC_OM_DACA_CTRL_RHPIS, 867 sun6i_codec_hp_src_enum_text); 868 869 static const struct snd_kcontrol_new sun6i_codec_hp_src[] = { 870 SOC_DAPM_ENUM("Headphone Source Playback Route", 871 sun6i_codec_hp_src_enum), 872 }; 873 874 /* microphone controls */ 875 static const char * const sun6i_codec_mic2_src_enum_text[] = { 876 "Mic2", "Mic3", 877 }; 878 879 static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum, 880 SUN6I_CODEC_MIC_CTRL, 881 SUN6I_CODEC_MIC_CTRL_MIC2SLT, 882 sun6i_codec_mic2_src_enum_text); 883 884 static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = { 885 SOC_DAPM_ENUM("Mic2 Amplifier Source Route", 886 sun6i_codec_mic2_src_enum), 887 }; 888 889 /* line out controls */ 890 static const char * const sun6i_codec_lineout_src_enum_text[] = { 891 "Stereo", "Mono Differential", 892 }; 893 894 static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum, 895 SUN6I_CODEC_MIC_CTRL, 896 SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC, 897 SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC, 898 sun6i_codec_lineout_src_enum_text); 899 900 static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = { 901 SOC_DAPM_ENUM("Line Out Source Playback Route", 902 sun6i_codec_lineout_src_enum), 903 }; 904 905 /* volume / mute controls */ 906 static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0); 907 static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1); 908 static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale, 909 -450, 150, 0); 910 static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale, 911 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 912 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0), 913 ); 914 static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale, 915 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 916 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0), 917 ); 918 919 static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = { 920 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC, 921 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1, 922 sun6i_codec_dvol_scale), 923 SOC_SINGLE_TLV("Headphone Playback Volume", 924 SUN6I_CODEC_OM_DACA_CTRL, 925 SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0, 926 sun6i_codec_hp_vol_scale), 927 SOC_SINGLE_TLV("Line Out Playback Volume", 928 SUN6I_CODEC_MIC_CTRL, 929 SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0, 930 sun6i_codec_lineout_vol_scale), 931 SOC_DOUBLE("Headphone Playback Switch", 932 SUN6I_CODEC_OM_DACA_CTRL, 933 SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE, 934 SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0), 935 SOC_DOUBLE("Line Out Playback Switch", 936 SUN6I_CODEC_MIC_CTRL, 937 SUN6I_CODEC_MIC_CTRL_LINEOUTLEN, 938 SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0), 939 /* Mixer pre-gains */ 940 SOC_SINGLE_TLV("Line In Playback Volume", 941 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING, 942 0x7, 0, sun6i_codec_out_mixer_pregain_scale), 943 SOC_SINGLE_TLV("Mic1 Playback Volume", 944 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G, 945 0x7, 0, sun6i_codec_out_mixer_pregain_scale), 946 SOC_SINGLE_TLV("Mic2 Playback Volume", 947 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G, 948 0x7, 0, sun6i_codec_out_mixer_pregain_scale), 949 950 /* Microphone Amp boost gains */ 951 SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL, 952 SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0, 953 sun6i_codec_mic_gain_scale), 954 SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL, 955 SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0, 956 sun6i_codec_mic_gain_scale), 957 SOC_DOUBLE_TLV("ADC Capture Volume", 958 SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG, 959 SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0, 960 sun6i_codec_out_mixer_pregain_scale), 961 }; 962 963 static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = { 964 /* Microphone inputs */ 965 SND_SOC_DAPM_INPUT("MIC1"), 966 SND_SOC_DAPM_INPUT("MIC2"), 967 SND_SOC_DAPM_INPUT("MIC3"), 968 969 /* Microphone Bias */ 970 SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL, 971 SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0), 972 SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL, 973 SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0), 974 975 /* Mic input path */ 976 SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route", 977 SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src), 978 SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL, 979 SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0), 980 SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL, 981 SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0), 982 983 /* Line In */ 984 SND_SOC_DAPM_INPUT("LINEIN"), 985 986 /* Digital parts of the ADCs */ 987 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC, 988 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, 989 NULL, 0), 990 991 /* Analog parts of the ADCs */ 992 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL, 993 SUN6I_CODEC_ADC_ACTL_ADCLEN, 0), 994 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL, 995 SUN6I_CODEC_ADC_ACTL_ADCREN, 0), 996 997 /* ADC Mixers */ 998 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 999 sun6i_codec_adc_mixer_controls), 1000 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1001 sun6i_codec_adc_mixer_controls), 1002 1003 /* Digital parts of the DACs */ 1004 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC, 1005 SUN4I_CODEC_DAC_DPC_EN_DA, 0, 1006 NULL, 0), 1007 1008 /* Analog parts of the DACs */ 1009 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", 1010 SUN6I_CODEC_OM_DACA_CTRL, 1011 SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0), 1012 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", 1013 SUN6I_CODEC_OM_DACA_CTRL, 1014 SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0), 1015 1016 /* Mixers */ 1017 SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL, 1018 SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0, 1019 sun6i_codec_mixer_controls), 1020 SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL, 1021 SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0, 1022 sun6i_codec_mixer_controls), 1023 1024 /* Headphone output path */ 1025 SND_SOC_DAPM_MUX("Headphone Source Playback Route", 1026 SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src), 1027 SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL, 1028 SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0), 1029 SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL, 1030 SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0), 1031 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL, 1032 SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0), 1033 SND_SOC_DAPM_OUTPUT("HP"), 1034 1035 /* Line Out path */ 1036 SND_SOC_DAPM_MUX("Line Out Source Playback Route", 1037 SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src), 1038 SND_SOC_DAPM_OUTPUT("LINEOUT"), 1039 }; 1040 1041 static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = { 1042 /* DAC Routes */ 1043 { "Left DAC", NULL, "DAC Enable" }, 1044 { "Right DAC", NULL, "DAC Enable" }, 1045 1046 /* Microphone Routes */ 1047 { "Mic1 Amplifier", NULL, "MIC1"}, 1048 { "Mic2 Amplifier Source Route", "Mic2", "MIC2" }, 1049 { "Mic2 Amplifier Source Route", "Mic3", "MIC3" }, 1050 { "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"}, 1051 1052 /* Left Mixer Routes */ 1053 { "Left Mixer", "DAC Playback Switch", "Left DAC" }, 1054 { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" }, 1055 { "Left Mixer", "Line In Playback Switch", "LINEIN" }, 1056 { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" }, 1057 { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" }, 1058 1059 /* Right Mixer Routes */ 1060 { "Right Mixer", "DAC Playback Switch", "Right DAC" }, 1061 { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" }, 1062 { "Right Mixer", "Line In Playback Switch", "LINEIN" }, 1063 { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" }, 1064 { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" }, 1065 1066 /* Left ADC Mixer Routes */ 1067 { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" }, 1068 { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" }, 1069 { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" }, 1070 { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" }, 1071 { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" }, 1072 1073 /* Right ADC Mixer Routes */ 1074 { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" }, 1075 { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" }, 1076 { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" }, 1077 { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" }, 1078 { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" }, 1079 1080 /* Headphone Routes */ 1081 { "Headphone Source Playback Route", "DAC", "Left DAC" }, 1082 { "Headphone Source Playback Route", "DAC", "Right DAC" }, 1083 { "Headphone Source Playback Route", "Mixer", "Left Mixer" }, 1084 { "Headphone Source Playback Route", "Mixer", "Right Mixer" }, 1085 { "Headphone Amp", NULL, "Headphone Source Playback Route" }, 1086 { "HP", NULL, "Headphone Amp" }, 1087 { "HPCOM", NULL, "HPCOM Protection" }, 1088 1089 /* Line Out Routes */ 1090 { "Line Out Source Playback Route", "Stereo", "Left Mixer" }, 1091 { "Line Out Source Playback Route", "Stereo", "Right Mixer" }, 1092 { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" }, 1093 { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" }, 1094 { "LINEOUT", NULL, "Line Out Source Playback Route" }, 1095 1096 /* ADC Routes */ 1097 { "Left ADC", NULL, "ADC Enable" }, 1098 { "Right ADC", NULL, "ADC Enable" }, 1099 { "Left ADC", NULL, "Left ADC Mixer" }, 1100 { "Right ADC", NULL, "Right ADC Mixer" }, 1101 }; 1102 1103 static const struct snd_soc_component_driver sun6i_codec_codec = { 1104 .controls = sun6i_codec_codec_widgets, 1105 .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets), 1106 .dapm_widgets = sun6i_codec_codec_dapm_widgets, 1107 .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets), 1108 .dapm_routes = sun6i_codec_codec_dapm_routes, 1109 .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes), 1110 .idle_bias_on = 1, 1111 .use_pmdown_time = 1, 1112 .endianness = 1, 1113 .non_legacy_dai_naming = 1, 1114 }; 1115 1116 /* sun8i A23 codec */ 1117 static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = { 1118 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC, 1119 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1, 1120 sun6i_codec_dvol_scale), 1121 }; 1122 1123 static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = { 1124 /* Digital parts of the ADCs */ 1125 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC, 1126 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0), 1127 /* Digital parts of the DACs */ 1128 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC, 1129 SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0), 1130 1131 }; 1132 1133 static const struct snd_soc_component_driver sun8i_a23_codec_codec = { 1134 .controls = sun8i_a23_codec_codec_controls, 1135 .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls), 1136 .dapm_widgets = sun8i_a23_codec_codec_widgets, 1137 .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets), 1138 .idle_bias_on = 1, 1139 .use_pmdown_time = 1, 1140 .endianness = 1, 1141 .non_legacy_dai_naming = 1, 1142 }; 1143 1144 static const struct snd_soc_component_driver sun4i_codec_component = { 1145 .name = "sun4i-codec", 1146 }; 1147 1148 #define SUN4I_CODEC_RATES SNDRV_PCM_RATE_CONTINUOUS 1149 #define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 1150 SNDRV_PCM_FMTBIT_S32_LE) 1151 1152 static int sun4i_codec_dai_probe(struct snd_soc_dai *dai) 1153 { 1154 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1155 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card); 1156 1157 snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data, 1158 &scodec->capture_dma_data); 1159 1160 return 0; 1161 } 1162 1163 static struct snd_soc_dai_driver dummy_cpu_dai = { 1164 .name = "sun4i-codec-cpu-dai", 1165 .probe = sun4i_codec_dai_probe, 1166 .playback = { 1167 .stream_name = "Playback", 1168 .channels_min = 1, 1169 .channels_max = 2, 1170 .rates = SUN4I_CODEC_RATES, 1171 .formats = SUN4I_CODEC_FORMATS, 1172 .sig_bits = 24, 1173 }, 1174 .capture = { 1175 .stream_name = "Capture", 1176 .channels_min = 1, 1177 .channels_max = 2, 1178 .rates = SUN4I_CODEC_RATES, 1179 .formats = SUN4I_CODEC_FORMATS, 1180 .sig_bits = 24, 1181 }, 1182 }; 1183 1184 static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev, 1185 int *num_links) 1186 { 1187 struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link), 1188 GFP_KERNEL); 1189 if (!link) 1190 return NULL; 1191 1192 link->name = "cdc"; 1193 link->stream_name = "CDC PCM"; 1194 link->codec_dai_name = "Codec"; 1195 link->cpu_dai_name = dev_name(dev); 1196 link->codec_name = dev_name(dev); 1197 link->platform_name = dev_name(dev); 1198 link->dai_fmt = SND_SOC_DAIFMT_I2S; 1199 1200 *num_links = 1; 1201 1202 return link; 1203 }; 1204 1205 static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w, 1206 struct snd_kcontrol *k, int event) 1207 { 1208 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card); 1209 1210 gpiod_set_value_cansleep(scodec->gpio_pa, 1211 !!SND_SOC_DAPM_EVENT_ON(event)); 1212 1213 return 0; 1214 } 1215 1216 static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = { 1217 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event), 1218 }; 1219 1220 static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = { 1221 { "Speaker", NULL, "HP Right" }, 1222 { "Speaker", NULL, "HP Left" }, 1223 }; 1224 1225 static struct snd_soc_card *sun4i_codec_create_card(struct device *dev) 1226 { 1227 struct snd_soc_card *card; 1228 1229 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1230 if (!card) 1231 return ERR_PTR(-ENOMEM); 1232 1233 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1234 if (!card->dai_link) 1235 return ERR_PTR(-ENOMEM); 1236 1237 card->dev = dev; 1238 card->name = "sun4i-codec"; 1239 card->dapm_widgets = sun4i_codec_card_dapm_widgets; 1240 card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets); 1241 card->dapm_routes = sun4i_codec_card_dapm_routes; 1242 card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes); 1243 1244 return card; 1245 }; 1246 1247 static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = { 1248 SND_SOC_DAPM_HP("Headphone", NULL), 1249 SND_SOC_DAPM_LINE("Line In", NULL), 1250 SND_SOC_DAPM_LINE("Line Out", NULL), 1251 SND_SOC_DAPM_MIC("Headset Mic", NULL), 1252 SND_SOC_DAPM_MIC("Mic", NULL), 1253 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event), 1254 }; 1255 1256 static struct snd_soc_card *sun6i_codec_create_card(struct device *dev) 1257 { 1258 struct snd_soc_card *card; 1259 int ret; 1260 1261 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1262 if (!card) 1263 return ERR_PTR(-ENOMEM); 1264 1265 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1266 if (!card->dai_link) 1267 return ERR_PTR(-ENOMEM); 1268 1269 card->dev = dev; 1270 card->name = "A31 Audio Codec"; 1271 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1272 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1273 card->fully_routed = true; 1274 1275 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1276 if (ret) 1277 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1278 1279 return card; 1280 }; 1281 1282 /* Connect digital side enables to analog side widgets */ 1283 static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = { 1284 /* ADC Routes */ 1285 { "Left ADC", NULL, "ADC Enable" }, 1286 { "Right ADC", NULL, "ADC Enable" }, 1287 { "Codec Capture", NULL, "Left ADC" }, 1288 { "Codec Capture", NULL, "Right ADC" }, 1289 1290 /* DAC Routes */ 1291 { "Left DAC", NULL, "DAC Enable" }, 1292 { "Right DAC", NULL, "DAC Enable" }, 1293 { "Left DAC", NULL, "Codec Playback" }, 1294 { "Right DAC", NULL, "Codec Playback" }, 1295 }; 1296 1297 static struct snd_soc_aux_dev aux_dev = { 1298 .name = "Codec Analog Controls", 1299 }; 1300 1301 static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev) 1302 { 1303 struct snd_soc_card *card; 1304 int ret; 1305 1306 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1307 if (!card) 1308 return ERR_PTR(-ENOMEM); 1309 1310 aux_dev.codec_of_node = of_parse_phandle(dev->of_node, 1311 "allwinner,codec-analog-controls", 1312 0); 1313 if (!aux_dev.codec_of_node) { 1314 dev_err(dev, "Can't find analog controls for codec.\n"); 1315 return ERR_PTR(-EINVAL); 1316 }; 1317 1318 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1319 if (!card->dai_link) 1320 return ERR_PTR(-ENOMEM); 1321 1322 card->dev = dev; 1323 card->name = "A23 Audio Codec"; 1324 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1325 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1326 card->dapm_routes = sun8i_codec_card_routes; 1327 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); 1328 card->aux_dev = &aux_dev; 1329 card->num_aux_devs = 1; 1330 card->fully_routed = true; 1331 1332 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1333 if (ret) 1334 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1335 1336 return card; 1337 }; 1338 1339 static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev) 1340 { 1341 struct snd_soc_card *card; 1342 int ret; 1343 1344 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1345 if (!card) 1346 return ERR_PTR(-ENOMEM); 1347 1348 aux_dev.codec_of_node = of_parse_phandle(dev->of_node, 1349 "allwinner,codec-analog-controls", 1350 0); 1351 if (!aux_dev.codec_of_node) { 1352 dev_err(dev, "Can't find analog controls for codec.\n"); 1353 return ERR_PTR(-EINVAL); 1354 }; 1355 1356 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1357 if (!card->dai_link) 1358 return ERR_PTR(-ENOMEM); 1359 1360 card->dev = dev; 1361 card->name = "H3 Audio Codec"; 1362 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1363 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1364 card->dapm_routes = sun8i_codec_card_routes; 1365 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); 1366 card->aux_dev = &aux_dev; 1367 card->num_aux_devs = 1; 1368 card->fully_routed = true; 1369 1370 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1371 if (ret) 1372 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1373 1374 return card; 1375 }; 1376 1377 static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev) 1378 { 1379 struct snd_soc_card *card; 1380 int ret; 1381 1382 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1383 if (!card) 1384 return ERR_PTR(-ENOMEM); 1385 1386 aux_dev.codec_of_node = of_parse_phandle(dev->of_node, 1387 "allwinner,codec-analog-controls", 1388 0); 1389 if (!aux_dev.codec_of_node) { 1390 dev_err(dev, "Can't find analog controls for codec.\n"); 1391 return ERR_PTR(-EINVAL); 1392 }; 1393 1394 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1395 if (!card->dai_link) 1396 return ERR_PTR(-ENOMEM); 1397 1398 card->dev = dev; 1399 card->name = "V3s Audio Codec"; 1400 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1401 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1402 card->dapm_routes = sun8i_codec_card_routes; 1403 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); 1404 card->aux_dev = &aux_dev; 1405 card->num_aux_devs = 1; 1406 card->fully_routed = true; 1407 1408 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1409 if (ret) 1410 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1411 1412 return card; 1413 }; 1414 1415 static const struct regmap_config sun4i_codec_regmap_config = { 1416 .reg_bits = 32, 1417 .reg_stride = 4, 1418 .val_bits = 32, 1419 .max_register = SUN4I_CODEC_ADC_RXCNT, 1420 }; 1421 1422 static const struct regmap_config sun6i_codec_regmap_config = { 1423 .reg_bits = 32, 1424 .reg_stride = 4, 1425 .val_bits = 32, 1426 .max_register = SUN6I_CODEC_HMIC_DATA, 1427 }; 1428 1429 static const struct regmap_config sun7i_codec_regmap_config = { 1430 .reg_bits = 32, 1431 .reg_stride = 4, 1432 .val_bits = 32, 1433 .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL, 1434 }; 1435 1436 static const struct regmap_config sun8i_a23_codec_regmap_config = { 1437 .reg_bits = 32, 1438 .reg_stride = 4, 1439 .val_bits = 32, 1440 .max_register = SUN8I_A23_CODEC_ADC_RXCNT, 1441 }; 1442 1443 static const struct regmap_config sun8i_h3_codec_regmap_config = { 1444 .reg_bits = 32, 1445 .reg_stride = 4, 1446 .val_bits = 32, 1447 .max_register = SUN8I_H3_CODEC_ADC_DBG, 1448 }; 1449 1450 static const struct regmap_config sun8i_v3s_codec_regmap_config = { 1451 .reg_bits = 32, 1452 .reg_stride = 4, 1453 .val_bits = 32, 1454 .max_register = SUN8I_H3_CODEC_ADC_DBG, 1455 }; 1456 1457 struct sun4i_codec_quirks { 1458 const struct regmap_config *regmap_config; 1459 const struct snd_soc_component_driver *codec; 1460 struct snd_soc_card * (*create_card)(struct device *dev); 1461 struct reg_field reg_adc_fifoc; /* used for regmap_field */ 1462 unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ 1463 unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ 1464 bool has_reset; 1465 }; 1466 1467 static const struct sun4i_codec_quirks sun4i_codec_quirks = { 1468 .regmap_config = &sun4i_codec_regmap_config, 1469 .codec = &sun4i_codec_codec, 1470 .create_card = sun4i_codec_create_card, 1471 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), 1472 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1473 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, 1474 }; 1475 1476 static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = { 1477 .regmap_config = &sun6i_codec_regmap_config, 1478 .codec = &sun6i_codec_codec, 1479 .create_card = sun6i_codec_create_card, 1480 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1481 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1482 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1483 .has_reset = true, 1484 }; 1485 1486 static const struct sun4i_codec_quirks sun7i_codec_quirks = { 1487 .regmap_config = &sun7i_codec_regmap_config, 1488 .codec = &sun4i_codec_codec, 1489 .create_card = sun4i_codec_create_card, 1490 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), 1491 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1492 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, 1493 }; 1494 1495 static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = { 1496 .regmap_config = &sun8i_a23_codec_regmap_config, 1497 .codec = &sun8i_a23_codec_codec, 1498 .create_card = sun8i_a23_codec_create_card, 1499 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1500 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1501 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1502 .has_reset = true, 1503 }; 1504 1505 static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = { 1506 .regmap_config = &sun8i_h3_codec_regmap_config, 1507 /* 1508 * TODO Share the codec structure with A23 for now. 1509 * This should be split out when adding digital audio 1510 * processing support for the H3. 1511 */ 1512 .codec = &sun8i_a23_codec_codec, 1513 .create_card = sun8i_h3_codec_create_card, 1514 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1515 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, 1516 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1517 .has_reset = true, 1518 }; 1519 1520 static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = { 1521 .regmap_config = &sun8i_v3s_codec_regmap_config, 1522 /* 1523 * TODO The codec structure should be split out, like 1524 * H3, when adding digital audio processing support. 1525 */ 1526 .codec = &sun8i_a23_codec_codec, 1527 .create_card = sun8i_v3s_codec_create_card, 1528 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1529 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, 1530 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1531 .has_reset = true, 1532 }; 1533 1534 static const struct of_device_id sun4i_codec_of_match[] = { 1535 { 1536 .compatible = "allwinner,sun4i-a10-codec", 1537 .data = &sun4i_codec_quirks, 1538 }, 1539 { 1540 .compatible = "allwinner,sun6i-a31-codec", 1541 .data = &sun6i_a31_codec_quirks, 1542 }, 1543 { 1544 .compatible = "allwinner,sun7i-a20-codec", 1545 .data = &sun7i_codec_quirks, 1546 }, 1547 { 1548 .compatible = "allwinner,sun8i-a23-codec", 1549 .data = &sun8i_a23_codec_quirks, 1550 }, 1551 { 1552 .compatible = "allwinner,sun8i-h3-codec", 1553 .data = &sun8i_h3_codec_quirks, 1554 }, 1555 { 1556 .compatible = "allwinner,sun8i-v3s-codec", 1557 .data = &sun8i_v3s_codec_quirks, 1558 }, 1559 {} 1560 }; 1561 MODULE_DEVICE_TABLE(of, sun4i_codec_of_match); 1562 1563 static int sun4i_codec_probe(struct platform_device *pdev) 1564 { 1565 struct snd_soc_card *card; 1566 struct sun4i_codec *scodec; 1567 const struct sun4i_codec_quirks *quirks; 1568 struct resource *res; 1569 void __iomem *base; 1570 int ret; 1571 1572 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL); 1573 if (!scodec) 1574 return -ENOMEM; 1575 1576 scodec->dev = &pdev->dev; 1577 1578 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1579 base = devm_ioremap_resource(&pdev->dev, res); 1580 if (IS_ERR(base)) { 1581 dev_err(&pdev->dev, "Failed to map the registers\n"); 1582 return PTR_ERR(base); 1583 } 1584 1585 quirks = of_device_get_match_data(&pdev->dev); 1586 if (quirks == NULL) { 1587 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1588 return -ENODEV; 1589 } 1590 1591 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1592 quirks->regmap_config); 1593 if (IS_ERR(scodec->regmap)) { 1594 dev_err(&pdev->dev, "Failed to create our regmap\n"); 1595 return PTR_ERR(scodec->regmap); 1596 } 1597 1598 /* Get the clocks from the DT */ 1599 scodec->clk_apb = devm_clk_get(&pdev->dev, "apb"); 1600 if (IS_ERR(scodec->clk_apb)) { 1601 dev_err(&pdev->dev, "Failed to get the APB clock\n"); 1602 return PTR_ERR(scodec->clk_apb); 1603 } 1604 1605 scodec->clk_module = devm_clk_get(&pdev->dev, "codec"); 1606 if (IS_ERR(scodec->clk_module)) { 1607 dev_err(&pdev->dev, "Failed to get the module clock\n"); 1608 return PTR_ERR(scodec->clk_module); 1609 } 1610 1611 if (quirks->has_reset) { 1612 scodec->rst = devm_reset_control_get_exclusive(&pdev->dev, 1613 NULL); 1614 if (IS_ERR(scodec->rst)) { 1615 dev_err(&pdev->dev, "Failed to get reset control\n"); 1616 return PTR_ERR(scodec->rst); 1617 } 1618 } 1619 1620 scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa", 1621 GPIOD_OUT_LOW); 1622 if (IS_ERR(scodec->gpio_pa)) { 1623 ret = PTR_ERR(scodec->gpio_pa); 1624 if (ret != -EPROBE_DEFER) 1625 dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret); 1626 return ret; 1627 } 1628 1629 /* reg_field setup */ 1630 scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev, 1631 scodec->regmap, 1632 quirks->reg_adc_fifoc); 1633 if (IS_ERR(scodec->reg_adc_fifoc)) { 1634 ret = PTR_ERR(scodec->reg_adc_fifoc); 1635 dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", 1636 ret); 1637 return ret; 1638 } 1639 1640 /* Enable the bus clock */ 1641 if (clk_prepare_enable(scodec->clk_apb)) { 1642 dev_err(&pdev->dev, "Failed to enable the APB clock\n"); 1643 return -EINVAL; 1644 } 1645 1646 /* Deassert the reset control */ 1647 if (scodec->rst) { 1648 ret = reset_control_deassert(scodec->rst); 1649 if (ret) { 1650 dev_err(&pdev->dev, 1651 "Failed to deassert the reset control\n"); 1652 goto err_clk_disable; 1653 } 1654 } 1655 1656 /* DMA configuration for TX FIFO */ 1657 scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata; 1658 scodec->playback_dma_data.maxburst = 8; 1659 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1660 1661 /* DMA configuration for RX FIFO */ 1662 scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata; 1663 scodec->capture_dma_data.maxburst = 8; 1664 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1665 1666 ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec, 1667 &sun4i_codec_dai, 1); 1668 if (ret) { 1669 dev_err(&pdev->dev, "Failed to register our codec\n"); 1670 goto err_assert_reset; 1671 } 1672 1673 ret = devm_snd_soc_register_component(&pdev->dev, 1674 &sun4i_codec_component, 1675 &dummy_cpu_dai, 1); 1676 if (ret) { 1677 dev_err(&pdev->dev, "Failed to register our DAI\n"); 1678 goto err_assert_reset; 1679 } 1680 1681 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1682 if (ret) { 1683 dev_err(&pdev->dev, "Failed to register against DMAEngine\n"); 1684 goto err_assert_reset; 1685 } 1686 1687 card = quirks->create_card(&pdev->dev); 1688 if (IS_ERR(card)) { 1689 ret = PTR_ERR(card); 1690 dev_err(&pdev->dev, "Failed to create our card\n"); 1691 goto err_assert_reset; 1692 } 1693 1694 snd_soc_card_set_drvdata(card, scodec); 1695 1696 ret = snd_soc_register_card(card); 1697 if (ret) { 1698 dev_err(&pdev->dev, "Failed to register our card\n"); 1699 goto err_assert_reset; 1700 } 1701 1702 return 0; 1703 1704 err_assert_reset: 1705 if (scodec->rst) 1706 reset_control_assert(scodec->rst); 1707 err_clk_disable: 1708 clk_disable_unprepare(scodec->clk_apb); 1709 return ret; 1710 } 1711 1712 static int sun4i_codec_remove(struct platform_device *pdev) 1713 { 1714 struct snd_soc_card *card = platform_get_drvdata(pdev); 1715 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card); 1716 1717 snd_soc_unregister_card(card); 1718 if (scodec->rst) 1719 reset_control_assert(scodec->rst); 1720 clk_disable_unprepare(scodec->clk_apb); 1721 1722 return 0; 1723 } 1724 1725 static struct platform_driver sun4i_codec_driver = { 1726 .driver = { 1727 .name = "sun4i-codec", 1728 .of_match_table = sun4i_codec_of_match, 1729 }, 1730 .probe = sun4i_codec_probe, 1731 .remove = sun4i_codec_remove, 1732 }; 1733 module_platform_driver(sun4i_codec_driver); 1734 1735 MODULE_DESCRIPTION("Allwinner A10 codec driver"); 1736 MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>"); 1737 MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>"); 1738 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1739 MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>"); 1740 MODULE_LICENSE("GPL"); 1741