1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 3 * 4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/completion.h> 21 #include <linux/delay.h> 22 #include <linux/module.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/regmap.h> 26 #include <linux/reset.h> 27 28 #include <sound/dmaengine_pcm.h> 29 #include <sound/pcm_params.h> 30 31 /* SPDIF-rx Register Map */ 32 #define STM32_SPDIFRX_CR 0x00 33 #define STM32_SPDIFRX_IMR 0x04 34 #define STM32_SPDIFRX_SR 0x08 35 #define STM32_SPDIFRX_IFCR 0x0C 36 #define STM32_SPDIFRX_DR 0x10 37 #define STM32_SPDIFRX_CSR 0x14 38 #define STM32_SPDIFRX_DIR 0x18 39 40 /* Bit definition for SPDIF_CR register */ 41 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 42 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 43 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 44 45 #define SPDIFRX_CR_RXDMAEN BIT(2) 46 #define SPDIFRX_CR_RXSTEO BIT(3) 47 48 #define SPDIFRX_CR_DRFMT_SHIFT 4 49 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 50 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 51 52 #define SPDIFRX_CR_PMSK BIT(6) 53 #define SPDIFRX_CR_VMSK BIT(7) 54 #define SPDIFRX_CR_CUMSK BIT(8) 55 #define SPDIFRX_CR_PTMSK BIT(9) 56 #define SPDIFRX_CR_CBDMAEN BIT(10) 57 #define SPDIFRX_CR_CHSEL_SHIFT 11 58 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 59 60 #define SPDIFRX_CR_NBTR_SHIFT 12 61 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 62 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 63 64 #define SPDIFRX_CR_WFA BIT(14) 65 66 #define SPDIFRX_CR_INSEL_SHIFT 16 67 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 68 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 69 70 #define SPDIFRX_CR_CKSEN_SHIFT 20 71 #define SPDIFRX_CR_CKSEN BIT(20) 72 #define SPDIFRX_CR_CKSBKPEN BIT(21) 73 74 /* Bit definition for SPDIFRX_IMR register */ 75 #define SPDIFRX_IMR_RXNEI BIT(0) 76 #define SPDIFRX_IMR_CSRNEIE BIT(1) 77 #define SPDIFRX_IMR_PERRIE BIT(2) 78 #define SPDIFRX_IMR_OVRIE BIT(3) 79 #define SPDIFRX_IMR_SBLKIE BIT(4) 80 #define SPDIFRX_IMR_SYNCDIE BIT(5) 81 #define SPDIFRX_IMR_IFEIE BIT(6) 82 83 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 84 85 /* Bit definition for SPDIFRX_SR register */ 86 #define SPDIFRX_SR_RXNE BIT(0) 87 #define SPDIFRX_SR_CSRNE BIT(1) 88 #define SPDIFRX_SR_PERR BIT(2) 89 #define SPDIFRX_SR_OVR BIT(3) 90 #define SPDIFRX_SR_SBD BIT(4) 91 #define SPDIFRX_SR_SYNCD BIT(5) 92 #define SPDIFRX_SR_FERR BIT(6) 93 #define SPDIFRX_SR_SERR BIT(7) 94 #define SPDIFRX_SR_TERR BIT(8) 95 96 #define SPDIFRX_SR_WIDTH5_SHIFT 16 97 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 98 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 99 100 /* Bit definition for SPDIFRX_IFCR register */ 101 #define SPDIFRX_IFCR_PERRCF BIT(2) 102 #define SPDIFRX_IFCR_OVRCF BIT(3) 103 #define SPDIFRX_IFCR_SBDCF BIT(4) 104 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 105 106 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 107 108 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 109 #define SPDIFRX_DR0_DR_SHIFT 0 110 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 111 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 112 113 #define SPDIFRX_DR0_PE BIT(24) 114 115 #define SPDIFRX_DR0_V BIT(25) 116 #define SPDIFRX_DR0_U BIT(26) 117 #define SPDIFRX_DR0_C BIT(27) 118 119 #define SPDIFRX_DR0_PT_SHIFT 28 120 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 121 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 122 123 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 124 #define SPDIFRX_DR1_PE BIT(0) 125 #define SPDIFRX_DR1_V BIT(1) 126 #define SPDIFRX_DR1_U BIT(2) 127 #define SPDIFRX_DR1_C BIT(3) 128 129 #define SPDIFRX_DR1_PT_SHIFT 4 130 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 131 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 132 133 #define SPDIFRX_DR1_DR_SHIFT 8 134 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 135 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 136 137 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 138 #define SPDIFRX_DR1_DRNL1_SHIFT 0 139 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 140 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 141 142 #define SPDIFRX_DR1_DRNL2_SHIFT 16 143 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 144 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 145 146 /* Bit definition for SPDIFRX_CSR register */ 147 #define SPDIFRX_CSR_USR_SHIFT 0 148 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 149 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 150 >> SPDIFRX_CSR_USR_SHIFT) 151 152 #define SPDIFRX_CSR_CS_SHIFT 16 153 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 154 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 155 >> SPDIFRX_CSR_CS_SHIFT) 156 157 #define SPDIFRX_CSR_SOB BIT(24) 158 159 /* Bit definition for SPDIFRX_DIR register */ 160 #define SPDIFRX_DIR_THI_SHIFT 0 161 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 162 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 163 164 #define SPDIFRX_DIR_TLO_SHIFT 16 165 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 166 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 167 168 #define SPDIFRX_SPDIFEN_DISABLE 0x0 169 #define SPDIFRX_SPDIFEN_SYNC 0x1 170 #define SPDIFRX_SPDIFEN_ENABLE 0x3 171 172 #define SPDIFRX_IN1 0x1 173 #define SPDIFRX_IN2 0x2 174 #define SPDIFRX_IN3 0x3 175 #define SPDIFRX_IN4 0x4 176 #define SPDIFRX_IN5 0x5 177 #define SPDIFRX_IN6 0x6 178 #define SPDIFRX_IN7 0x7 179 #define SPDIFRX_IN8 0x8 180 181 #define SPDIFRX_NBTR_NONE 0x0 182 #define SPDIFRX_NBTR_3 0x1 183 #define SPDIFRX_NBTR_15 0x2 184 #define SPDIFRX_NBTR_63 0x3 185 186 #define SPDIFRX_DRFMT_RIGHT 0x0 187 #define SPDIFRX_DRFMT_LEFT 0x1 188 #define SPDIFRX_DRFMT_PACKED 0x2 189 190 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 191 #define SPDIFRX_CS_BYTES_NB 24 192 #define SPDIFRX_UB_BYTES_NB 48 193 194 /* 195 * CSR register is retrieved as a 32 bits word 196 * It contains 1 channel status byte and 2 user data bytes 197 * 2 S/PDIF frames are acquired to get all CS/UB bits 198 */ 199 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 200 201 /** 202 * struct stm32_spdifrx_data - private data of SPDIFRX 203 * @pdev: device data pointer 204 * @base: mmio register base virtual address 205 * @regmap: SPDIFRX register map pointer 206 * @regmap_conf: SPDIFRX register map configuration pointer 207 * @cs_completion: channel status retrieving completion 208 * @kclk: kernel clock feeding the SPDIFRX clock generator 209 * @dma_params: dma configuration data for rx channel 210 * @substream: PCM substream data pointer 211 * @dmab: dma buffer info pointer 212 * @ctrl_chan: dma channel for S/PDIF control bits 213 * @desc:dma async transaction descriptor 214 * @slave_config: dma slave channel runtime config pointer 215 * @phys_addr: SPDIFRX registers physical base address 216 * @lock: synchronization enabling lock 217 * @cs: channel status buffer 218 * @ub: user data buffer 219 * @irq: SPDIFRX interrupt line 220 * @refcount: keep count of opened DMA channels 221 */ 222 struct stm32_spdifrx_data { 223 struct platform_device *pdev; 224 void __iomem *base; 225 struct regmap *regmap; 226 const struct regmap_config *regmap_conf; 227 struct completion cs_completion; 228 struct clk *kclk; 229 struct snd_dmaengine_dai_dma_data dma_params; 230 struct snd_pcm_substream *substream; 231 struct snd_dma_buffer *dmab; 232 struct dma_chan *ctrl_chan; 233 struct dma_async_tx_descriptor *desc; 234 struct dma_slave_config slave_config; 235 dma_addr_t phys_addr; 236 spinlock_t lock; /* Sync enabling lock */ 237 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 238 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 239 int irq; 240 int refcount; 241 }; 242 243 static void stm32_spdifrx_dma_complete(void *data) 244 { 245 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 246 struct platform_device *pdev = spdifrx->pdev; 247 u32 *p_start = (u32 *)spdifrx->dmab->area; 248 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 249 u32 *ptr = p_start; 250 u16 *ub_ptr = (short *)spdifrx->ub; 251 int i = 0; 252 253 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 254 SPDIFRX_CR_CBDMAEN, 255 (unsigned int)~SPDIFRX_CR_CBDMAEN); 256 257 if (!spdifrx->dmab->area) 258 return; 259 260 while (ptr <= p_end) { 261 if (*ptr & SPDIFRX_CSR_SOB) 262 break; 263 ptr++; 264 } 265 266 if (ptr > p_end) { 267 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 268 return; 269 } 270 271 while (i < SPDIFRX_CS_BYTES_NB) { 272 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 273 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 274 if (ptr > p_end) { 275 dev_err(&pdev->dev, "Failed to get channel status\n"); 276 return; 277 } 278 i++; 279 } 280 281 complete(&spdifrx->cs_completion); 282 } 283 284 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 285 { 286 dma_cookie_t cookie; 287 int err; 288 289 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 290 spdifrx->dmab->addr, 291 SPDIFRX_CSR_BUF_LENGTH, 292 DMA_DEV_TO_MEM, 293 DMA_CTRL_ACK); 294 if (!spdifrx->desc) 295 return -EINVAL; 296 297 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 298 spdifrx->desc->callback_param = spdifrx; 299 cookie = dmaengine_submit(spdifrx->desc); 300 err = dma_submit_error(cookie); 301 if (err) 302 return -EINVAL; 303 304 dma_async_issue_pending(spdifrx->ctrl_chan); 305 306 return 0; 307 } 308 309 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 310 { 311 dmaengine_terminate_async(spdifrx->ctrl_chan); 312 } 313 314 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 315 { 316 int cr, cr_mask, imr, ret; 317 318 /* Enable IRQs */ 319 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 320 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 321 if (ret) 322 return ret; 323 324 spin_lock(&spdifrx->lock); 325 326 spdifrx->refcount++; 327 328 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 329 330 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 331 /* 332 * Start sync if SPDIFRX is still in idle state. 333 * SPDIFRX reception enabled when sync done 334 */ 335 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 336 337 /* 338 * SPDIFRX configuration: 339 * Wait for activity before starting sync process. This avoid 340 * to issue sync errors when spdif signal is missing on input. 341 * Preamble, CS, user, validity and parity error bits not copied 342 * to DR register. 343 */ 344 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 345 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 346 cr_mask = cr; 347 348 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 349 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 350 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 351 cr_mask, cr); 352 if (ret < 0) 353 dev_err(&spdifrx->pdev->dev, 354 "Failed to start synchronization\n"); 355 } 356 357 spin_unlock(&spdifrx->lock); 358 359 return ret; 360 } 361 362 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 363 { 364 int cr, cr_mask, reg; 365 366 spin_lock(&spdifrx->lock); 367 368 if (--spdifrx->refcount) { 369 spin_unlock(&spdifrx->lock); 370 return; 371 } 372 373 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 374 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 375 376 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 377 378 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 379 SPDIFRX_XIMR_MASK, 0); 380 381 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 382 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 383 384 /* dummy read to clear CSRNE and RXNE in status register */ 385 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 386 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 387 388 spin_unlock(&spdifrx->lock); 389 } 390 391 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 392 struct stm32_spdifrx_data *spdifrx) 393 { 394 int ret; 395 396 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 397 if (IS_ERR(spdifrx->ctrl_chan)) { 398 dev_err(dev, "dma_request_slave_channel failed\n"); 399 return PTR_ERR(spdifrx->ctrl_chan); 400 } 401 402 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 403 GFP_KERNEL); 404 if (!spdifrx->dmab) 405 return -ENOMEM; 406 407 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 408 spdifrx->dmab->dev.dev = dev; 409 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 410 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 411 if (ret < 0) { 412 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 413 return ret; 414 } 415 416 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 417 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 418 STM32_SPDIFRX_CSR); 419 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 420 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 421 spdifrx->slave_config.src_maxburst = 1; 422 423 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 424 &spdifrx->slave_config); 425 if (ret < 0) { 426 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 427 spdifrx->ctrl_chan = NULL; 428 } 429 430 return ret; 431 }; 432 433 static const char * const spdifrx_enum_input[] = { 434 "in0", "in1", "in2", "in3" 435 }; 436 437 /* By default CS bits are retrieved from channel A */ 438 static const char * const spdifrx_enum_cs_channel[] = { 439 "A", "B" 440 }; 441 442 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 443 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 444 spdifrx_enum_input); 445 446 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 447 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 448 spdifrx_enum_cs_channel); 449 450 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 451 struct snd_ctl_elem_info *uinfo) 452 { 453 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 454 uinfo->count = 1; 455 456 return 0; 457 } 458 459 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 460 struct snd_ctl_elem_info *uinfo) 461 { 462 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 463 uinfo->count = 1; 464 465 return 0; 466 } 467 468 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 469 { 470 int ret = 0; 471 472 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 473 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 474 475 pinctrl_pm_select_default_state(&spdifrx->pdev->dev); 476 477 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 478 if (ret < 0) 479 return ret; 480 481 ret = clk_prepare_enable(spdifrx->kclk); 482 if (ret) { 483 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 484 return ret; 485 } 486 487 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 488 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 489 if (ret < 0) 490 goto end; 491 492 ret = stm32_spdifrx_start_sync(spdifrx); 493 if (ret < 0) 494 goto end; 495 496 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 497 msecs_to_jiffies(100)) 498 <= 0) { 499 dev_err(&spdifrx->pdev->dev, "Failed to get control data\n"); 500 ret = -EAGAIN; 501 } 502 503 stm32_spdifrx_stop(spdifrx); 504 stm32_spdifrx_dma_ctrl_stop(spdifrx); 505 506 end: 507 clk_disable_unprepare(spdifrx->kclk); 508 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev); 509 510 return ret; 511 } 512 513 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 514 struct snd_ctl_elem_value *ucontrol) 515 { 516 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 517 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 518 519 stm32_spdifrx_get_ctrl_data(spdifrx); 520 521 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 522 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 523 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 524 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 525 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 526 527 return 0; 528 } 529 530 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 531 struct snd_ctl_elem_value *ucontrol) 532 { 533 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 534 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 535 536 stm32_spdifrx_get_ctrl_data(spdifrx); 537 538 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 539 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 540 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 541 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 542 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 543 544 return 0; 545 } 546 547 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 548 /* Channel status control */ 549 { 550 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 551 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 552 .access = SNDRV_CTL_ELEM_ACCESS_READ | 553 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 554 .info = stm32_spdifrx_info, 555 .get = stm32_spdifrx_capture_get, 556 }, 557 /* User bits control */ 558 { 559 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 560 .name = "IEC958 User Bit Capture Default", 561 .access = SNDRV_CTL_ELEM_ACCESS_READ | 562 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 563 .info = stm32_spdifrx_ub_info, 564 .get = stm32_spdif_user_bits_get, 565 }, 566 }; 567 568 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 569 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 570 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 571 }; 572 573 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 574 { 575 int ret; 576 577 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 578 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 579 if (ret < 0) 580 return ret; 581 582 return snd_soc_add_component_controls(cpu_dai->component, 583 stm32_spdifrx_ctrls, 584 ARRAY_SIZE(stm32_spdifrx_ctrls)); 585 } 586 587 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 588 { 589 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 590 591 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 592 STM32_SPDIFRX_DR); 593 spdifrx->dma_params.maxburst = 1; 594 595 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 596 597 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 598 } 599 600 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 601 { 602 switch (reg) { 603 case STM32_SPDIFRX_CR: 604 case STM32_SPDIFRX_IMR: 605 case STM32_SPDIFRX_SR: 606 case STM32_SPDIFRX_IFCR: 607 case STM32_SPDIFRX_DR: 608 case STM32_SPDIFRX_CSR: 609 case STM32_SPDIFRX_DIR: 610 return true; 611 default: 612 return false; 613 } 614 } 615 616 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 617 { 618 switch (reg) { 619 case STM32_SPDIFRX_DR: 620 case STM32_SPDIFRX_CSR: 621 case STM32_SPDIFRX_SR: 622 case STM32_SPDIFRX_DIR: 623 return true; 624 default: 625 return false; 626 } 627 } 628 629 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 630 { 631 switch (reg) { 632 case STM32_SPDIFRX_CR: 633 case STM32_SPDIFRX_IMR: 634 case STM32_SPDIFRX_IFCR: 635 return true; 636 default: 637 return false; 638 } 639 } 640 641 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 642 .reg_bits = 32, 643 .reg_stride = 4, 644 .val_bits = 32, 645 .max_register = STM32_SPDIFRX_DIR, 646 .readable_reg = stm32_spdifrx_readable_reg, 647 .volatile_reg = stm32_spdifrx_volatile_reg, 648 .writeable_reg = stm32_spdifrx_writeable_reg, 649 .fast_io = true, 650 .cache_type = REGCACHE_FLAT, 651 }; 652 653 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 654 { 655 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 656 struct snd_pcm_substream *substream = spdifrx->substream; 657 struct platform_device *pdev = spdifrx->pdev; 658 unsigned int cr, mask, sr, imr; 659 unsigned int flags; 660 int err = 0, err_xrun = 0; 661 662 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 663 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 664 665 mask = imr & SPDIFRX_XIMR_MASK; 666 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 667 if (mask & SPDIFRX_IMR_IFEIE) 668 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 669 670 flags = sr & mask; 671 if (!flags) { 672 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 673 sr, imr); 674 return IRQ_NONE; 675 } 676 677 /* Clear IRQs */ 678 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 679 SPDIFRX_XIFCR_MASK, flags); 680 681 if (flags & SPDIFRX_SR_PERR) { 682 dev_dbg(&pdev->dev, "Parity error\n"); 683 err_xrun = 1; 684 } 685 686 if (flags & SPDIFRX_SR_OVR) { 687 dev_dbg(&pdev->dev, "Overrun error\n"); 688 err_xrun = 1; 689 } 690 691 if (flags & SPDIFRX_SR_SBD) 692 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 693 694 if (flags & SPDIFRX_SR_SYNCD) { 695 dev_dbg(&pdev->dev, "Synchronization done\n"); 696 697 /* Enable spdifrx */ 698 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 699 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 700 SPDIFRX_CR_SPDIFEN_MASK, cr); 701 } 702 703 if (flags & SPDIFRX_SR_FERR) { 704 dev_dbg(&pdev->dev, "Frame error\n"); 705 err = 1; 706 } 707 708 if (flags & SPDIFRX_SR_SERR) { 709 dev_dbg(&pdev->dev, "Synchronization error\n"); 710 err = 1; 711 } 712 713 if (flags & SPDIFRX_SR_TERR) { 714 dev_dbg(&pdev->dev, "Timeout error\n"); 715 err = 1; 716 } 717 718 if (err) { 719 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */ 720 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 721 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 722 SPDIFRX_CR_SPDIFEN_MASK, cr); 723 724 if (substream) 725 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); 726 727 return IRQ_HANDLED; 728 } 729 730 if (err_xrun && substream) 731 snd_pcm_stop_xrun(substream); 732 733 return IRQ_HANDLED; 734 } 735 736 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 737 struct snd_soc_dai *cpu_dai) 738 { 739 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 740 int ret; 741 742 spdifrx->substream = substream; 743 744 ret = clk_prepare_enable(spdifrx->kclk); 745 if (ret) 746 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 747 748 return ret; 749 } 750 751 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 752 struct snd_pcm_hw_params *params, 753 struct snd_soc_dai *cpu_dai) 754 { 755 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 756 int data_size = params_width(params); 757 int fmt; 758 759 switch (data_size) { 760 case 16: 761 fmt = SPDIFRX_DRFMT_PACKED; 762 break; 763 case 32: 764 fmt = SPDIFRX_DRFMT_LEFT; 765 break; 766 default: 767 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 768 return -EINVAL; 769 } 770 771 /* 772 * Set buswidth to 4 bytes for all data formats. 773 * Packed format: transfer 2 x 2 bytes samples 774 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 775 */ 776 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 777 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 778 779 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 780 SPDIFRX_CR_DRFMT_MASK, 781 SPDIFRX_CR_DRFMTSET(fmt)); 782 } 783 784 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 785 struct snd_soc_dai *cpu_dai) 786 { 787 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 788 int ret = 0; 789 790 switch (cmd) { 791 case SNDRV_PCM_TRIGGER_START: 792 case SNDRV_PCM_TRIGGER_RESUME: 793 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 794 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 795 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 796 797 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 798 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 799 800 ret = stm32_spdifrx_start_sync(spdifrx); 801 break; 802 case SNDRV_PCM_TRIGGER_SUSPEND: 803 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 804 case SNDRV_PCM_TRIGGER_STOP: 805 stm32_spdifrx_stop(spdifrx); 806 break; 807 default: 808 return -EINVAL; 809 } 810 811 return ret; 812 } 813 814 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 815 struct snd_soc_dai *cpu_dai) 816 { 817 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 818 819 spdifrx->substream = NULL; 820 clk_disable_unprepare(spdifrx->kclk); 821 } 822 823 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 824 .startup = stm32_spdifrx_startup, 825 .hw_params = stm32_spdifrx_hw_params, 826 .trigger = stm32_spdifrx_trigger, 827 .shutdown = stm32_spdifrx_shutdown, 828 }; 829 830 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 831 { 832 .probe = stm32_spdifrx_dai_probe, 833 .capture = { 834 .stream_name = "CPU-Capture", 835 .channels_min = 1, 836 .channels_max = 2, 837 .rates = SNDRV_PCM_RATE_8000_192000, 838 .formats = SNDRV_PCM_FMTBIT_S32_LE | 839 SNDRV_PCM_FMTBIT_S16_LE, 840 }, 841 .ops = &stm32_spdifrx_pcm_dai_ops, 842 } 843 }; 844 845 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 846 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 847 .buffer_bytes_max = 8 * PAGE_SIZE, 848 .period_bytes_max = 2048, /* MDMA constraint */ 849 .periods_min = 2, 850 .periods_max = 8, 851 }; 852 853 static const struct snd_soc_component_driver stm32_spdifrx_component = { 854 .name = "stm32-spdifrx", 855 }; 856 857 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 858 .pcm_hardware = &stm32_spdifrx_pcm_hw, 859 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 860 }; 861 862 static const struct of_device_id stm32_spdifrx_ids[] = { 863 { 864 .compatible = "st,stm32h7-spdifrx", 865 .data = &stm32_h7_spdifrx_regmap_conf 866 }, 867 {} 868 }; 869 870 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 871 struct stm32_spdifrx_data *spdifrx) 872 { 873 struct device_node *np = pdev->dev.of_node; 874 const struct of_device_id *of_id; 875 struct resource *res; 876 877 if (!np) 878 return -ENODEV; 879 880 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 881 if (of_id) 882 spdifrx->regmap_conf = 883 (const struct regmap_config *)of_id->data; 884 else 885 return -EINVAL; 886 887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 888 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 889 if (IS_ERR(spdifrx->base)) 890 return PTR_ERR(spdifrx->base); 891 892 spdifrx->phys_addr = res->start; 893 894 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 895 if (IS_ERR(spdifrx->kclk)) { 896 dev_err(&pdev->dev, "Could not get kclk\n"); 897 return PTR_ERR(spdifrx->kclk); 898 } 899 900 spdifrx->irq = platform_get_irq(pdev, 0); 901 if (spdifrx->irq < 0) { 902 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name); 903 return spdifrx->irq; 904 } 905 906 return 0; 907 } 908 909 static int stm32_spdifrx_probe(struct platform_device *pdev) 910 { 911 struct stm32_spdifrx_data *spdifrx; 912 struct reset_control *rst; 913 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 914 int ret; 915 916 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 917 if (!spdifrx) 918 return -ENOMEM; 919 920 spdifrx->pdev = pdev; 921 init_completion(&spdifrx->cs_completion); 922 spin_lock_init(&spdifrx->lock); 923 924 platform_set_drvdata(pdev, spdifrx); 925 926 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 927 if (ret) 928 return ret; 929 930 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 931 spdifrx->base, 932 spdifrx->regmap_conf); 933 if (IS_ERR(spdifrx->regmap)) { 934 dev_err(&pdev->dev, "Regmap init failed\n"); 935 return PTR_ERR(spdifrx->regmap); 936 } 937 938 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 939 dev_name(&pdev->dev), spdifrx); 940 if (ret) { 941 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 942 return ret; 943 } 944 945 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 946 if (!IS_ERR(rst)) { 947 reset_control_assert(rst); 948 udelay(2); 949 reset_control_deassert(rst); 950 } 951 952 ret = devm_snd_soc_register_component(&pdev->dev, 953 &stm32_spdifrx_component, 954 stm32_spdifrx_dai, 955 ARRAY_SIZE(stm32_spdifrx_dai)); 956 if (ret) 957 return ret; 958 959 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 960 if (ret) 961 goto error; 962 963 pcm_config = &stm32_spdifrx_pcm_config; 964 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 965 if (ret) { 966 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret); 967 goto error; 968 } 969 970 return 0; 971 972 error: 973 if (!IS_ERR(spdifrx->ctrl_chan)) 974 dma_release_channel(spdifrx->ctrl_chan); 975 if (spdifrx->dmab) 976 snd_dma_free_pages(spdifrx->dmab); 977 978 return ret; 979 } 980 981 static int stm32_spdifrx_remove(struct platform_device *pdev) 982 { 983 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 984 985 if (spdifrx->ctrl_chan) 986 dma_release_channel(spdifrx->ctrl_chan); 987 988 if (spdifrx->dmab) 989 snd_dma_free_pages(spdifrx->dmab); 990 991 return 0; 992 } 993 994 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 995 996 #ifdef CONFIG_PM_SLEEP 997 static int stm32_spdifrx_suspend(struct device *dev) 998 { 999 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1000 1001 regcache_cache_only(spdifrx->regmap, true); 1002 regcache_mark_dirty(spdifrx->regmap); 1003 1004 return 0; 1005 } 1006 1007 static int stm32_spdifrx_resume(struct device *dev) 1008 { 1009 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1010 1011 regcache_cache_only(spdifrx->regmap, false); 1012 1013 return regcache_sync(spdifrx->regmap); 1014 } 1015 #endif /* CONFIG_PM_SLEEP */ 1016 1017 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1018 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1019 }; 1020 1021 static struct platform_driver stm32_spdifrx_driver = { 1022 .driver = { 1023 .name = "st,stm32-spdifrx", 1024 .of_match_table = stm32_spdifrx_ids, 1025 .pm = &stm32_spdifrx_pm_ops, 1026 }, 1027 .probe = stm32_spdifrx_probe, 1028 .remove = stm32_spdifrx_remove, 1029 }; 1030 1031 module_platform_driver(stm32_spdifrx_driver); 1032 1033 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1034 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1035 MODULE_ALIAS("platform:stm32-spdifrx"); 1036 MODULE_LICENSE("GPL v2"); 1037