1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 3 * 4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/completion.h> 21 #include <linux/delay.h> 22 #include <linux/module.h> 23 #include <linux/of_platform.h> 24 #include <linux/regmap.h> 25 #include <linux/reset.h> 26 27 #include <sound/dmaengine_pcm.h> 28 #include <sound/pcm_params.h> 29 30 /* SPDIF-rx Register Map */ 31 #define STM32_SPDIFRX_CR 0x00 32 #define STM32_SPDIFRX_IMR 0x04 33 #define STM32_SPDIFRX_SR 0x08 34 #define STM32_SPDIFRX_IFCR 0x0C 35 #define STM32_SPDIFRX_DR 0x10 36 #define STM32_SPDIFRX_CSR 0x14 37 #define STM32_SPDIFRX_DIR 0x18 38 39 /* Bit definition for SPDIF_CR register */ 40 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 41 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 42 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 43 44 #define SPDIFRX_CR_RXDMAEN BIT(2) 45 #define SPDIFRX_CR_RXSTEO BIT(3) 46 47 #define SPDIFRX_CR_DRFMT_SHIFT 4 48 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 49 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 50 51 #define SPDIFRX_CR_PMSK BIT(6) 52 #define SPDIFRX_CR_VMSK BIT(7) 53 #define SPDIFRX_CR_CUMSK BIT(8) 54 #define SPDIFRX_CR_PTMSK BIT(9) 55 #define SPDIFRX_CR_CBDMAEN BIT(10) 56 #define SPDIFRX_CR_CHSEL_SHIFT 11 57 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 58 59 #define SPDIFRX_CR_NBTR_SHIFT 12 60 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 61 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 62 63 #define SPDIFRX_CR_WFA BIT(14) 64 65 #define SPDIFRX_CR_INSEL_SHIFT 16 66 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 67 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 68 69 #define SPDIFRX_CR_CKSEN_SHIFT 20 70 #define SPDIFRX_CR_CKSEN BIT(20) 71 #define SPDIFRX_CR_CKSBKPEN BIT(21) 72 73 /* Bit definition for SPDIFRX_IMR register */ 74 #define SPDIFRX_IMR_RXNEI BIT(0) 75 #define SPDIFRX_IMR_CSRNEIE BIT(1) 76 #define SPDIFRX_IMR_PERRIE BIT(2) 77 #define SPDIFRX_IMR_OVRIE BIT(3) 78 #define SPDIFRX_IMR_SBLKIE BIT(4) 79 #define SPDIFRX_IMR_SYNCDIE BIT(5) 80 #define SPDIFRX_IMR_IFEIE BIT(6) 81 82 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 83 84 /* Bit definition for SPDIFRX_SR register */ 85 #define SPDIFRX_SR_RXNE BIT(0) 86 #define SPDIFRX_SR_CSRNE BIT(1) 87 #define SPDIFRX_SR_PERR BIT(2) 88 #define SPDIFRX_SR_OVR BIT(3) 89 #define SPDIFRX_SR_SBD BIT(4) 90 #define SPDIFRX_SR_SYNCD BIT(5) 91 #define SPDIFRX_SR_FERR BIT(6) 92 #define SPDIFRX_SR_SERR BIT(7) 93 #define SPDIFRX_SR_TERR BIT(8) 94 95 #define SPDIFRX_SR_WIDTH5_SHIFT 16 96 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 97 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 98 99 /* Bit definition for SPDIFRX_IFCR register */ 100 #define SPDIFRX_IFCR_PERRCF BIT(2) 101 #define SPDIFRX_IFCR_OVRCF BIT(3) 102 #define SPDIFRX_IFCR_SBDCF BIT(4) 103 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 104 105 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 106 107 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 108 #define SPDIFRX_DR0_DR_SHIFT 0 109 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 110 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 111 112 #define SPDIFRX_DR0_PE BIT(24) 113 114 #define SPDIFRX_DR0_V BIT(25) 115 #define SPDIFRX_DR0_U BIT(26) 116 #define SPDIFRX_DR0_C BIT(27) 117 118 #define SPDIFRX_DR0_PT_SHIFT 28 119 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 120 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 121 122 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 123 #define SPDIFRX_DR1_PE BIT(0) 124 #define SPDIFRX_DR1_V BIT(1) 125 #define SPDIFRX_DR1_U BIT(2) 126 #define SPDIFRX_DR1_C BIT(3) 127 128 #define SPDIFRX_DR1_PT_SHIFT 4 129 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 130 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 131 132 #define SPDIFRX_DR1_DR_SHIFT 8 133 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 134 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 135 136 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 137 #define SPDIFRX_DR1_DRNL1_SHIFT 0 138 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 139 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 140 141 #define SPDIFRX_DR1_DRNL2_SHIFT 16 142 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 143 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 144 145 /* Bit definition for SPDIFRX_CSR register */ 146 #define SPDIFRX_CSR_USR_SHIFT 0 147 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 148 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 149 >> SPDIFRX_CSR_USR_SHIFT) 150 151 #define SPDIFRX_CSR_CS_SHIFT 16 152 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 153 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 154 >> SPDIFRX_CSR_CS_SHIFT) 155 156 #define SPDIFRX_CSR_SOB BIT(24) 157 158 /* Bit definition for SPDIFRX_DIR register */ 159 #define SPDIFRX_DIR_THI_SHIFT 0 160 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 161 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 162 163 #define SPDIFRX_DIR_TLO_SHIFT 16 164 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 165 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 166 167 #define SPDIFRX_SPDIFEN_DISABLE 0x0 168 #define SPDIFRX_SPDIFEN_SYNC 0x1 169 #define SPDIFRX_SPDIFEN_ENABLE 0x3 170 171 #define SPDIFRX_IN1 0x1 172 #define SPDIFRX_IN2 0x2 173 #define SPDIFRX_IN3 0x3 174 #define SPDIFRX_IN4 0x4 175 #define SPDIFRX_IN5 0x5 176 #define SPDIFRX_IN6 0x6 177 #define SPDIFRX_IN7 0x7 178 #define SPDIFRX_IN8 0x8 179 180 #define SPDIFRX_NBTR_NONE 0x0 181 #define SPDIFRX_NBTR_3 0x1 182 #define SPDIFRX_NBTR_15 0x2 183 #define SPDIFRX_NBTR_63 0x3 184 185 #define SPDIFRX_DRFMT_RIGHT 0x0 186 #define SPDIFRX_DRFMT_LEFT 0x1 187 #define SPDIFRX_DRFMT_PACKED 0x2 188 189 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 190 #define SPDIFRX_CS_BYTES_NB 24 191 #define SPDIFRX_UB_BYTES_NB 48 192 193 /* 194 * CSR register is retrieved as a 32 bits word 195 * It contains 1 channel status byte and 2 user data bytes 196 * 2 S/PDIF frames are acquired to get all CS/UB bits 197 */ 198 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 199 200 /** 201 * struct stm32_spdifrx_data - private data of SPDIFRX 202 * @pdev: device data pointer 203 * @base: mmio register base virtual address 204 * @regmap: SPDIFRX register map pointer 205 * @regmap_conf: SPDIFRX register map configuration pointer 206 * @cs_completion: channel status retrieving completion 207 * @kclk: kernel clock feeding the SPDIFRX clock generator 208 * @dma_params: dma configuration data for rx channel 209 * @substream: PCM substream data pointer 210 * @dmab: dma buffer info pointer 211 * @ctrl_chan: dma channel for S/PDIF control bits 212 * @desc:dma async transaction descriptor 213 * @slave_config: dma slave channel runtime config pointer 214 * @phys_addr: SPDIFRX registers physical base address 215 * @lock: synchronization enabling lock 216 * @cs: channel status buffer 217 * @ub: user data buffer 218 * @irq: SPDIFRX interrupt line 219 * @refcount: keep count of opened DMA channels 220 */ 221 struct stm32_spdifrx_data { 222 struct platform_device *pdev; 223 void __iomem *base; 224 struct regmap *regmap; 225 const struct regmap_config *regmap_conf; 226 struct completion cs_completion; 227 struct clk *kclk; 228 struct snd_dmaengine_dai_dma_data dma_params; 229 struct snd_pcm_substream *substream; 230 struct snd_dma_buffer *dmab; 231 struct dma_chan *ctrl_chan; 232 struct dma_async_tx_descriptor *desc; 233 struct dma_slave_config slave_config; 234 dma_addr_t phys_addr; 235 spinlock_t lock; /* Sync enabling lock */ 236 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 237 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 238 int irq; 239 int refcount; 240 }; 241 242 static void stm32_spdifrx_dma_complete(void *data) 243 { 244 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 245 struct platform_device *pdev = spdifrx->pdev; 246 u32 *p_start = (u32 *)spdifrx->dmab->area; 247 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 248 u32 *ptr = p_start; 249 u16 *ub_ptr = (short *)spdifrx->ub; 250 int i = 0; 251 252 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 253 SPDIFRX_CR_CBDMAEN, 254 (unsigned int)~SPDIFRX_CR_CBDMAEN); 255 256 if (!spdifrx->dmab->area) 257 return; 258 259 while (ptr <= p_end) { 260 if (*ptr & SPDIFRX_CSR_SOB) 261 break; 262 ptr++; 263 } 264 265 if (ptr > p_end) { 266 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 267 return; 268 } 269 270 while (i < SPDIFRX_CS_BYTES_NB) { 271 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 272 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 273 if (ptr > p_end) { 274 dev_err(&pdev->dev, "Failed to get channel status\n"); 275 return; 276 } 277 i++; 278 } 279 280 complete(&spdifrx->cs_completion); 281 } 282 283 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 284 { 285 dma_cookie_t cookie; 286 int err; 287 288 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 289 spdifrx->dmab->addr, 290 SPDIFRX_CSR_BUF_LENGTH, 291 DMA_DEV_TO_MEM, 292 DMA_CTRL_ACK); 293 if (!spdifrx->desc) 294 return -EINVAL; 295 296 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 297 spdifrx->desc->callback_param = spdifrx; 298 cookie = dmaengine_submit(spdifrx->desc); 299 err = dma_submit_error(cookie); 300 if (err) 301 return -EINVAL; 302 303 dma_async_issue_pending(spdifrx->ctrl_chan); 304 305 return 0; 306 } 307 308 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 309 { 310 dmaengine_terminate_async(spdifrx->ctrl_chan); 311 } 312 313 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 314 { 315 int cr, cr_mask, imr, ret; 316 317 /* Enable IRQs */ 318 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 319 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 320 if (ret) 321 return ret; 322 323 spin_lock(&spdifrx->lock); 324 325 spdifrx->refcount++; 326 327 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 328 329 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 330 /* 331 * Start sync if SPDIFRX is still in idle state. 332 * SPDIFRX reception enabled when sync done 333 */ 334 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 335 336 /* 337 * SPDIFRX configuration: 338 * Wait for activity before starting sync process. This avoid 339 * to issue sync errors when spdif signal is missing on input. 340 * Preamble, CS, user, validity and parity error bits not copied 341 * to DR register. 342 */ 343 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 344 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 345 cr_mask = cr; 346 347 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 348 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 349 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 350 cr_mask, cr); 351 if (ret < 0) 352 dev_err(&spdifrx->pdev->dev, 353 "Failed to start synchronization\n"); 354 } 355 356 spin_unlock(&spdifrx->lock); 357 358 return ret; 359 } 360 361 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 362 { 363 int cr, cr_mask, reg; 364 365 spin_lock(&spdifrx->lock); 366 367 if (--spdifrx->refcount) { 368 spin_unlock(&spdifrx->lock); 369 return; 370 } 371 372 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 373 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 374 375 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 376 377 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 378 SPDIFRX_XIMR_MASK, 0); 379 380 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 381 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 382 383 /* dummy read to clear CSRNE and RXNE in status register */ 384 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 385 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 386 387 spin_unlock(&spdifrx->lock); 388 } 389 390 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 391 struct stm32_spdifrx_data *spdifrx) 392 { 393 int ret; 394 395 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 396 if (IS_ERR(spdifrx->ctrl_chan)) { 397 dev_err(dev, "dma_request_slave_channel failed\n"); 398 return PTR_ERR(spdifrx->ctrl_chan); 399 } 400 401 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 402 GFP_KERNEL); 403 if (!spdifrx->dmab) 404 return -ENOMEM; 405 406 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 407 spdifrx->dmab->dev.dev = dev; 408 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 409 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 410 if (ret < 0) { 411 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 412 return ret; 413 } 414 415 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 416 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 417 STM32_SPDIFRX_CSR); 418 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 419 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 420 spdifrx->slave_config.src_maxburst = 1; 421 422 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 423 &spdifrx->slave_config); 424 if (ret < 0) { 425 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 426 spdifrx->ctrl_chan = NULL; 427 } 428 429 return ret; 430 }; 431 432 static const char * const spdifrx_enum_input[] = { 433 "in0", "in1", "in2", "in3" 434 }; 435 436 /* By default CS bits are retrieved from channel A */ 437 static const char * const spdifrx_enum_cs_channel[] = { 438 "A", "B" 439 }; 440 441 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 442 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 443 spdifrx_enum_input); 444 445 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 446 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 447 spdifrx_enum_cs_channel); 448 449 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 450 struct snd_ctl_elem_info *uinfo) 451 { 452 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 453 uinfo->count = 1; 454 455 return 0; 456 } 457 458 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 459 struct snd_ctl_elem_info *uinfo) 460 { 461 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 462 uinfo->count = 1; 463 464 return 0; 465 } 466 467 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 468 { 469 int ret = 0; 470 471 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 472 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 473 474 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 475 if (ret < 0) 476 return ret; 477 478 ret = clk_prepare_enable(spdifrx->kclk); 479 if (ret) { 480 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 481 return ret; 482 } 483 484 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 485 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 486 if (ret < 0) 487 goto end; 488 489 ret = stm32_spdifrx_start_sync(spdifrx); 490 if (ret < 0) 491 goto end; 492 493 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 494 msecs_to_jiffies(100)) 495 <= 0) { 496 dev_err(&spdifrx->pdev->dev, "Failed to get control data\n"); 497 ret = -EAGAIN; 498 } 499 500 stm32_spdifrx_stop(spdifrx); 501 stm32_spdifrx_dma_ctrl_stop(spdifrx); 502 503 end: 504 clk_disable_unprepare(spdifrx->kclk); 505 506 return ret; 507 } 508 509 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 510 struct snd_ctl_elem_value *ucontrol) 511 { 512 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 513 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 514 515 stm32_spdifrx_get_ctrl_data(spdifrx); 516 517 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 518 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 519 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 520 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 521 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 522 523 return 0; 524 } 525 526 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 527 struct snd_ctl_elem_value *ucontrol) 528 { 529 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 530 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 531 532 stm32_spdifrx_get_ctrl_data(spdifrx); 533 534 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 535 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 536 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 537 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 538 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 539 540 return 0; 541 } 542 543 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 544 /* Channel status control */ 545 { 546 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 547 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 548 .access = SNDRV_CTL_ELEM_ACCESS_READ | 549 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 550 .info = stm32_spdifrx_info, 551 .get = stm32_spdifrx_capture_get, 552 }, 553 /* User bits control */ 554 { 555 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 556 .name = "IEC958 User Bit Capture Default", 557 .access = SNDRV_CTL_ELEM_ACCESS_READ | 558 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 559 .info = stm32_spdifrx_ub_info, 560 .get = stm32_spdif_user_bits_get, 561 }, 562 }; 563 564 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 565 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 566 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 567 }; 568 569 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 570 { 571 int ret; 572 573 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 574 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 575 if (ret < 0) 576 return ret; 577 578 return snd_soc_add_component_controls(cpu_dai->component, 579 stm32_spdifrx_ctrls, 580 ARRAY_SIZE(stm32_spdifrx_ctrls)); 581 } 582 583 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 584 { 585 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 586 587 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 588 STM32_SPDIFRX_DR); 589 spdifrx->dma_params.maxburst = 1; 590 591 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 592 593 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 594 } 595 596 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 597 { 598 switch (reg) { 599 case STM32_SPDIFRX_CR: 600 case STM32_SPDIFRX_IMR: 601 case STM32_SPDIFRX_SR: 602 case STM32_SPDIFRX_IFCR: 603 case STM32_SPDIFRX_DR: 604 case STM32_SPDIFRX_CSR: 605 case STM32_SPDIFRX_DIR: 606 return true; 607 default: 608 return false; 609 } 610 } 611 612 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 613 { 614 if (reg == STM32_SPDIFRX_DR) 615 return true; 616 617 return false; 618 } 619 620 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 621 { 622 switch (reg) { 623 case STM32_SPDIFRX_CR: 624 case STM32_SPDIFRX_IMR: 625 case STM32_SPDIFRX_IFCR: 626 return true; 627 default: 628 return false; 629 } 630 } 631 632 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 633 .reg_bits = 32, 634 .reg_stride = 4, 635 .val_bits = 32, 636 .max_register = STM32_SPDIFRX_DIR, 637 .readable_reg = stm32_spdifrx_readable_reg, 638 .volatile_reg = stm32_spdifrx_volatile_reg, 639 .writeable_reg = stm32_spdifrx_writeable_reg, 640 .fast_io = true, 641 }; 642 643 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 644 { 645 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 646 struct snd_pcm_substream *substream = spdifrx->substream; 647 struct platform_device *pdev = spdifrx->pdev; 648 unsigned int cr, mask, sr, imr; 649 unsigned int flags; 650 int err = 0, err_xrun = 0; 651 652 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 653 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 654 655 mask = imr & SPDIFRX_XIMR_MASK; 656 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 657 if (mask & SPDIFRX_IMR_IFEIE) 658 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 659 660 flags = sr & mask; 661 if (!flags) { 662 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 663 sr, imr); 664 return IRQ_NONE; 665 } 666 667 /* Clear IRQs */ 668 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 669 SPDIFRX_XIFCR_MASK, flags); 670 671 if (flags & SPDIFRX_SR_PERR) { 672 dev_dbg(&pdev->dev, "Parity error\n"); 673 err_xrun = 1; 674 } 675 676 if (flags & SPDIFRX_SR_OVR) { 677 dev_dbg(&pdev->dev, "Overrun error\n"); 678 err_xrun = 1; 679 } 680 681 if (flags & SPDIFRX_SR_SBD) 682 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 683 684 if (flags & SPDIFRX_SR_SYNCD) { 685 dev_dbg(&pdev->dev, "Synchronization done\n"); 686 687 /* Enable spdifrx */ 688 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 689 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 690 SPDIFRX_CR_SPDIFEN_MASK, cr); 691 } 692 693 if (flags & SPDIFRX_SR_FERR) { 694 dev_dbg(&pdev->dev, "Frame error\n"); 695 err = 1; 696 } 697 698 if (flags & SPDIFRX_SR_SERR) { 699 dev_dbg(&pdev->dev, "Synchronization error\n"); 700 err = 1; 701 } 702 703 if (flags & SPDIFRX_SR_TERR) { 704 dev_dbg(&pdev->dev, "Timeout error\n"); 705 err = 1; 706 } 707 708 if (err) { 709 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */ 710 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 711 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 712 SPDIFRX_CR_SPDIFEN_MASK, cr); 713 714 if (substream) 715 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); 716 717 return IRQ_HANDLED; 718 } 719 720 if (err_xrun && substream) 721 snd_pcm_stop_xrun(substream); 722 723 return IRQ_HANDLED; 724 } 725 726 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 727 struct snd_soc_dai *cpu_dai) 728 { 729 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 730 int ret; 731 732 spdifrx->substream = substream; 733 734 ret = clk_prepare_enable(spdifrx->kclk); 735 if (ret) 736 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 737 738 return ret; 739 } 740 741 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 742 struct snd_pcm_hw_params *params, 743 struct snd_soc_dai *cpu_dai) 744 { 745 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 746 int data_size = params_width(params); 747 int fmt; 748 749 switch (data_size) { 750 case 16: 751 fmt = SPDIFRX_DRFMT_PACKED; 752 break; 753 case 32: 754 fmt = SPDIFRX_DRFMT_LEFT; 755 break; 756 default: 757 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 758 return -EINVAL; 759 } 760 761 /* 762 * Set buswidth to 4 bytes for all data formats. 763 * Packed format: transfer 2 x 2 bytes samples 764 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 765 */ 766 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 767 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 768 769 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 770 SPDIFRX_CR_DRFMT_MASK, 771 SPDIFRX_CR_DRFMTSET(fmt)); 772 } 773 774 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 775 struct snd_soc_dai *cpu_dai) 776 { 777 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 778 int ret = 0; 779 780 switch (cmd) { 781 case SNDRV_PCM_TRIGGER_START: 782 case SNDRV_PCM_TRIGGER_RESUME: 783 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 784 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 785 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 786 787 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 788 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 789 790 ret = stm32_spdifrx_start_sync(spdifrx); 791 break; 792 case SNDRV_PCM_TRIGGER_SUSPEND: 793 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 794 case SNDRV_PCM_TRIGGER_STOP: 795 stm32_spdifrx_stop(spdifrx); 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 return ret; 802 } 803 804 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 805 struct snd_soc_dai *cpu_dai) 806 { 807 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 808 809 spdifrx->substream = NULL; 810 clk_disable_unprepare(spdifrx->kclk); 811 } 812 813 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 814 .startup = stm32_spdifrx_startup, 815 .hw_params = stm32_spdifrx_hw_params, 816 .trigger = stm32_spdifrx_trigger, 817 .shutdown = stm32_spdifrx_shutdown, 818 }; 819 820 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 821 { 822 .name = "spdifrx-capture-cpu-dai", 823 .probe = stm32_spdifrx_dai_probe, 824 .capture = { 825 .stream_name = "CPU-Capture", 826 .channels_min = 1, 827 .channels_max = 2, 828 .rates = SNDRV_PCM_RATE_8000_192000, 829 .formats = SNDRV_PCM_FMTBIT_S32_LE | 830 SNDRV_PCM_FMTBIT_S16_LE, 831 }, 832 .ops = &stm32_spdifrx_pcm_dai_ops, 833 } 834 }; 835 836 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 837 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 838 .buffer_bytes_max = 8 * PAGE_SIZE, 839 .period_bytes_max = 2048, /* MDMA constraint */ 840 .periods_min = 2, 841 .periods_max = 8, 842 }; 843 844 static const struct snd_soc_component_driver stm32_spdifrx_component = { 845 .name = "stm32-spdifrx", 846 }; 847 848 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 849 .pcm_hardware = &stm32_spdifrx_pcm_hw, 850 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 851 }; 852 853 static const struct of_device_id stm32_spdifrx_ids[] = { 854 { 855 .compatible = "st,stm32h7-spdifrx", 856 .data = &stm32_h7_spdifrx_regmap_conf 857 }, 858 {} 859 }; 860 861 static int stm_spdifrx_parse_of(struct platform_device *pdev, 862 struct stm32_spdifrx_data *spdifrx) 863 { 864 struct device_node *np = pdev->dev.of_node; 865 const struct of_device_id *of_id; 866 struct resource *res; 867 868 if (!np) 869 return -ENODEV; 870 871 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 872 if (of_id) 873 spdifrx->regmap_conf = 874 (const struct regmap_config *)of_id->data; 875 else 876 return -EINVAL; 877 878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 879 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 880 if (IS_ERR(spdifrx->base)) 881 return PTR_ERR(spdifrx->base); 882 883 spdifrx->phys_addr = res->start; 884 885 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 886 if (IS_ERR(spdifrx->kclk)) { 887 dev_err(&pdev->dev, "Could not get kclk\n"); 888 return PTR_ERR(spdifrx->kclk); 889 } 890 891 spdifrx->irq = platform_get_irq(pdev, 0); 892 if (spdifrx->irq < 0) { 893 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name); 894 return spdifrx->irq; 895 } 896 897 return 0; 898 } 899 900 static int stm32_spdifrx_probe(struct platform_device *pdev) 901 { 902 struct stm32_spdifrx_data *spdifrx; 903 struct reset_control *rst; 904 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 905 int ret; 906 907 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 908 if (!spdifrx) 909 return -ENOMEM; 910 911 spdifrx->pdev = pdev; 912 init_completion(&spdifrx->cs_completion); 913 spin_lock_init(&spdifrx->lock); 914 915 platform_set_drvdata(pdev, spdifrx); 916 917 ret = stm_spdifrx_parse_of(pdev, spdifrx); 918 if (ret) 919 return ret; 920 921 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 922 spdifrx->base, 923 spdifrx->regmap_conf); 924 if (IS_ERR(spdifrx->regmap)) { 925 dev_err(&pdev->dev, "Regmap init failed\n"); 926 return PTR_ERR(spdifrx->regmap); 927 } 928 929 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 930 dev_name(&pdev->dev), spdifrx); 931 if (ret) { 932 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 933 return ret; 934 } 935 936 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 937 if (!IS_ERR(rst)) { 938 reset_control_assert(rst); 939 udelay(2); 940 reset_control_deassert(rst); 941 } 942 943 ret = devm_snd_soc_register_component(&pdev->dev, 944 &stm32_spdifrx_component, 945 stm32_spdifrx_dai, 946 ARRAY_SIZE(stm32_spdifrx_dai)); 947 if (ret) 948 return ret; 949 950 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 951 if (ret) 952 goto error; 953 954 pcm_config = &stm32_spdifrx_pcm_config; 955 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 956 if (ret) { 957 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret); 958 goto error; 959 } 960 961 return 0; 962 963 error: 964 if (!IS_ERR(spdifrx->ctrl_chan)) 965 dma_release_channel(spdifrx->ctrl_chan); 966 if (spdifrx->dmab) 967 snd_dma_free_pages(spdifrx->dmab); 968 969 return ret; 970 } 971 972 static int stm32_spdifrx_remove(struct platform_device *pdev) 973 { 974 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 975 976 if (spdifrx->ctrl_chan) 977 dma_release_channel(spdifrx->ctrl_chan); 978 979 if (spdifrx->dmab) 980 snd_dma_free_pages(spdifrx->dmab); 981 982 return 0; 983 } 984 985 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 986 987 static struct platform_driver stm32_spdifrx_driver = { 988 .driver = { 989 .name = "st,stm32-spdifrx", 990 .of_match_table = stm32_spdifrx_ids, 991 }, 992 .probe = stm32_spdifrx_probe, 993 .remove = stm32_spdifrx_remove, 994 }; 995 996 module_platform_driver(stm32_spdifrx_driver); 997 998 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 999 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1000 MODULE_ALIAS("platform:stm32-spdifrx"); 1001 MODULE_LICENSE("GPL v2"); 1002