1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 21 /* SPDIF-rx Register Map */ 22 #define STM32_SPDIFRX_CR 0x00 23 #define STM32_SPDIFRX_IMR 0x04 24 #define STM32_SPDIFRX_SR 0x08 25 #define STM32_SPDIFRX_IFCR 0x0C 26 #define STM32_SPDIFRX_DR 0x10 27 #define STM32_SPDIFRX_CSR 0x14 28 #define STM32_SPDIFRX_DIR 0x18 29 #define STM32_SPDIFRX_VERR 0x3F4 30 #define STM32_SPDIFRX_IDR 0x3F8 31 #define STM32_SPDIFRX_SIDR 0x3FC 32 33 /* Bit definition for SPDIF_CR register */ 34 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 35 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 36 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 37 38 #define SPDIFRX_CR_RXDMAEN BIT(2) 39 #define SPDIFRX_CR_RXSTEO BIT(3) 40 41 #define SPDIFRX_CR_DRFMT_SHIFT 4 42 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 43 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 44 45 #define SPDIFRX_CR_PMSK BIT(6) 46 #define SPDIFRX_CR_VMSK BIT(7) 47 #define SPDIFRX_CR_CUMSK BIT(8) 48 #define SPDIFRX_CR_PTMSK BIT(9) 49 #define SPDIFRX_CR_CBDMAEN BIT(10) 50 #define SPDIFRX_CR_CHSEL_SHIFT 11 51 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 52 53 #define SPDIFRX_CR_NBTR_SHIFT 12 54 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 55 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 56 57 #define SPDIFRX_CR_WFA BIT(14) 58 59 #define SPDIFRX_CR_INSEL_SHIFT 16 60 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 61 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 62 63 #define SPDIFRX_CR_CKSEN_SHIFT 20 64 #define SPDIFRX_CR_CKSEN BIT(20) 65 #define SPDIFRX_CR_CKSBKPEN BIT(21) 66 67 /* Bit definition for SPDIFRX_IMR register */ 68 #define SPDIFRX_IMR_RXNEI BIT(0) 69 #define SPDIFRX_IMR_CSRNEIE BIT(1) 70 #define SPDIFRX_IMR_PERRIE BIT(2) 71 #define SPDIFRX_IMR_OVRIE BIT(3) 72 #define SPDIFRX_IMR_SBLKIE BIT(4) 73 #define SPDIFRX_IMR_SYNCDIE BIT(5) 74 #define SPDIFRX_IMR_IFEIE BIT(6) 75 76 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 77 78 /* Bit definition for SPDIFRX_SR register */ 79 #define SPDIFRX_SR_RXNE BIT(0) 80 #define SPDIFRX_SR_CSRNE BIT(1) 81 #define SPDIFRX_SR_PERR BIT(2) 82 #define SPDIFRX_SR_OVR BIT(3) 83 #define SPDIFRX_SR_SBD BIT(4) 84 #define SPDIFRX_SR_SYNCD BIT(5) 85 #define SPDIFRX_SR_FERR BIT(6) 86 #define SPDIFRX_SR_SERR BIT(7) 87 #define SPDIFRX_SR_TERR BIT(8) 88 89 #define SPDIFRX_SR_WIDTH5_SHIFT 16 90 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 91 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 92 93 /* Bit definition for SPDIFRX_IFCR register */ 94 #define SPDIFRX_IFCR_PERRCF BIT(2) 95 #define SPDIFRX_IFCR_OVRCF BIT(3) 96 #define SPDIFRX_IFCR_SBDCF BIT(4) 97 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 98 99 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 100 101 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 102 #define SPDIFRX_DR0_DR_SHIFT 0 103 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 104 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 105 106 #define SPDIFRX_DR0_PE BIT(24) 107 108 #define SPDIFRX_DR0_V BIT(25) 109 #define SPDIFRX_DR0_U BIT(26) 110 #define SPDIFRX_DR0_C BIT(27) 111 112 #define SPDIFRX_DR0_PT_SHIFT 28 113 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 114 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 115 116 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 117 #define SPDIFRX_DR1_PE BIT(0) 118 #define SPDIFRX_DR1_V BIT(1) 119 #define SPDIFRX_DR1_U BIT(2) 120 #define SPDIFRX_DR1_C BIT(3) 121 122 #define SPDIFRX_DR1_PT_SHIFT 4 123 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 124 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 125 126 #define SPDIFRX_DR1_DR_SHIFT 8 127 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 128 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 129 130 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 131 #define SPDIFRX_DR1_DRNL1_SHIFT 0 132 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 133 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 134 135 #define SPDIFRX_DR1_DRNL2_SHIFT 16 136 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 137 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 138 139 /* Bit definition for SPDIFRX_CSR register */ 140 #define SPDIFRX_CSR_USR_SHIFT 0 141 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 142 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 143 >> SPDIFRX_CSR_USR_SHIFT) 144 145 #define SPDIFRX_CSR_CS_SHIFT 16 146 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 147 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 148 >> SPDIFRX_CSR_CS_SHIFT) 149 150 #define SPDIFRX_CSR_SOB BIT(24) 151 152 /* Bit definition for SPDIFRX_DIR register */ 153 #define SPDIFRX_DIR_THI_SHIFT 0 154 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 155 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 156 157 #define SPDIFRX_DIR_TLO_SHIFT 16 158 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 159 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 160 161 #define SPDIFRX_SPDIFEN_DISABLE 0x0 162 #define SPDIFRX_SPDIFEN_SYNC 0x1 163 #define SPDIFRX_SPDIFEN_ENABLE 0x3 164 165 /* Bit definition for SPDIFRX_VERR register */ 166 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0) 167 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4) 168 169 /* Bit definition for SPDIFRX_IDR register */ 170 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0) 171 172 /* Bit definition for SPDIFRX_SIDR register */ 173 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0) 174 175 #define SPDIFRX_IPIDR_NUMBER 0x00130041 176 177 #define SPDIFRX_IN1 0x1 178 #define SPDIFRX_IN2 0x2 179 #define SPDIFRX_IN3 0x3 180 #define SPDIFRX_IN4 0x4 181 #define SPDIFRX_IN5 0x5 182 #define SPDIFRX_IN6 0x6 183 #define SPDIFRX_IN7 0x7 184 #define SPDIFRX_IN8 0x8 185 186 #define SPDIFRX_NBTR_NONE 0x0 187 #define SPDIFRX_NBTR_3 0x1 188 #define SPDIFRX_NBTR_15 0x2 189 #define SPDIFRX_NBTR_63 0x3 190 191 #define SPDIFRX_DRFMT_RIGHT 0x0 192 #define SPDIFRX_DRFMT_LEFT 0x1 193 #define SPDIFRX_DRFMT_PACKED 0x2 194 195 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 196 #define SPDIFRX_CS_BYTES_NB 24 197 #define SPDIFRX_UB_BYTES_NB 48 198 199 /* 200 * CSR register is retrieved as a 32 bits word 201 * It contains 1 channel status byte and 2 user data bytes 202 * 2 S/PDIF frames are acquired to get all CS/UB bits 203 */ 204 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 205 206 /** 207 * struct stm32_spdifrx_data - private data of SPDIFRX 208 * @pdev: device data pointer 209 * @base: mmio register base virtual address 210 * @regmap: SPDIFRX register map pointer 211 * @regmap_conf: SPDIFRX register map configuration pointer 212 * @cs_completion: channel status retrieving completion 213 * @kclk: kernel clock feeding the SPDIFRX clock generator 214 * @dma_params: dma configuration data for rx channel 215 * @substream: PCM substream data pointer 216 * @dmab: dma buffer info pointer 217 * @ctrl_chan: dma channel for S/PDIF control bits 218 * @desc:dma async transaction descriptor 219 * @slave_config: dma slave channel runtime config pointer 220 * @phys_addr: SPDIFRX registers physical base address 221 * @lock: synchronization enabling lock 222 * @irq_lock: prevent race condition with IRQ on stream state 223 * @cs: channel status buffer 224 * @ub: user data buffer 225 * @irq: SPDIFRX interrupt line 226 * @refcount: keep count of opened DMA channels 227 */ 228 struct stm32_spdifrx_data { 229 struct platform_device *pdev; 230 void __iomem *base; 231 struct regmap *regmap; 232 const struct regmap_config *regmap_conf; 233 struct completion cs_completion; 234 struct clk *kclk; 235 struct snd_dmaengine_dai_dma_data dma_params; 236 struct snd_pcm_substream *substream; 237 struct snd_dma_buffer *dmab; 238 struct dma_chan *ctrl_chan; 239 struct dma_async_tx_descriptor *desc; 240 struct dma_slave_config slave_config; 241 dma_addr_t phys_addr; 242 spinlock_t lock; /* Sync enabling lock */ 243 spinlock_t irq_lock; /* Prevent race condition on stream state */ 244 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 245 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 246 int irq; 247 int refcount; 248 }; 249 250 static void stm32_spdifrx_dma_complete(void *data) 251 { 252 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 253 struct platform_device *pdev = spdifrx->pdev; 254 u32 *p_start = (u32 *)spdifrx->dmab->area; 255 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 256 u32 *ptr = p_start; 257 u16 *ub_ptr = (short *)spdifrx->ub; 258 int i = 0; 259 260 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 261 SPDIFRX_CR_CBDMAEN, 262 (unsigned int)~SPDIFRX_CR_CBDMAEN); 263 264 if (!spdifrx->dmab->area) 265 return; 266 267 while (ptr <= p_end) { 268 if (*ptr & SPDIFRX_CSR_SOB) 269 break; 270 ptr++; 271 } 272 273 if (ptr > p_end) { 274 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 275 return; 276 } 277 278 while (i < SPDIFRX_CS_BYTES_NB) { 279 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 280 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 281 if (ptr > p_end) { 282 dev_err(&pdev->dev, "Failed to get channel status\n"); 283 return; 284 } 285 i++; 286 } 287 288 complete(&spdifrx->cs_completion); 289 } 290 291 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 292 { 293 dma_cookie_t cookie; 294 int err; 295 296 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 297 spdifrx->dmab->addr, 298 SPDIFRX_CSR_BUF_LENGTH, 299 DMA_DEV_TO_MEM, 300 DMA_CTRL_ACK); 301 if (!spdifrx->desc) 302 return -EINVAL; 303 304 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 305 spdifrx->desc->callback_param = spdifrx; 306 cookie = dmaengine_submit(spdifrx->desc); 307 err = dma_submit_error(cookie); 308 if (err) 309 return -EINVAL; 310 311 dma_async_issue_pending(spdifrx->ctrl_chan); 312 313 return 0; 314 } 315 316 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 317 { 318 dmaengine_terminate_async(spdifrx->ctrl_chan); 319 } 320 321 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 322 { 323 int cr, cr_mask, imr, ret; 324 unsigned long flags; 325 326 /* Enable IRQs */ 327 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 328 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 329 if (ret) 330 return ret; 331 332 spin_lock_irqsave(&spdifrx->lock, flags); 333 334 spdifrx->refcount++; 335 336 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 337 338 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 339 /* 340 * Start sync if SPDIFRX is still in idle state. 341 * SPDIFRX reception enabled when sync done 342 */ 343 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 344 345 /* 346 * SPDIFRX configuration: 347 * Wait for activity before starting sync process. This avoid 348 * to issue sync errors when spdif signal is missing on input. 349 * Preamble, CS, user, validity and parity error bits not copied 350 * to DR register. 351 */ 352 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 353 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 354 cr_mask = cr; 355 356 cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63); 357 cr_mask |= SPDIFRX_CR_NBTR_MASK; 358 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 359 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 360 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 361 cr_mask, cr); 362 if (ret < 0) 363 dev_err(&spdifrx->pdev->dev, 364 "Failed to start synchronization\n"); 365 } 366 367 spin_unlock_irqrestore(&spdifrx->lock, flags); 368 369 return ret; 370 } 371 372 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 373 { 374 int cr, cr_mask, reg; 375 unsigned long flags; 376 377 spin_lock_irqsave(&spdifrx->lock, flags); 378 379 if (--spdifrx->refcount) { 380 spin_unlock_irqrestore(&spdifrx->lock, flags); 381 return; 382 } 383 384 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 385 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 386 387 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 388 389 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 390 SPDIFRX_XIMR_MASK, 0); 391 392 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 393 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 394 395 /* dummy read to clear CSRNE and RXNE in status register */ 396 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 397 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 398 399 spin_unlock_irqrestore(&spdifrx->lock, flags); 400 } 401 402 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 403 struct stm32_spdifrx_data *spdifrx) 404 { 405 int ret; 406 407 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 408 if (IS_ERR(spdifrx->ctrl_chan)) { 409 if (PTR_ERR(spdifrx->ctrl_chan) != -EPROBE_DEFER) 410 dev_err(dev, "dma_request_slave_channel error %ld\n", 411 PTR_ERR(spdifrx->ctrl_chan)); 412 return PTR_ERR(spdifrx->ctrl_chan); 413 } 414 415 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 416 GFP_KERNEL); 417 if (!spdifrx->dmab) 418 return -ENOMEM; 419 420 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 421 spdifrx->dmab->dev.dev = dev; 422 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 423 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 424 if (ret < 0) { 425 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 426 return ret; 427 } 428 429 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 430 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 431 STM32_SPDIFRX_CSR); 432 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 433 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 434 spdifrx->slave_config.src_maxburst = 1; 435 436 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 437 &spdifrx->slave_config); 438 if (ret < 0) { 439 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 440 spdifrx->ctrl_chan = NULL; 441 } 442 443 return ret; 444 }; 445 446 static const char * const spdifrx_enum_input[] = { 447 "in0", "in1", "in2", "in3" 448 }; 449 450 /* By default CS bits are retrieved from channel A */ 451 static const char * const spdifrx_enum_cs_channel[] = { 452 "A", "B" 453 }; 454 455 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 456 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 457 spdifrx_enum_input); 458 459 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 460 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 461 spdifrx_enum_cs_channel); 462 463 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 464 struct snd_ctl_elem_info *uinfo) 465 { 466 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 467 uinfo->count = 1; 468 469 return 0; 470 } 471 472 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 473 struct snd_ctl_elem_info *uinfo) 474 { 475 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 476 uinfo->count = 1; 477 478 return 0; 479 } 480 481 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 482 { 483 int ret = 0; 484 485 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 486 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 487 488 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 489 if (ret < 0) 490 return ret; 491 492 ret = clk_prepare_enable(spdifrx->kclk); 493 if (ret) { 494 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 495 return ret; 496 } 497 498 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 499 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 500 if (ret < 0) 501 goto end; 502 503 ret = stm32_spdifrx_start_sync(spdifrx); 504 if (ret < 0) 505 goto end; 506 507 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 508 msecs_to_jiffies(100)) 509 <= 0) { 510 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n"); 511 ret = -EAGAIN; 512 } 513 514 stm32_spdifrx_stop(spdifrx); 515 stm32_spdifrx_dma_ctrl_stop(spdifrx); 516 517 end: 518 clk_disable_unprepare(spdifrx->kclk); 519 520 return ret; 521 } 522 523 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 524 struct snd_ctl_elem_value *ucontrol) 525 { 526 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 527 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 528 529 stm32_spdifrx_get_ctrl_data(spdifrx); 530 531 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 532 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 533 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 534 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 535 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 536 537 return 0; 538 } 539 540 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 541 struct snd_ctl_elem_value *ucontrol) 542 { 543 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 544 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 545 546 stm32_spdifrx_get_ctrl_data(spdifrx); 547 548 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 549 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 550 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 551 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 552 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 553 554 return 0; 555 } 556 557 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 558 /* Channel status control */ 559 { 560 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 561 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 562 .access = SNDRV_CTL_ELEM_ACCESS_READ | 563 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 564 .info = stm32_spdifrx_info, 565 .get = stm32_spdifrx_capture_get, 566 }, 567 /* User bits control */ 568 { 569 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 570 .name = "IEC958 User Bit Capture Default", 571 .access = SNDRV_CTL_ELEM_ACCESS_READ | 572 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 573 .info = stm32_spdifrx_ub_info, 574 .get = stm32_spdif_user_bits_get, 575 }, 576 }; 577 578 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 579 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 580 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 581 }; 582 583 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 584 { 585 int ret; 586 587 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 588 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 589 if (ret < 0) 590 return ret; 591 592 return snd_soc_add_component_controls(cpu_dai->component, 593 stm32_spdifrx_ctrls, 594 ARRAY_SIZE(stm32_spdifrx_ctrls)); 595 } 596 597 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 598 { 599 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 600 601 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 602 STM32_SPDIFRX_DR); 603 spdifrx->dma_params.maxburst = 1; 604 605 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 606 607 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 608 } 609 610 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 611 { 612 switch (reg) { 613 case STM32_SPDIFRX_CR: 614 case STM32_SPDIFRX_IMR: 615 case STM32_SPDIFRX_SR: 616 case STM32_SPDIFRX_IFCR: 617 case STM32_SPDIFRX_DR: 618 case STM32_SPDIFRX_CSR: 619 case STM32_SPDIFRX_DIR: 620 case STM32_SPDIFRX_VERR: 621 case STM32_SPDIFRX_IDR: 622 case STM32_SPDIFRX_SIDR: 623 return true; 624 default: 625 return false; 626 } 627 } 628 629 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 630 { 631 switch (reg) { 632 case STM32_SPDIFRX_DR: 633 case STM32_SPDIFRX_CSR: 634 case STM32_SPDIFRX_SR: 635 case STM32_SPDIFRX_DIR: 636 return true; 637 default: 638 return false; 639 } 640 } 641 642 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 643 { 644 switch (reg) { 645 case STM32_SPDIFRX_CR: 646 case STM32_SPDIFRX_IMR: 647 case STM32_SPDIFRX_IFCR: 648 return true; 649 default: 650 return false; 651 } 652 } 653 654 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 655 .reg_bits = 32, 656 .reg_stride = 4, 657 .val_bits = 32, 658 .max_register = STM32_SPDIFRX_SIDR, 659 .readable_reg = stm32_spdifrx_readable_reg, 660 .volatile_reg = stm32_spdifrx_volatile_reg, 661 .writeable_reg = stm32_spdifrx_writeable_reg, 662 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1, 663 .fast_io = true, 664 .cache_type = REGCACHE_FLAT, 665 }; 666 667 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 668 { 669 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 670 struct platform_device *pdev = spdifrx->pdev; 671 unsigned int cr, mask, sr, imr; 672 unsigned int flags, sync_state; 673 int err = 0, err_xrun = 0; 674 675 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 676 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 677 678 mask = imr & SPDIFRX_XIMR_MASK; 679 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 680 if (mask & SPDIFRX_IMR_IFEIE) 681 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 682 683 flags = sr & mask; 684 if (!flags) { 685 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 686 sr, imr); 687 return IRQ_NONE; 688 } 689 690 /* Clear IRQs */ 691 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 692 SPDIFRX_XIFCR_MASK, flags); 693 694 if (flags & SPDIFRX_SR_PERR) { 695 dev_dbg(&pdev->dev, "Parity error\n"); 696 err_xrun = 1; 697 } 698 699 if (flags & SPDIFRX_SR_OVR) { 700 dev_dbg(&pdev->dev, "Overrun error\n"); 701 err_xrun = 1; 702 } 703 704 if (flags & SPDIFRX_SR_SBD) 705 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 706 707 if (flags & SPDIFRX_SR_SYNCD) { 708 dev_dbg(&pdev->dev, "Synchronization done\n"); 709 710 /* Enable spdifrx */ 711 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 712 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 713 SPDIFRX_CR_SPDIFEN_MASK, cr); 714 } 715 716 if (flags & SPDIFRX_SR_FERR) { 717 dev_dbg(&pdev->dev, "Frame error\n"); 718 err = 1; 719 } 720 721 if (flags & SPDIFRX_SR_SERR) { 722 dev_dbg(&pdev->dev, "Synchronization error\n"); 723 err = 1; 724 } 725 726 if (flags & SPDIFRX_SR_TERR) { 727 dev_dbg(&pdev->dev, "Timeout error\n"); 728 err = 1; 729 } 730 731 if (err) { 732 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 733 sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) && 734 SPDIFRX_SPDIFEN_SYNC; 735 736 /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */ 737 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 738 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 739 SPDIFRX_CR_SPDIFEN_MASK, cr); 740 741 /* If SPDIFRX was in STATE_SYNC, retry synchro */ 742 if (sync_state) { 743 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 744 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 745 SPDIFRX_CR_SPDIFEN_MASK, cr); 746 return IRQ_HANDLED; 747 } 748 749 spin_lock(&spdifrx->irq_lock); 750 if (spdifrx->substream) 751 snd_pcm_stop(spdifrx->substream, 752 SNDRV_PCM_STATE_DISCONNECTED); 753 spin_unlock(&spdifrx->irq_lock); 754 755 return IRQ_HANDLED; 756 } 757 758 spin_lock(&spdifrx->irq_lock); 759 if (err_xrun && spdifrx->substream) 760 snd_pcm_stop_xrun(spdifrx->substream); 761 spin_unlock(&spdifrx->irq_lock); 762 763 return IRQ_HANDLED; 764 } 765 766 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 767 struct snd_soc_dai *cpu_dai) 768 { 769 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 770 unsigned long flags; 771 int ret; 772 773 spin_lock_irqsave(&spdifrx->irq_lock, flags); 774 spdifrx->substream = substream; 775 spin_unlock_irqrestore(&spdifrx->irq_lock, flags); 776 777 ret = clk_prepare_enable(spdifrx->kclk); 778 if (ret) 779 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 780 781 return ret; 782 } 783 784 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 785 struct snd_pcm_hw_params *params, 786 struct snd_soc_dai *cpu_dai) 787 { 788 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 789 int data_size = params_width(params); 790 int fmt; 791 792 switch (data_size) { 793 case 16: 794 fmt = SPDIFRX_DRFMT_PACKED; 795 break; 796 case 32: 797 fmt = SPDIFRX_DRFMT_LEFT; 798 break; 799 default: 800 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 801 return -EINVAL; 802 } 803 804 /* 805 * Set buswidth to 4 bytes for all data formats. 806 * Packed format: transfer 2 x 2 bytes samples 807 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 808 */ 809 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 810 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 811 812 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 813 SPDIFRX_CR_DRFMT_MASK, 814 SPDIFRX_CR_DRFMTSET(fmt)); 815 } 816 817 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 818 struct snd_soc_dai *cpu_dai) 819 { 820 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 821 int ret = 0; 822 823 switch (cmd) { 824 case SNDRV_PCM_TRIGGER_START: 825 case SNDRV_PCM_TRIGGER_RESUME: 826 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 827 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 828 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 829 830 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 831 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 832 833 ret = stm32_spdifrx_start_sync(spdifrx); 834 break; 835 case SNDRV_PCM_TRIGGER_SUSPEND: 836 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 837 case SNDRV_PCM_TRIGGER_STOP: 838 stm32_spdifrx_stop(spdifrx); 839 break; 840 default: 841 return -EINVAL; 842 } 843 844 return ret; 845 } 846 847 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 848 struct snd_soc_dai *cpu_dai) 849 { 850 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 851 unsigned long flags; 852 853 spin_lock_irqsave(&spdifrx->irq_lock, flags); 854 spdifrx->substream = NULL; 855 spin_unlock_irqrestore(&spdifrx->irq_lock, flags); 856 857 clk_disable_unprepare(spdifrx->kclk); 858 } 859 860 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 861 .startup = stm32_spdifrx_startup, 862 .hw_params = stm32_spdifrx_hw_params, 863 .trigger = stm32_spdifrx_trigger, 864 .shutdown = stm32_spdifrx_shutdown, 865 }; 866 867 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 868 { 869 .probe = stm32_spdifrx_dai_probe, 870 .capture = { 871 .stream_name = "CPU-Capture", 872 .channels_min = 1, 873 .channels_max = 2, 874 .rates = SNDRV_PCM_RATE_8000_192000, 875 .formats = SNDRV_PCM_FMTBIT_S32_LE | 876 SNDRV_PCM_FMTBIT_S16_LE, 877 }, 878 .ops = &stm32_spdifrx_pcm_dai_ops, 879 } 880 }; 881 882 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 883 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 884 .buffer_bytes_max = 8 * PAGE_SIZE, 885 .period_bytes_min = 1024, 886 .period_bytes_max = 4 * PAGE_SIZE, 887 .periods_min = 2, 888 .periods_max = 8, 889 }; 890 891 static const struct snd_soc_component_driver stm32_spdifrx_component = { 892 .name = "stm32-spdifrx", 893 }; 894 895 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 896 .pcm_hardware = &stm32_spdifrx_pcm_hw, 897 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 898 }; 899 900 static const struct of_device_id stm32_spdifrx_ids[] = { 901 { 902 .compatible = "st,stm32h7-spdifrx", 903 .data = &stm32_h7_spdifrx_regmap_conf 904 }, 905 {} 906 }; 907 908 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 909 struct stm32_spdifrx_data *spdifrx) 910 { 911 struct device_node *np = pdev->dev.of_node; 912 const struct of_device_id *of_id; 913 struct resource *res; 914 915 if (!np) 916 return -ENODEV; 917 918 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 919 if (of_id) 920 spdifrx->regmap_conf = 921 (const struct regmap_config *)of_id->data; 922 else 923 return -EINVAL; 924 925 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 926 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 927 if (IS_ERR(spdifrx->base)) 928 return PTR_ERR(spdifrx->base); 929 930 spdifrx->phys_addr = res->start; 931 932 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 933 if (IS_ERR(spdifrx->kclk)) { 934 if (PTR_ERR(spdifrx->kclk) != -EPROBE_DEFER) 935 dev_err(&pdev->dev, "Could not get kclk: %ld\n", 936 PTR_ERR(spdifrx->kclk)); 937 return PTR_ERR(spdifrx->kclk); 938 } 939 940 spdifrx->irq = platform_get_irq(pdev, 0); 941 if (spdifrx->irq < 0) 942 return spdifrx->irq; 943 944 return 0; 945 } 946 947 static int stm32_spdifrx_remove(struct platform_device *pdev) 948 { 949 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 950 951 if (spdifrx->ctrl_chan) 952 dma_release_channel(spdifrx->ctrl_chan); 953 954 if (spdifrx->dmab) 955 snd_dma_free_pages(spdifrx->dmab); 956 957 snd_dmaengine_pcm_unregister(&pdev->dev); 958 snd_soc_unregister_component(&pdev->dev); 959 960 return 0; 961 } 962 963 static int stm32_spdifrx_probe(struct platform_device *pdev) 964 { 965 struct stm32_spdifrx_data *spdifrx; 966 struct reset_control *rst; 967 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 968 u32 ver, idr; 969 int ret; 970 971 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 972 if (!spdifrx) 973 return -ENOMEM; 974 975 spdifrx->pdev = pdev; 976 init_completion(&spdifrx->cs_completion); 977 spin_lock_init(&spdifrx->lock); 978 spin_lock_init(&spdifrx->irq_lock); 979 980 platform_set_drvdata(pdev, spdifrx); 981 982 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 983 if (ret) 984 return ret; 985 986 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 987 spdifrx->base, 988 spdifrx->regmap_conf); 989 if (IS_ERR(spdifrx->regmap)) { 990 if (PTR_ERR(spdifrx->regmap) != -EPROBE_DEFER) 991 dev_err(&pdev->dev, "Regmap init error %ld\n", 992 PTR_ERR(spdifrx->regmap)); 993 return PTR_ERR(spdifrx->regmap); 994 } 995 996 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 997 dev_name(&pdev->dev), spdifrx); 998 if (ret) { 999 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1000 return ret; 1001 } 1002 1003 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1004 if (IS_ERR(rst)) { 1005 if (PTR_ERR(rst) != -EPROBE_DEFER) 1006 dev_err(&pdev->dev, "Reset controller error %ld\n", 1007 PTR_ERR(rst)); 1008 return PTR_ERR(rst); 1009 } 1010 reset_control_assert(rst); 1011 udelay(2); 1012 reset_control_deassert(rst); 1013 1014 pcm_config = &stm32_spdifrx_pcm_config; 1015 ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 1016 if (ret) { 1017 if (ret != -EPROBE_DEFER) 1018 dev_err(&pdev->dev, "PCM DMA register error %d\n", ret); 1019 return ret; 1020 } 1021 1022 ret = snd_soc_register_component(&pdev->dev, 1023 &stm32_spdifrx_component, 1024 stm32_spdifrx_dai, 1025 ARRAY_SIZE(stm32_spdifrx_dai)); 1026 if (ret) { 1027 snd_dmaengine_pcm_unregister(&pdev->dev); 1028 return ret; 1029 } 1030 1031 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 1032 if (ret) 1033 goto error; 1034 1035 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr); 1036 if (ret) 1037 goto error; 1038 1039 if (idr == SPDIFRX_IPIDR_NUMBER) { 1040 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver); 1041 if (ret) 1042 goto error; 1043 1044 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n", 1045 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver), 1046 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver)); 1047 } 1048 1049 return ret; 1050 1051 error: 1052 stm32_spdifrx_remove(pdev); 1053 1054 return ret; 1055 } 1056 1057 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 1058 1059 #ifdef CONFIG_PM_SLEEP 1060 static int stm32_spdifrx_suspend(struct device *dev) 1061 { 1062 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1063 1064 regcache_cache_only(spdifrx->regmap, true); 1065 regcache_mark_dirty(spdifrx->regmap); 1066 1067 return 0; 1068 } 1069 1070 static int stm32_spdifrx_resume(struct device *dev) 1071 { 1072 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1073 1074 regcache_cache_only(spdifrx->regmap, false); 1075 1076 return regcache_sync(spdifrx->regmap); 1077 } 1078 #endif /* CONFIG_PM_SLEEP */ 1079 1080 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1081 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1082 }; 1083 1084 static struct platform_driver stm32_spdifrx_driver = { 1085 .driver = { 1086 .name = "st,stm32-spdifrx", 1087 .of_match_table = stm32_spdifrx_ids, 1088 .pm = &stm32_spdifrx_pm_ops, 1089 }, 1090 .probe = stm32_spdifrx_probe, 1091 .remove = stm32_spdifrx_remove, 1092 }; 1093 1094 module_platform_driver(stm32_spdifrx_driver); 1095 1096 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1097 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1098 MODULE_ALIAS("platform:stm32-spdifrx"); 1099 MODULE_LICENSE("GPL v2"); 1100