1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 3 * 4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/bitfield.h> 20 #include <linux/clk.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/module.h> 24 #include <linux/of_platform.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regmap.h> 27 #include <linux/reset.h> 28 29 #include <sound/dmaengine_pcm.h> 30 #include <sound/pcm_params.h> 31 32 /* SPDIF-rx Register Map */ 33 #define STM32_SPDIFRX_CR 0x00 34 #define STM32_SPDIFRX_IMR 0x04 35 #define STM32_SPDIFRX_SR 0x08 36 #define STM32_SPDIFRX_IFCR 0x0C 37 #define STM32_SPDIFRX_DR 0x10 38 #define STM32_SPDIFRX_CSR 0x14 39 #define STM32_SPDIFRX_DIR 0x18 40 #define STM32_SPDIFRX_VERR 0x3F4 41 #define STM32_SPDIFRX_IDR 0x3F8 42 #define STM32_SPDIFRX_SIDR 0x3FC 43 44 /* Bit definition for SPDIF_CR register */ 45 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 46 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 47 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 48 49 #define SPDIFRX_CR_RXDMAEN BIT(2) 50 #define SPDIFRX_CR_RXSTEO BIT(3) 51 52 #define SPDIFRX_CR_DRFMT_SHIFT 4 53 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 54 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 55 56 #define SPDIFRX_CR_PMSK BIT(6) 57 #define SPDIFRX_CR_VMSK BIT(7) 58 #define SPDIFRX_CR_CUMSK BIT(8) 59 #define SPDIFRX_CR_PTMSK BIT(9) 60 #define SPDIFRX_CR_CBDMAEN BIT(10) 61 #define SPDIFRX_CR_CHSEL_SHIFT 11 62 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 63 64 #define SPDIFRX_CR_NBTR_SHIFT 12 65 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 66 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 67 68 #define SPDIFRX_CR_WFA BIT(14) 69 70 #define SPDIFRX_CR_INSEL_SHIFT 16 71 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 72 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 73 74 #define SPDIFRX_CR_CKSEN_SHIFT 20 75 #define SPDIFRX_CR_CKSEN BIT(20) 76 #define SPDIFRX_CR_CKSBKPEN BIT(21) 77 78 /* Bit definition for SPDIFRX_IMR register */ 79 #define SPDIFRX_IMR_RXNEI BIT(0) 80 #define SPDIFRX_IMR_CSRNEIE BIT(1) 81 #define SPDIFRX_IMR_PERRIE BIT(2) 82 #define SPDIFRX_IMR_OVRIE BIT(3) 83 #define SPDIFRX_IMR_SBLKIE BIT(4) 84 #define SPDIFRX_IMR_SYNCDIE BIT(5) 85 #define SPDIFRX_IMR_IFEIE BIT(6) 86 87 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 88 89 /* Bit definition for SPDIFRX_SR register */ 90 #define SPDIFRX_SR_RXNE BIT(0) 91 #define SPDIFRX_SR_CSRNE BIT(1) 92 #define SPDIFRX_SR_PERR BIT(2) 93 #define SPDIFRX_SR_OVR BIT(3) 94 #define SPDIFRX_SR_SBD BIT(4) 95 #define SPDIFRX_SR_SYNCD BIT(5) 96 #define SPDIFRX_SR_FERR BIT(6) 97 #define SPDIFRX_SR_SERR BIT(7) 98 #define SPDIFRX_SR_TERR BIT(8) 99 100 #define SPDIFRX_SR_WIDTH5_SHIFT 16 101 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 102 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 103 104 /* Bit definition for SPDIFRX_IFCR register */ 105 #define SPDIFRX_IFCR_PERRCF BIT(2) 106 #define SPDIFRX_IFCR_OVRCF BIT(3) 107 #define SPDIFRX_IFCR_SBDCF BIT(4) 108 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 109 110 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 111 112 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 113 #define SPDIFRX_DR0_DR_SHIFT 0 114 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 115 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 116 117 #define SPDIFRX_DR0_PE BIT(24) 118 119 #define SPDIFRX_DR0_V BIT(25) 120 #define SPDIFRX_DR0_U BIT(26) 121 #define SPDIFRX_DR0_C BIT(27) 122 123 #define SPDIFRX_DR0_PT_SHIFT 28 124 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 125 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 126 127 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 128 #define SPDIFRX_DR1_PE BIT(0) 129 #define SPDIFRX_DR1_V BIT(1) 130 #define SPDIFRX_DR1_U BIT(2) 131 #define SPDIFRX_DR1_C BIT(3) 132 133 #define SPDIFRX_DR1_PT_SHIFT 4 134 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 135 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 136 137 #define SPDIFRX_DR1_DR_SHIFT 8 138 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 139 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 140 141 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 142 #define SPDIFRX_DR1_DRNL1_SHIFT 0 143 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 144 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 145 146 #define SPDIFRX_DR1_DRNL2_SHIFT 16 147 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 148 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 149 150 /* Bit definition for SPDIFRX_CSR register */ 151 #define SPDIFRX_CSR_USR_SHIFT 0 152 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 153 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 154 >> SPDIFRX_CSR_USR_SHIFT) 155 156 #define SPDIFRX_CSR_CS_SHIFT 16 157 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 158 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 159 >> SPDIFRX_CSR_CS_SHIFT) 160 161 #define SPDIFRX_CSR_SOB BIT(24) 162 163 /* Bit definition for SPDIFRX_DIR register */ 164 #define SPDIFRX_DIR_THI_SHIFT 0 165 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 166 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 167 168 #define SPDIFRX_DIR_TLO_SHIFT 16 169 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 170 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 171 172 #define SPDIFRX_SPDIFEN_DISABLE 0x0 173 #define SPDIFRX_SPDIFEN_SYNC 0x1 174 #define SPDIFRX_SPDIFEN_ENABLE 0x3 175 176 /* Bit definition for SPDIFRX_VERR register */ 177 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0) 178 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4) 179 180 /* Bit definition for SPDIFRX_IDR register */ 181 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0) 182 183 /* Bit definition for SPDIFRX_SIDR register */ 184 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0) 185 186 #define SPDIFRX_IPIDR_NUMBER 0x00130041 187 188 #define SPDIFRX_IN1 0x1 189 #define SPDIFRX_IN2 0x2 190 #define SPDIFRX_IN3 0x3 191 #define SPDIFRX_IN4 0x4 192 #define SPDIFRX_IN5 0x5 193 #define SPDIFRX_IN6 0x6 194 #define SPDIFRX_IN7 0x7 195 #define SPDIFRX_IN8 0x8 196 197 #define SPDIFRX_NBTR_NONE 0x0 198 #define SPDIFRX_NBTR_3 0x1 199 #define SPDIFRX_NBTR_15 0x2 200 #define SPDIFRX_NBTR_63 0x3 201 202 #define SPDIFRX_DRFMT_RIGHT 0x0 203 #define SPDIFRX_DRFMT_LEFT 0x1 204 #define SPDIFRX_DRFMT_PACKED 0x2 205 206 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 207 #define SPDIFRX_CS_BYTES_NB 24 208 #define SPDIFRX_UB_BYTES_NB 48 209 210 /* 211 * CSR register is retrieved as a 32 bits word 212 * It contains 1 channel status byte and 2 user data bytes 213 * 2 S/PDIF frames are acquired to get all CS/UB bits 214 */ 215 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 216 217 /** 218 * struct stm32_spdifrx_data - private data of SPDIFRX 219 * @pdev: device data pointer 220 * @base: mmio register base virtual address 221 * @regmap: SPDIFRX register map pointer 222 * @regmap_conf: SPDIFRX register map configuration pointer 223 * @cs_completion: channel status retrieving completion 224 * @kclk: kernel clock feeding the SPDIFRX clock generator 225 * @dma_params: dma configuration data for rx channel 226 * @substream: PCM substream data pointer 227 * @dmab: dma buffer info pointer 228 * @ctrl_chan: dma channel for S/PDIF control bits 229 * @desc:dma async transaction descriptor 230 * @slave_config: dma slave channel runtime config pointer 231 * @phys_addr: SPDIFRX registers physical base address 232 * @lock: synchronization enabling lock 233 * @cs: channel status buffer 234 * @ub: user data buffer 235 * @irq: SPDIFRX interrupt line 236 * @refcount: keep count of opened DMA channels 237 */ 238 struct stm32_spdifrx_data { 239 struct platform_device *pdev; 240 void __iomem *base; 241 struct regmap *regmap; 242 const struct regmap_config *regmap_conf; 243 struct completion cs_completion; 244 struct clk *kclk; 245 struct snd_dmaengine_dai_dma_data dma_params; 246 struct snd_pcm_substream *substream; 247 struct snd_dma_buffer *dmab; 248 struct dma_chan *ctrl_chan; 249 struct dma_async_tx_descriptor *desc; 250 struct dma_slave_config slave_config; 251 dma_addr_t phys_addr; 252 spinlock_t lock; /* Sync enabling lock */ 253 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 254 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 255 int irq; 256 int refcount; 257 }; 258 259 static void stm32_spdifrx_dma_complete(void *data) 260 { 261 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 262 struct platform_device *pdev = spdifrx->pdev; 263 u32 *p_start = (u32 *)spdifrx->dmab->area; 264 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 265 u32 *ptr = p_start; 266 u16 *ub_ptr = (short *)spdifrx->ub; 267 int i = 0; 268 269 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 270 SPDIFRX_CR_CBDMAEN, 271 (unsigned int)~SPDIFRX_CR_CBDMAEN); 272 273 if (!spdifrx->dmab->area) 274 return; 275 276 while (ptr <= p_end) { 277 if (*ptr & SPDIFRX_CSR_SOB) 278 break; 279 ptr++; 280 } 281 282 if (ptr > p_end) { 283 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 284 return; 285 } 286 287 while (i < SPDIFRX_CS_BYTES_NB) { 288 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 289 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 290 if (ptr > p_end) { 291 dev_err(&pdev->dev, "Failed to get channel status\n"); 292 return; 293 } 294 i++; 295 } 296 297 complete(&spdifrx->cs_completion); 298 } 299 300 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 301 { 302 dma_cookie_t cookie; 303 int err; 304 305 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 306 spdifrx->dmab->addr, 307 SPDIFRX_CSR_BUF_LENGTH, 308 DMA_DEV_TO_MEM, 309 DMA_CTRL_ACK); 310 if (!spdifrx->desc) 311 return -EINVAL; 312 313 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 314 spdifrx->desc->callback_param = spdifrx; 315 cookie = dmaengine_submit(spdifrx->desc); 316 err = dma_submit_error(cookie); 317 if (err) 318 return -EINVAL; 319 320 dma_async_issue_pending(spdifrx->ctrl_chan); 321 322 return 0; 323 } 324 325 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 326 { 327 dmaengine_terminate_async(spdifrx->ctrl_chan); 328 } 329 330 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 331 { 332 int cr, cr_mask, imr, ret; 333 334 /* Enable IRQs */ 335 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 336 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 337 if (ret) 338 return ret; 339 340 spin_lock(&spdifrx->lock); 341 342 spdifrx->refcount++; 343 344 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 345 346 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 347 /* 348 * Start sync if SPDIFRX is still in idle state. 349 * SPDIFRX reception enabled when sync done 350 */ 351 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 352 353 /* 354 * SPDIFRX configuration: 355 * Wait for activity before starting sync process. This avoid 356 * to issue sync errors when spdif signal is missing on input. 357 * Preamble, CS, user, validity and parity error bits not copied 358 * to DR register. 359 */ 360 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 361 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 362 cr_mask = cr; 363 364 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 365 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 366 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 367 cr_mask, cr); 368 if (ret < 0) 369 dev_err(&spdifrx->pdev->dev, 370 "Failed to start synchronization\n"); 371 } 372 373 spin_unlock(&spdifrx->lock); 374 375 return ret; 376 } 377 378 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 379 { 380 int cr, cr_mask, reg; 381 382 spin_lock(&spdifrx->lock); 383 384 if (--spdifrx->refcount) { 385 spin_unlock(&spdifrx->lock); 386 return; 387 } 388 389 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 390 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 391 392 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 393 394 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 395 SPDIFRX_XIMR_MASK, 0); 396 397 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 398 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 399 400 /* dummy read to clear CSRNE and RXNE in status register */ 401 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 402 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 403 404 spin_unlock(&spdifrx->lock); 405 } 406 407 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 408 struct stm32_spdifrx_data *spdifrx) 409 { 410 int ret; 411 412 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 413 if (IS_ERR(spdifrx->ctrl_chan)) { 414 dev_err(dev, "dma_request_slave_channel failed\n"); 415 return PTR_ERR(spdifrx->ctrl_chan); 416 } 417 418 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 419 GFP_KERNEL); 420 if (!spdifrx->dmab) 421 return -ENOMEM; 422 423 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 424 spdifrx->dmab->dev.dev = dev; 425 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 426 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 427 if (ret < 0) { 428 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 429 return ret; 430 } 431 432 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 433 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 434 STM32_SPDIFRX_CSR); 435 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 436 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 437 spdifrx->slave_config.src_maxburst = 1; 438 439 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 440 &spdifrx->slave_config); 441 if (ret < 0) { 442 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 443 spdifrx->ctrl_chan = NULL; 444 } 445 446 return ret; 447 }; 448 449 static const char * const spdifrx_enum_input[] = { 450 "in0", "in1", "in2", "in3" 451 }; 452 453 /* By default CS bits are retrieved from channel A */ 454 static const char * const spdifrx_enum_cs_channel[] = { 455 "A", "B" 456 }; 457 458 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 459 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 460 spdifrx_enum_input); 461 462 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 463 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 464 spdifrx_enum_cs_channel); 465 466 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 467 struct snd_ctl_elem_info *uinfo) 468 { 469 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 470 uinfo->count = 1; 471 472 return 0; 473 } 474 475 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 476 struct snd_ctl_elem_info *uinfo) 477 { 478 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 479 uinfo->count = 1; 480 481 return 0; 482 } 483 484 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 485 { 486 int ret = 0; 487 488 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 489 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 490 491 pinctrl_pm_select_default_state(&spdifrx->pdev->dev); 492 493 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 494 if (ret < 0) 495 return ret; 496 497 ret = clk_prepare_enable(spdifrx->kclk); 498 if (ret) { 499 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 500 return ret; 501 } 502 503 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 504 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 505 if (ret < 0) 506 goto end; 507 508 ret = stm32_spdifrx_start_sync(spdifrx); 509 if (ret < 0) 510 goto end; 511 512 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 513 msecs_to_jiffies(100)) 514 <= 0) { 515 dev_err(&spdifrx->pdev->dev, "Failed to get control data\n"); 516 ret = -EAGAIN; 517 } 518 519 stm32_spdifrx_stop(spdifrx); 520 stm32_spdifrx_dma_ctrl_stop(spdifrx); 521 522 end: 523 clk_disable_unprepare(spdifrx->kclk); 524 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev); 525 526 return ret; 527 } 528 529 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 530 struct snd_ctl_elem_value *ucontrol) 531 { 532 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 533 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 534 535 stm32_spdifrx_get_ctrl_data(spdifrx); 536 537 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 538 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 539 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 540 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 541 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 542 543 return 0; 544 } 545 546 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 547 struct snd_ctl_elem_value *ucontrol) 548 { 549 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 550 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 551 552 stm32_spdifrx_get_ctrl_data(spdifrx); 553 554 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 555 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 556 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 557 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 558 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 559 560 return 0; 561 } 562 563 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 564 /* Channel status control */ 565 { 566 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 567 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 568 .access = SNDRV_CTL_ELEM_ACCESS_READ | 569 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 570 .info = stm32_spdifrx_info, 571 .get = stm32_spdifrx_capture_get, 572 }, 573 /* User bits control */ 574 { 575 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 576 .name = "IEC958 User Bit Capture Default", 577 .access = SNDRV_CTL_ELEM_ACCESS_READ | 578 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 579 .info = stm32_spdifrx_ub_info, 580 .get = stm32_spdif_user_bits_get, 581 }, 582 }; 583 584 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 585 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 586 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 587 }; 588 589 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 590 { 591 int ret; 592 593 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 594 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 595 if (ret < 0) 596 return ret; 597 598 return snd_soc_add_component_controls(cpu_dai->component, 599 stm32_spdifrx_ctrls, 600 ARRAY_SIZE(stm32_spdifrx_ctrls)); 601 } 602 603 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 604 { 605 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 606 607 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 608 STM32_SPDIFRX_DR); 609 spdifrx->dma_params.maxburst = 1; 610 611 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 612 613 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 614 } 615 616 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 617 { 618 switch (reg) { 619 case STM32_SPDIFRX_CR: 620 case STM32_SPDIFRX_IMR: 621 case STM32_SPDIFRX_SR: 622 case STM32_SPDIFRX_IFCR: 623 case STM32_SPDIFRX_DR: 624 case STM32_SPDIFRX_CSR: 625 case STM32_SPDIFRX_DIR: 626 case STM32_SPDIFRX_VERR: 627 case STM32_SPDIFRX_IDR: 628 case STM32_SPDIFRX_SIDR: 629 return true; 630 default: 631 return false; 632 } 633 } 634 635 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 636 { 637 switch (reg) { 638 case STM32_SPDIFRX_DR: 639 case STM32_SPDIFRX_CSR: 640 case STM32_SPDIFRX_SR: 641 case STM32_SPDIFRX_DIR: 642 return true; 643 default: 644 return false; 645 } 646 } 647 648 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 649 { 650 switch (reg) { 651 case STM32_SPDIFRX_CR: 652 case STM32_SPDIFRX_IMR: 653 case STM32_SPDIFRX_IFCR: 654 return true; 655 default: 656 return false; 657 } 658 } 659 660 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 661 .reg_bits = 32, 662 .reg_stride = 4, 663 .val_bits = 32, 664 .max_register = STM32_SPDIFRX_SIDR, 665 .readable_reg = stm32_spdifrx_readable_reg, 666 .volatile_reg = stm32_spdifrx_volatile_reg, 667 .writeable_reg = stm32_spdifrx_writeable_reg, 668 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1, 669 .fast_io = true, 670 .cache_type = REGCACHE_FLAT, 671 }; 672 673 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 674 { 675 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 676 struct snd_pcm_substream *substream = spdifrx->substream; 677 struct platform_device *pdev = spdifrx->pdev; 678 unsigned int cr, mask, sr, imr; 679 unsigned int flags; 680 int err = 0, err_xrun = 0; 681 682 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 683 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 684 685 mask = imr & SPDIFRX_XIMR_MASK; 686 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 687 if (mask & SPDIFRX_IMR_IFEIE) 688 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 689 690 flags = sr & mask; 691 if (!flags) { 692 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 693 sr, imr); 694 return IRQ_NONE; 695 } 696 697 /* Clear IRQs */ 698 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 699 SPDIFRX_XIFCR_MASK, flags); 700 701 if (flags & SPDIFRX_SR_PERR) { 702 dev_dbg(&pdev->dev, "Parity error\n"); 703 err_xrun = 1; 704 } 705 706 if (flags & SPDIFRX_SR_OVR) { 707 dev_dbg(&pdev->dev, "Overrun error\n"); 708 err_xrun = 1; 709 } 710 711 if (flags & SPDIFRX_SR_SBD) 712 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 713 714 if (flags & SPDIFRX_SR_SYNCD) { 715 dev_dbg(&pdev->dev, "Synchronization done\n"); 716 717 /* Enable spdifrx */ 718 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 719 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 720 SPDIFRX_CR_SPDIFEN_MASK, cr); 721 } 722 723 if (flags & SPDIFRX_SR_FERR) { 724 dev_dbg(&pdev->dev, "Frame error\n"); 725 err = 1; 726 } 727 728 if (flags & SPDIFRX_SR_SERR) { 729 dev_dbg(&pdev->dev, "Synchronization error\n"); 730 err = 1; 731 } 732 733 if (flags & SPDIFRX_SR_TERR) { 734 dev_dbg(&pdev->dev, "Timeout error\n"); 735 err = 1; 736 } 737 738 if (err) { 739 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */ 740 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 741 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 742 SPDIFRX_CR_SPDIFEN_MASK, cr); 743 744 if (substream) 745 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); 746 747 return IRQ_HANDLED; 748 } 749 750 if (err_xrun && substream) 751 snd_pcm_stop_xrun(substream); 752 753 return IRQ_HANDLED; 754 } 755 756 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 757 struct snd_soc_dai *cpu_dai) 758 { 759 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 760 int ret; 761 762 spdifrx->substream = substream; 763 764 ret = clk_prepare_enable(spdifrx->kclk); 765 if (ret) 766 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 767 768 return ret; 769 } 770 771 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 772 struct snd_pcm_hw_params *params, 773 struct snd_soc_dai *cpu_dai) 774 { 775 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 776 int data_size = params_width(params); 777 int fmt; 778 779 switch (data_size) { 780 case 16: 781 fmt = SPDIFRX_DRFMT_PACKED; 782 break; 783 case 32: 784 fmt = SPDIFRX_DRFMT_LEFT; 785 break; 786 default: 787 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 788 return -EINVAL; 789 } 790 791 /* 792 * Set buswidth to 4 bytes for all data formats. 793 * Packed format: transfer 2 x 2 bytes samples 794 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 795 */ 796 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 797 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 798 799 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 800 SPDIFRX_CR_DRFMT_MASK, 801 SPDIFRX_CR_DRFMTSET(fmt)); 802 } 803 804 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 805 struct snd_soc_dai *cpu_dai) 806 { 807 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 808 int ret = 0; 809 810 switch (cmd) { 811 case SNDRV_PCM_TRIGGER_START: 812 case SNDRV_PCM_TRIGGER_RESUME: 813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 814 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 815 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 816 817 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 818 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 819 820 ret = stm32_spdifrx_start_sync(spdifrx); 821 break; 822 case SNDRV_PCM_TRIGGER_SUSPEND: 823 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 824 case SNDRV_PCM_TRIGGER_STOP: 825 stm32_spdifrx_stop(spdifrx); 826 break; 827 default: 828 return -EINVAL; 829 } 830 831 return ret; 832 } 833 834 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 835 struct snd_soc_dai *cpu_dai) 836 { 837 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 838 839 spdifrx->substream = NULL; 840 clk_disable_unprepare(spdifrx->kclk); 841 } 842 843 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 844 .startup = stm32_spdifrx_startup, 845 .hw_params = stm32_spdifrx_hw_params, 846 .trigger = stm32_spdifrx_trigger, 847 .shutdown = stm32_spdifrx_shutdown, 848 }; 849 850 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 851 { 852 .probe = stm32_spdifrx_dai_probe, 853 .capture = { 854 .stream_name = "CPU-Capture", 855 .channels_min = 1, 856 .channels_max = 2, 857 .rates = SNDRV_PCM_RATE_8000_192000, 858 .formats = SNDRV_PCM_FMTBIT_S32_LE | 859 SNDRV_PCM_FMTBIT_S16_LE, 860 }, 861 .ops = &stm32_spdifrx_pcm_dai_ops, 862 } 863 }; 864 865 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 866 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 867 .buffer_bytes_max = 8 * PAGE_SIZE, 868 .period_bytes_max = 2048, /* MDMA constraint */ 869 .periods_min = 2, 870 .periods_max = 8, 871 }; 872 873 static const struct snd_soc_component_driver stm32_spdifrx_component = { 874 .name = "stm32-spdifrx", 875 }; 876 877 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 878 .pcm_hardware = &stm32_spdifrx_pcm_hw, 879 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 880 }; 881 882 static const struct of_device_id stm32_spdifrx_ids[] = { 883 { 884 .compatible = "st,stm32h7-spdifrx", 885 .data = &stm32_h7_spdifrx_regmap_conf 886 }, 887 {} 888 }; 889 890 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 891 struct stm32_spdifrx_data *spdifrx) 892 { 893 struct device_node *np = pdev->dev.of_node; 894 const struct of_device_id *of_id; 895 struct resource *res; 896 897 if (!np) 898 return -ENODEV; 899 900 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 901 if (of_id) 902 spdifrx->regmap_conf = 903 (const struct regmap_config *)of_id->data; 904 else 905 return -EINVAL; 906 907 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 908 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 909 if (IS_ERR(spdifrx->base)) 910 return PTR_ERR(spdifrx->base); 911 912 spdifrx->phys_addr = res->start; 913 914 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 915 if (IS_ERR(spdifrx->kclk)) { 916 dev_err(&pdev->dev, "Could not get kclk\n"); 917 return PTR_ERR(spdifrx->kclk); 918 } 919 920 spdifrx->irq = platform_get_irq(pdev, 0); 921 if (spdifrx->irq < 0) { 922 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name); 923 return spdifrx->irq; 924 } 925 926 return 0; 927 } 928 929 static int stm32_spdifrx_probe(struct platform_device *pdev) 930 { 931 struct stm32_spdifrx_data *spdifrx; 932 struct reset_control *rst; 933 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 934 u32 ver, idr; 935 int ret; 936 937 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 938 if (!spdifrx) 939 return -ENOMEM; 940 941 spdifrx->pdev = pdev; 942 init_completion(&spdifrx->cs_completion); 943 spin_lock_init(&spdifrx->lock); 944 945 platform_set_drvdata(pdev, spdifrx); 946 947 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 948 if (ret) 949 return ret; 950 951 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 952 spdifrx->base, 953 spdifrx->regmap_conf); 954 if (IS_ERR(spdifrx->regmap)) { 955 dev_err(&pdev->dev, "Regmap init failed\n"); 956 return PTR_ERR(spdifrx->regmap); 957 } 958 959 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 960 dev_name(&pdev->dev), spdifrx); 961 if (ret) { 962 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 963 return ret; 964 } 965 966 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 967 if (!IS_ERR(rst)) { 968 reset_control_assert(rst); 969 udelay(2); 970 reset_control_deassert(rst); 971 } 972 973 ret = devm_snd_soc_register_component(&pdev->dev, 974 &stm32_spdifrx_component, 975 stm32_spdifrx_dai, 976 ARRAY_SIZE(stm32_spdifrx_dai)); 977 if (ret) 978 return ret; 979 980 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 981 if (ret) 982 goto error; 983 984 pcm_config = &stm32_spdifrx_pcm_config; 985 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 986 if (ret) { 987 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret); 988 goto error; 989 } 990 991 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr); 992 if (ret) 993 goto error; 994 995 if (idr == SPDIFRX_IPIDR_NUMBER) { 996 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver); 997 998 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n", 999 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver), 1000 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver)); 1001 } 1002 1003 return ret; 1004 1005 error: 1006 if (!IS_ERR(spdifrx->ctrl_chan)) 1007 dma_release_channel(spdifrx->ctrl_chan); 1008 if (spdifrx->dmab) 1009 snd_dma_free_pages(spdifrx->dmab); 1010 1011 return ret; 1012 } 1013 1014 static int stm32_spdifrx_remove(struct platform_device *pdev) 1015 { 1016 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 1017 1018 if (spdifrx->ctrl_chan) 1019 dma_release_channel(spdifrx->ctrl_chan); 1020 1021 if (spdifrx->dmab) 1022 snd_dma_free_pages(spdifrx->dmab); 1023 1024 return 0; 1025 } 1026 1027 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 1028 1029 #ifdef CONFIG_PM_SLEEP 1030 static int stm32_spdifrx_suspend(struct device *dev) 1031 { 1032 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1033 1034 regcache_cache_only(spdifrx->regmap, true); 1035 regcache_mark_dirty(spdifrx->regmap); 1036 1037 return 0; 1038 } 1039 1040 static int stm32_spdifrx_resume(struct device *dev) 1041 { 1042 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1043 1044 regcache_cache_only(spdifrx->regmap, false); 1045 1046 return regcache_sync(spdifrx->regmap); 1047 } 1048 #endif /* CONFIG_PM_SLEEP */ 1049 1050 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1051 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1052 }; 1053 1054 static struct platform_driver stm32_spdifrx_driver = { 1055 .driver = { 1056 .name = "st,stm32-spdifrx", 1057 .of_match_table = stm32_spdifrx_ids, 1058 .pm = &stm32_spdifrx_pm_ops, 1059 }, 1060 .probe = stm32_spdifrx_probe, 1061 .remove = stm32_spdifrx_remove, 1062 }; 1063 1064 module_platform_driver(stm32_spdifrx_driver); 1065 1066 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1067 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1068 MODULE_ALIAS("platform:stm32-spdifrx"); 1069 MODULE_LICENSE("GPL v2"); 1070