1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/regmap.h> 25 26 #include <sound/core.h> 27 #include <sound/dmaengine_pcm.h> 28 #include <sound/pcm_params.h> 29 30 #include "stm32_sai.h" 31 32 #define SAI_FREE_PROTOCOL 0x0 33 34 #define SAI_SLOT_SIZE_AUTO 0x0 35 #define SAI_SLOT_SIZE_16 0x1 36 #define SAI_SLOT_SIZE_32 0x2 37 38 #define SAI_DATASIZE_8 0x2 39 #define SAI_DATASIZE_10 0x3 40 #define SAI_DATASIZE_16 0x4 41 #define SAI_DATASIZE_20 0x5 42 #define SAI_DATASIZE_24 0x6 43 #define SAI_DATASIZE_32 0x7 44 45 #define STM_SAI_FIFO_SIZE 8 46 #define STM_SAI_DAI_NAME_SIZE 15 47 48 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 49 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 50 51 #define STM_SAI_A_ID 0x0 52 #define STM_SAI_B_ID 0x1 53 54 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 55 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 56 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 57 58 #define SAI_SYNC_NONE 0x0 59 #define SAI_SYNC_INTERNAL 0x1 60 #define SAI_SYNC_EXTERNAL 0x2 61 62 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 63 64 /** 65 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 66 * @pdev: device data pointer 67 * @regmap: SAI register map pointer 68 * @regmap_config: SAI sub block register map configuration pointer 69 * @dma_params: dma configuration data for rx or tx channel 70 * @cpu_dai_drv: DAI driver data pointer 71 * @cpu_dai: DAI runtime data pointer 72 * @substream: PCM substream data pointer 73 * @pdata: SAI block parent data pointer 74 * @np_sync_provider: synchronization provider node 75 * @sai_ck: kernel clock feeding the SAI clock generator 76 * @phys_addr: SAI registers physical base address 77 * @mclk_rate: SAI block master clock frequency (Hz). set at init 78 * @id: SAI sub block id corresponding to sub-block A or B 79 * @dir: SAI block direction (playback or capture). set at init 80 * @master: SAI block mode flag. (true=master, false=slave) set at init 81 * @fmt: SAI block format. relevant only for custom protocols. set at init 82 * @sync: SAI block synchronization mode. (none, internal or external) 83 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 84 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 85 * @fs_length: frame synchronization length. depends on protocol settings 86 * @slots: rx or tx slot number 87 * @slot_width: rx or tx slot width in bits 88 * @slot_mask: rx or tx active slots mask. set at init or at runtime 89 * @data_size: PCM data width. corresponds to PCM substream width. 90 */ 91 struct stm32_sai_sub_data { 92 struct platform_device *pdev; 93 struct regmap *regmap; 94 const struct regmap_config *regmap_config; 95 struct snd_dmaengine_dai_dma_data dma_params; 96 struct snd_soc_dai_driver *cpu_dai_drv; 97 struct snd_soc_dai *cpu_dai; 98 struct snd_pcm_substream *substream; 99 struct stm32_sai_data *pdata; 100 struct device_node *np_sync_provider; 101 struct clk *sai_ck; 102 dma_addr_t phys_addr; 103 unsigned int mclk_rate; 104 unsigned int id; 105 int dir; 106 bool master; 107 int fmt; 108 int sync; 109 int synco; 110 int synci; 111 int fs_length; 112 int slots; 113 int slot_width; 114 int slot_mask; 115 int data_size; 116 }; 117 118 enum stm32_sai_fifo_th { 119 STM_SAI_FIFO_TH_EMPTY, 120 STM_SAI_FIFO_TH_QUARTER, 121 STM_SAI_FIFO_TH_HALF, 122 STM_SAI_FIFO_TH_3_QUARTER, 123 STM_SAI_FIFO_TH_FULL, 124 }; 125 126 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 127 { 128 switch (reg) { 129 case STM_SAI_CR1_REGX: 130 case STM_SAI_CR2_REGX: 131 case STM_SAI_FRCR_REGX: 132 case STM_SAI_SLOTR_REGX: 133 case STM_SAI_IMR_REGX: 134 case STM_SAI_SR_REGX: 135 case STM_SAI_CLRFR_REGX: 136 case STM_SAI_DR_REGX: 137 case STM_SAI_PDMCR_REGX: 138 case STM_SAI_PDMLY_REGX: 139 return true; 140 default: 141 return false; 142 } 143 } 144 145 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 146 { 147 switch (reg) { 148 case STM_SAI_DR_REGX: 149 return true; 150 default: 151 return false; 152 } 153 } 154 155 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 156 { 157 switch (reg) { 158 case STM_SAI_CR1_REGX: 159 case STM_SAI_CR2_REGX: 160 case STM_SAI_FRCR_REGX: 161 case STM_SAI_SLOTR_REGX: 162 case STM_SAI_IMR_REGX: 163 case STM_SAI_SR_REGX: 164 case STM_SAI_CLRFR_REGX: 165 case STM_SAI_DR_REGX: 166 case STM_SAI_PDMCR_REGX: 167 case STM_SAI_PDMLY_REGX: 168 return true; 169 default: 170 return false; 171 } 172 } 173 174 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 175 .reg_bits = 32, 176 .reg_stride = 4, 177 .val_bits = 32, 178 .max_register = STM_SAI_DR_REGX, 179 .readable_reg = stm32_sai_sub_readable_reg, 180 .volatile_reg = stm32_sai_sub_volatile_reg, 181 .writeable_reg = stm32_sai_sub_writeable_reg, 182 .fast_io = true, 183 }; 184 185 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 186 .reg_bits = 32, 187 .reg_stride = 4, 188 .val_bits = 32, 189 .max_register = STM_SAI_PDMLY_REGX, 190 .readable_reg = stm32_sai_sub_readable_reg, 191 .volatile_reg = stm32_sai_sub_volatile_reg, 192 .writeable_reg = stm32_sai_sub_writeable_reg, 193 .fast_io = true, 194 }; 195 196 static irqreturn_t stm32_sai_isr(int irq, void *devid) 197 { 198 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 199 struct platform_device *pdev = sai->pdev; 200 unsigned int sr, imr, flags; 201 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 202 203 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 204 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 205 206 flags = sr & imr; 207 if (!flags) 208 return IRQ_NONE; 209 210 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 211 SAI_XCLRFR_MASK); 212 213 if (!sai->substream) { 214 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 215 return IRQ_NONE; 216 } 217 218 if (flags & SAI_XIMR_OVRUDRIE) { 219 dev_err(&pdev->dev, "IRQ %s\n", 220 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 221 status = SNDRV_PCM_STATE_XRUN; 222 } 223 224 if (flags & SAI_XIMR_MUTEDETIE) 225 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 226 227 if (flags & SAI_XIMR_WCKCFGIE) { 228 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 229 status = SNDRV_PCM_STATE_DISCONNECTED; 230 } 231 232 if (flags & SAI_XIMR_CNRDYIE) 233 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 234 235 if (flags & SAI_XIMR_AFSDETIE) { 236 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 237 status = SNDRV_PCM_STATE_XRUN; 238 } 239 240 if (flags & SAI_XIMR_LFSDETIE) { 241 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 242 status = SNDRV_PCM_STATE_XRUN; 243 } 244 245 if (status != SNDRV_PCM_STATE_RUNNING) { 246 snd_pcm_stream_lock(sai->substream); 247 snd_pcm_stop(sai->substream, SNDRV_PCM_STATE_XRUN); 248 snd_pcm_stream_unlock(sai->substream); 249 } 250 251 return IRQ_HANDLED; 252 } 253 254 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 255 int clk_id, unsigned int freq, int dir) 256 { 257 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 258 int ret; 259 260 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) { 261 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 262 SAI_XCR1_NODIV, 263 (unsigned int)~SAI_XCR1_NODIV); 264 if (ret < 0) 265 return ret; 266 267 sai->mclk_rate = freq; 268 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 269 } 270 271 return 0; 272 } 273 274 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 275 u32 rx_mask, int slots, int slot_width) 276 { 277 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 278 int slotr, slotr_mask, slot_size; 279 280 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 281 tx_mask, rx_mask, slots, slot_width); 282 283 switch (slot_width) { 284 case 16: 285 slot_size = SAI_SLOT_SIZE_16; 286 break; 287 case 32: 288 slot_size = SAI_SLOT_SIZE_32; 289 break; 290 default: 291 slot_size = SAI_SLOT_SIZE_AUTO; 292 break; 293 } 294 295 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 296 SAI_XSLOTR_NBSLOT_SET(slots - 1); 297 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 298 299 /* tx/rx mask set in machine init, if slot number defined in DT */ 300 if (STM_SAI_IS_PLAYBACK(sai)) { 301 sai->slot_mask = tx_mask; 302 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 303 } 304 305 if (STM_SAI_IS_CAPTURE(sai)) { 306 sai->slot_mask = rx_mask; 307 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 308 } 309 310 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 311 312 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 313 314 sai->slot_width = slot_width; 315 sai->slots = slots; 316 317 return 0; 318 } 319 320 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 321 { 322 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 323 int cr1, frcr = 0; 324 int cr1_mask, frcr_mask = 0; 325 int ret; 326 327 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 328 329 cr1_mask = SAI_XCR1_PRTCFG_MASK; 330 cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 331 332 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 333 /* SCK active high for all protocols */ 334 case SND_SOC_DAIFMT_I2S: 335 cr1 |= SAI_XCR1_CKSTR; 336 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 337 break; 338 /* Left justified */ 339 case SND_SOC_DAIFMT_MSB: 340 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 341 break; 342 /* Right justified */ 343 case SND_SOC_DAIFMT_LSB: 344 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 345 break; 346 case SND_SOC_DAIFMT_DSP_A: 347 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 348 break; 349 case SND_SOC_DAIFMT_DSP_B: 350 frcr |= SAI_XFRCR_FSPOL; 351 break; 352 default: 353 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 354 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 355 return -EINVAL; 356 } 357 358 cr1_mask |= SAI_XCR1_CKSTR; 359 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 360 SAI_XFRCR_FSDEF; 361 362 /* DAI clock strobing. Invert setting previously set */ 363 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 364 case SND_SOC_DAIFMT_NB_NF: 365 break; 366 case SND_SOC_DAIFMT_IB_NF: 367 cr1 ^= SAI_XCR1_CKSTR; 368 break; 369 case SND_SOC_DAIFMT_NB_IF: 370 frcr ^= SAI_XFRCR_FSPOL; 371 break; 372 case SND_SOC_DAIFMT_IB_IF: 373 /* Invert fs & sck */ 374 cr1 ^= SAI_XCR1_CKSTR; 375 frcr ^= SAI_XFRCR_FSPOL; 376 break; 377 default: 378 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 379 fmt & SND_SOC_DAIFMT_INV_MASK); 380 return -EINVAL; 381 } 382 cr1_mask |= SAI_XCR1_CKSTR; 383 frcr_mask |= SAI_XFRCR_FSPOL; 384 385 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 386 387 /* DAI clock master masks */ 388 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 389 case SND_SOC_DAIFMT_CBM_CFM: 390 /* codec is master */ 391 cr1 |= SAI_XCR1_SLAVE; 392 sai->master = false; 393 break; 394 case SND_SOC_DAIFMT_CBS_CFS: 395 sai->master = true; 396 break; 397 default: 398 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 399 fmt & SND_SOC_DAIFMT_MASTER_MASK); 400 return -EINVAL; 401 } 402 403 /* Set slave mode if sub-block is synchronized with another SAI */ 404 if (sai->sync) { 405 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 406 cr1 |= SAI_XCR1_SLAVE; 407 sai->master = false; 408 } 409 410 cr1_mask |= SAI_XCR1_SLAVE; 411 412 /* do not generate master by default */ 413 cr1 |= SAI_XCR1_NODIV; 414 cr1_mask |= SAI_XCR1_NODIV; 415 416 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 417 if (ret < 0) { 418 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 419 return ret; 420 } 421 422 sai->fmt = fmt; 423 424 return 0; 425 } 426 427 static int stm32_sai_startup(struct snd_pcm_substream *substream, 428 struct snd_soc_dai *cpu_dai) 429 { 430 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 431 int imr, cr2, ret; 432 433 sai->substream = substream; 434 435 ret = clk_prepare_enable(sai->sai_ck); 436 if (ret < 0) { 437 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 438 return ret; 439 } 440 441 /* Enable ITs */ 442 443 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 444 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 445 446 imr = SAI_XIMR_OVRUDRIE; 447 if (STM_SAI_IS_CAPTURE(sai)) { 448 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 449 if (cr2 & SAI_XCR2_MUTECNT_MASK) 450 imr |= SAI_XIMR_MUTEDETIE; 451 } 452 453 if (sai->master) 454 imr |= SAI_XIMR_WCKCFGIE; 455 else 456 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 457 458 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 459 SAI_XIMR_MASK, imr); 460 461 return 0; 462 } 463 464 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 465 struct snd_pcm_substream *substream, 466 struct snd_pcm_hw_params *params) 467 { 468 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 469 int cr1, cr1_mask, ret; 470 471 /* 472 * DMA bursts increment is set to 4 words. 473 * SAI fifo threshold is set to half fifo, to keep enough space 474 * for DMA incoming bursts. 475 */ 476 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 477 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 478 SAI_XCR2_FFLUSH | 479 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 480 481 /* Mode, data format and channel config */ 482 cr1_mask = SAI_XCR1_DS_MASK; 483 switch (params_format(params)) { 484 case SNDRV_PCM_FORMAT_S8: 485 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 486 break; 487 case SNDRV_PCM_FORMAT_S16_LE: 488 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 489 break; 490 case SNDRV_PCM_FORMAT_S32_LE: 491 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 492 break; 493 default: 494 dev_err(cpu_dai->dev, "Data format not supported"); 495 return -EINVAL; 496 } 497 498 cr1_mask |= SAI_XCR1_MONO; 499 if ((sai->slots == 2) && (params_channels(params) == 1)) 500 cr1 |= SAI_XCR1_MONO; 501 502 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 503 if (ret < 0) { 504 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 505 return ret; 506 } 507 508 return 0; 509 } 510 511 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 512 { 513 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 514 int slotr, slot_sz; 515 516 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 517 518 /* 519 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 520 * By default slot width = data size, if not forced from DT 521 */ 522 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 523 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 524 sai->slot_width = sai->data_size; 525 526 if (sai->slot_width < sai->data_size) { 527 dev_err(cpu_dai->dev, 528 "Data size %d larger than slot width\n", 529 sai->data_size); 530 return -EINVAL; 531 } 532 533 /* Slot number is set to 2, if not specified in DT */ 534 if (!sai->slots) 535 sai->slots = 2; 536 537 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 538 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 539 SAI_XSLOTR_NBSLOT_MASK, 540 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 541 542 /* Set default slots mask if not already set from DT */ 543 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 544 sai->slot_mask = (1 << sai->slots) - 1; 545 regmap_update_bits(sai->regmap, 546 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 547 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 548 } 549 550 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 551 sai->slots, sai->slot_width); 552 553 return 0; 554 } 555 556 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 557 { 558 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 559 int fs_active, offset, format; 560 int frcr, frcr_mask; 561 562 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 563 sai->fs_length = sai->slot_width * sai->slots; 564 565 fs_active = sai->fs_length / 2; 566 if ((format == SND_SOC_DAIFMT_DSP_A) || 567 (format == SND_SOC_DAIFMT_DSP_B)) 568 fs_active = 1; 569 570 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 571 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 572 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 573 574 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 575 sai->fs_length, fs_active); 576 577 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 578 579 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 580 offset = sai->slot_width - sai->data_size; 581 582 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 583 SAI_XSLOTR_FBOFF_MASK, 584 SAI_XSLOTR_FBOFF_SET(offset)); 585 } 586 } 587 588 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 589 struct snd_pcm_hw_params *params) 590 { 591 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 592 int cr1, mask, div = 0; 593 int sai_clk_rate, mclk_ratio, den, ret; 594 int version = sai->pdata->conf->version; 595 596 if (!sai->mclk_rate) { 597 dev_err(cpu_dai->dev, "Mclk rate is null\n"); 598 return -EINVAL; 599 } 600 601 if (!(params_rate(params) % 11025)) 602 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k); 603 else 604 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k); 605 sai_clk_rate = clk_get_rate(sai->sai_ck); 606 607 if (STM_SAI_IS_F4(sai->pdata)) { 608 /* 609 * mclk_rate = 256 * fs 610 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 611 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 612 */ 613 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) 614 div = DIV_ROUND_CLOSEST(sai_clk_rate, 615 2 * sai->mclk_rate); 616 } else { 617 /* 618 * TDM mode : 619 * mclk on 620 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 621 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 622 * mclk off 623 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 624 * Note: NOMCK/NODIV correspond to same bit. 625 */ 626 if (sai->mclk_rate) { 627 mclk_ratio = sai->mclk_rate / params_rate(params); 628 if (mclk_ratio != 256) { 629 if (mclk_ratio == 512) { 630 mask = SAI_XCR1_OSR; 631 cr1 = SAI_XCR1_OSR; 632 } else { 633 dev_err(cpu_dai->dev, 634 "Wrong mclk ratio %d\n", 635 mclk_ratio); 636 return -EINVAL; 637 } 638 } 639 div = DIV_ROUND_CLOSEST(sai_clk_rate, sai->mclk_rate); 640 } else { 641 /* mclk-fs not set, master clock not active. NOMCK=1 */ 642 den = sai->fs_length * params_rate(params); 643 div = DIV_ROUND_CLOSEST(sai_clk_rate, den); 644 } 645 } 646 647 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 648 dev_err(cpu_dai->dev, "Divider %d out of range\n", div); 649 return -EINVAL; 650 } 651 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div); 652 653 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 654 cr1 = SAI_XCR1_MCKDIV_SET(div); 655 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 656 if (ret < 0) { 657 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 658 return ret; 659 } 660 661 return 0; 662 } 663 664 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 665 struct snd_pcm_hw_params *params, 666 struct snd_soc_dai *cpu_dai) 667 { 668 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 669 int ret; 670 671 sai->data_size = params_width(params); 672 673 ret = stm32_sai_set_slots(cpu_dai); 674 if (ret < 0) 675 return ret; 676 stm32_sai_set_frame(cpu_dai); 677 678 ret = stm32_sai_set_config(cpu_dai, substream, params); 679 if (ret) 680 return ret; 681 682 if (sai->master) 683 ret = stm32_sai_configure_clock(cpu_dai, params); 684 685 return ret; 686 } 687 688 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 689 struct snd_soc_dai *cpu_dai) 690 { 691 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 692 int ret; 693 694 switch (cmd) { 695 case SNDRV_PCM_TRIGGER_START: 696 case SNDRV_PCM_TRIGGER_RESUME: 697 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 698 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 699 700 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 701 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 702 703 /* Enable SAI */ 704 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 705 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 706 if (ret < 0) 707 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 708 break; 709 case SNDRV_PCM_TRIGGER_SUSPEND: 710 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 711 case SNDRV_PCM_TRIGGER_STOP: 712 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 713 714 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 715 SAI_XIMR_MASK, 0); 716 717 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 718 SAI_XCR1_SAIEN, 719 (unsigned int)~SAI_XCR1_SAIEN); 720 721 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 722 SAI_XCR1_DMAEN, 723 (unsigned int)~SAI_XCR1_DMAEN); 724 if (ret < 0) 725 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 726 break; 727 default: 728 return -EINVAL; 729 } 730 731 return ret; 732 } 733 734 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 735 struct snd_soc_dai *cpu_dai) 736 { 737 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 738 739 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 740 741 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 742 SAI_XCR1_NODIV); 743 744 clk_disable_unprepare(sai->sai_ck); 745 sai->substream = NULL; 746 } 747 748 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 749 { 750 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 751 int cr1 = 0, cr1_mask; 752 753 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 754 /* 755 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 756 * as it allows bytes, half-word and words transfers. (See DMA fifos 757 * constraints). 758 */ 759 sai->dma_params.maxburst = 4; 760 /* Buswidth will be set by framework at runtime */ 761 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 762 763 if (STM_SAI_IS_PLAYBACK(sai)) 764 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 765 else 766 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 767 768 cr1_mask = SAI_XCR1_RX_TX; 769 if (STM_SAI_IS_CAPTURE(sai)) 770 cr1 |= SAI_XCR1_RX_TX; 771 772 /* Configure synchronization */ 773 if (sai->sync == SAI_SYNC_EXTERNAL) { 774 /* Configure synchro client and provider */ 775 sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 776 sai->synco, sai->synci); 777 } 778 779 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 780 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 781 782 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 783 } 784 785 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 786 .set_sysclk = stm32_sai_set_sysclk, 787 .set_fmt = stm32_sai_set_dai_fmt, 788 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 789 .startup = stm32_sai_startup, 790 .hw_params = stm32_sai_hw_params, 791 .trigger = stm32_sai_trigger, 792 .shutdown = stm32_sai_shutdown, 793 }; 794 795 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 796 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 797 .buffer_bytes_max = 8 * PAGE_SIZE, 798 .period_bytes_min = 1024, /* 5ms at 48kHz */ 799 .period_bytes_max = PAGE_SIZE, 800 .periods_min = 2, 801 .periods_max = 8, 802 }; 803 804 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 805 { 806 .probe = stm32_sai_dai_probe, 807 .id = 1, /* avoid call to fmt_single_name() */ 808 .playback = { 809 .channels_min = 1, 810 .channels_max = 2, 811 .rate_min = 8000, 812 .rate_max = 192000, 813 .rates = SNDRV_PCM_RATE_CONTINUOUS, 814 /* DMA does not support 24 bits transfers */ 815 .formats = 816 SNDRV_PCM_FMTBIT_S8 | 817 SNDRV_PCM_FMTBIT_S16_LE | 818 SNDRV_PCM_FMTBIT_S32_LE, 819 }, 820 .ops = &stm32_sai_pcm_dai_ops, 821 } 822 }; 823 824 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 825 { 826 .probe = stm32_sai_dai_probe, 827 .id = 1, /* avoid call to fmt_single_name() */ 828 .capture = { 829 .channels_min = 1, 830 .channels_max = 2, 831 .rate_min = 8000, 832 .rate_max = 192000, 833 .rates = SNDRV_PCM_RATE_CONTINUOUS, 834 /* DMA does not support 24 bits transfers */ 835 .formats = 836 SNDRV_PCM_FMTBIT_S8 | 837 SNDRV_PCM_FMTBIT_S16_LE | 838 SNDRV_PCM_FMTBIT_S32_LE, 839 }, 840 .ops = &stm32_sai_pcm_dai_ops, 841 } 842 }; 843 844 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 845 .pcm_hardware = &stm32_sai_pcm_hw, 846 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 847 }; 848 849 static const struct snd_soc_component_driver stm32_component = { 850 .name = "stm32-sai", 851 }; 852 853 static const struct of_device_id stm32_sai_sub_ids[] = { 854 { .compatible = "st,stm32-sai-sub-a", 855 .data = (void *)STM_SAI_A_ID}, 856 { .compatible = "st,stm32-sai-sub-b", 857 .data = (void *)STM_SAI_B_ID}, 858 {} 859 }; 860 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 861 862 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 863 struct stm32_sai_sub_data *sai) 864 { 865 struct device_node *np = pdev->dev.of_node; 866 struct resource *res; 867 void __iomem *base; 868 struct of_phandle_args args; 869 int ret; 870 871 if (!np) 872 return -ENODEV; 873 874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 875 base = devm_ioremap_resource(&pdev->dev, res); 876 if (IS_ERR(base)) 877 return PTR_ERR(base); 878 879 sai->phys_addr = res->start; 880 881 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 882 /* Note: PDM registers not available for H7 sub-block B */ 883 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 884 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 885 886 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 887 base, sai->regmap_config); 888 if (IS_ERR(sai->regmap)) { 889 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 890 return PTR_ERR(sai->regmap); 891 } 892 893 /* Get direction property */ 894 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 895 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 896 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 897 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 898 } else { 899 dev_err(&pdev->dev, "Unsupported direction\n"); 900 return -EINVAL; 901 } 902 903 /* Get synchronization property */ 904 args.np = NULL; 905 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 906 if (ret < 0 && ret != -ENOENT) { 907 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 908 return ret; 909 } 910 911 sai->sync = SAI_SYNC_NONE; 912 if (args.np) { 913 if (args.np == np) { 914 dev_err(&pdev->dev, "%s sync own reference\n", 915 np->name); 916 of_node_put(args.np); 917 return -EINVAL; 918 } 919 920 sai->np_sync_provider = of_get_parent(args.np); 921 if (!sai->np_sync_provider) { 922 dev_err(&pdev->dev, "%s parent node not found\n", 923 np->name); 924 of_node_put(args.np); 925 return -ENODEV; 926 } 927 928 sai->sync = SAI_SYNC_INTERNAL; 929 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 930 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 931 dev_err(&pdev->dev, 932 "External synchro not supported\n"); 933 of_node_put(args.np); 934 return -EINVAL; 935 } 936 sai->sync = SAI_SYNC_EXTERNAL; 937 938 sai->synci = args.args[0]; 939 if (sai->synci < 1 || 940 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 941 dev_err(&pdev->dev, "Wrong SAI index\n"); 942 of_node_put(args.np); 943 return -EINVAL; 944 } 945 946 if (of_property_match_string(args.np, "compatible", 947 "st,stm32-sai-sub-a") >= 0) 948 sai->synco = STM_SAI_SYNC_OUT_A; 949 950 if (of_property_match_string(args.np, "compatible", 951 "st,stm32-sai-sub-b") >= 0) 952 sai->synco = STM_SAI_SYNC_OUT_B; 953 954 if (!sai->synco) { 955 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 956 of_node_put(args.np); 957 return -EINVAL; 958 } 959 } 960 961 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 962 pdev->name, args.np->full_name); 963 } 964 965 of_node_put(args.np); 966 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 967 if (IS_ERR(sai->sai_ck)) { 968 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 969 return PTR_ERR(sai->sai_ck); 970 } 971 972 return 0; 973 } 974 975 static int stm32_sai_sub_dais_init(struct platform_device *pdev, 976 struct stm32_sai_sub_data *sai) 977 { 978 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 979 sizeof(struct snd_soc_dai_driver), 980 GFP_KERNEL); 981 if (!sai->cpu_dai_drv) 982 return -ENOMEM; 983 984 sai->cpu_dai_drv->name = dev_name(&pdev->dev); 985 if (STM_SAI_IS_PLAYBACK(sai)) { 986 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 987 sizeof(stm32_sai_playback_dai)); 988 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 989 } else { 990 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 991 sizeof(stm32_sai_capture_dai)); 992 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 993 } 994 995 return 0; 996 } 997 998 static int stm32_sai_sub_probe(struct platform_device *pdev) 999 { 1000 struct stm32_sai_sub_data *sai; 1001 const struct of_device_id *of_id; 1002 int ret; 1003 1004 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1005 if (!sai) 1006 return -ENOMEM; 1007 1008 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1009 if (!of_id) 1010 return -EINVAL; 1011 sai->id = (uintptr_t)of_id->data; 1012 1013 sai->pdev = pdev; 1014 platform_set_drvdata(pdev, sai); 1015 1016 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1017 if (!sai->pdata) { 1018 dev_err(&pdev->dev, "Parent device data not available\n"); 1019 return -EINVAL; 1020 } 1021 1022 ret = stm32_sai_sub_parse_of(pdev, sai); 1023 if (ret) 1024 return ret; 1025 1026 ret = stm32_sai_sub_dais_init(pdev, sai); 1027 if (ret) 1028 return ret; 1029 1030 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1031 IRQF_SHARED, dev_name(&pdev->dev), sai); 1032 if (ret) { 1033 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1034 return ret; 1035 } 1036 1037 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1038 sai->cpu_dai_drv, 1); 1039 if (ret) 1040 return ret; 1041 1042 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, 1043 &stm32_sai_pcm_config, 0); 1044 if (ret) { 1045 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1046 return ret; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static struct platform_driver stm32_sai_sub_driver = { 1053 .driver = { 1054 .name = "st,stm32-sai-sub", 1055 .of_match_table = stm32_sai_sub_ids, 1056 }, 1057 .probe = stm32_sai_sub_probe, 1058 }; 1059 1060 module_platform_driver(stm32_sai_sub_driver); 1061 1062 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1063 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1064 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1065 MODULE_LICENSE("GPL v2"); 1066