1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/regmap.h> 16 17 #include <sound/asoundef.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 22 #include "stm32_sai.h" 23 24 #define SAI_FREE_PROTOCOL 0x0 25 #define SAI_SPDIF_PROTOCOL 0x1 26 27 #define SAI_SLOT_SIZE_AUTO 0x0 28 #define SAI_SLOT_SIZE_16 0x1 29 #define SAI_SLOT_SIZE_32 0x2 30 31 #define SAI_DATASIZE_8 0x2 32 #define SAI_DATASIZE_10 0x3 33 #define SAI_DATASIZE_16 0x4 34 #define SAI_DATASIZE_20 0x5 35 #define SAI_DATASIZE_24 0x6 36 #define SAI_DATASIZE_32 0x7 37 38 #define STM_SAI_DAI_NAME_SIZE 15 39 40 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 41 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 42 43 #define STM_SAI_A_ID 0x0 44 #define STM_SAI_B_ID 0x1 45 46 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 47 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 48 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 49 50 #define SAI_SYNC_NONE 0x0 51 #define SAI_SYNC_INTERNAL 0x1 52 #define SAI_SYNC_EXTERNAL 0x2 53 54 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 55 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 56 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 57 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 58 59 #define SAI_IEC60958_BLOCK_FRAMES 192 60 #define SAI_IEC60958_STATUS_BYTES 24 61 62 #define SAI_MCLK_NAME_LEN 32 63 #define SAI_RATE_11K 11025 64 65 /** 66 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 67 * @pdev: device data pointer 68 * @regmap: SAI register map pointer 69 * @regmap_config: SAI sub block register map configuration pointer 70 * @dma_params: dma configuration data for rx or tx channel 71 * @cpu_dai_drv: DAI driver data pointer 72 * @cpu_dai: DAI runtime data pointer 73 * @substream: PCM substream data pointer 74 * @pdata: SAI block parent data pointer 75 * @np_sync_provider: synchronization provider node 76 * @sai_ck: kernel clock feeding the SAI clock generator 77 * @sai_mclk: master clock from SAI mclk provider 78 * @phys_addr: SAI registers physical base address 79 * @mclk_rate: SAI block master clock frequency (Hz). set at init 80 * @id: SAI sub block id corresponding to sub-block A or B 81 * @dir: SAI block direction (playback or capture). set at init 82 * @master: SAI block mode flag. (true=master, false=slave) set at init 83 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 84 * @fmt: SAI block format. relevant only for custom protocols. set at init 85 * @sync: SAI block synchronization mode. (none, internal or external) 86 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 87 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 88 * @fs_length: frame synchronization length. depends on protocol settings 89 * @slots: rx or tx slot number 90 * @slot_width: rx or tx slot width in bits 91 * @slot_mask: rx or tx active slots mask. set at init or at runtime 92 * @data_size: PCM data width. corresponds to PCM substream width. 93 * @spdif_frm_cnt: S/PDIF playback frame counter 94 * @iec958: iec958 data 95 * @ctrl_lock: control lock 96 * @irq_lock: prevent race condition with IRQ 97 */ 98 struct stm32_sai_sub_data { 99 struct platform_device *pdev; 100 struct regmap *regmap; 101 const struct regmap_config *regmap_config; 102 struct snd_dmaengine_dai_dma_data dma_params; 103 struct snd_soc_dai_driver cpu_dai_drv; 104 struct snd_soc_dai *cpu_dai; 105 struct snd_pcm_substream *substream; 106 struct stm32_sai_data *pdata; 107 struct device_node *np_sync_provider; 108 struct clk *sai_ck; 109 struct clk *sai_mclk; 110 dma_addr_t phys_addr; 111 unsigned int mclk_rate; 112 unsigned int id; 113 int dir; 114 bool master; 115 bool spdif; 116 int fmt; 117 int sync; 118 int synco; 119 int synci; 120 int fs_length; 121 int slots; 122 int slot_width; 123 int slot_mask; 124 int data_size; 125 unsigned int spdif_frm_cnt; 126 struct snd_aes_iec958 iec958; 127 struct mutex ctrl_lock; /* protect resources accessed by controls */ 128 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 129 }; 130 131 enum stm32_sai_fifo_th { 132 STM_SAI_FIFO_TH_EMPTY, 133 STM_SAI_FIFO_TH_QUARTER, 134 STM_SAI_FIFO_TH_HALF, 135 STM_SAI_FIFO_TH_3_QUARTER, 136 STM_SAI_FIFO_TH_FULL, 137 }; 138 139 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 140 { 141 switch (reg) { 142 case STM_SAI_CR1_REGX: 143 case STM_SAI_CR2_REGX: 144 case STM_SAI_FRCR_REGX: 145 case STM_SAI_SLOTR_REGX: 146 case STM_SAI_IMR_REGX: 147 case STM_SAI_SR_REGX: 148 case STM_SAI_CLRFR_REGX: 149 case STM_SAI_DR_REGX: 150 case STM_SAI_PDMCR_REGX: 151 case STM_SAI_PDMLY_REGX: 152 return true; 153 default: 154 return false; 155 } 156 } 157 158 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 159 { 160 switch (reg) { 161 case STM_SAI_DR_REGX: 162 case STM_SAI_SR_REGX: 163 return true; 164 default: 165 return false; 166 } 167 } 168 169 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 170 { 171 switch (reg) { 172 case STM_SAI_CR1_REGX: 173 case STM_SAI_CR2_REGX: 174 case STM_SAI_FRCR_REGX: 175 case STM_SAI_SLOTR_REGX: 176 case STM_SAI_IMR_REGX: 177 case STM_SAI_CLRFR_REGX: 178 case STM_SAI_DR_REGX: 179 case STM_SAI_PDMCR_REGX: 180 case STM_SAI_PDMLY_REGX: 181 return true; 182 default: 183 return false; 184 } 185 } 186 187 static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, 188 unsigned int reg, unsigned int mask, 189 unsigned int val) 190 { 191 int ret; 192 193 ret = clk_enable(sai->pdata->pclk); 194 if (ret < 0) 195 return ret; 196 197 ret = regmap_update_bits(sai->regmap, reg, mask, val); 198 199 clk_disable(sai->pdata->pclk); 200 201 return ret; 202 } 203 204 static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, 205 unsigned int reg, unsigned int mask, 206 unsigned int val) 207 { 208 int ret; 209 210 ret = clk_enable(sai->pdata->pclk); 211 if (ret < 0) 212 return ret; 213 214 ret = regmap_write_bits(sai->regmap, reg, mask, val); 215 216 clk_disable(sai->pdata->pclk); 217 218 return ret; 219 } 220 221 static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, 222 unsigned int reg, unsigned int *val) 223 { 224 int ret; 225 226 ret = clk_enable(sai->pdata->pclk); 227 if (ret < 0) 228 return ret; 229 230 ret = regmap_read(sai->regmap, reg, val); 231 232 clk_disable(sai->pdata->pclk); 233 234 return ret; 235 } 236 237 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 238 .reg_bits = 32, 239 .reg_stride = 4, 240 .val_bits = 32, 241 .max_register = STM_SAI_DR_REGX, 242 .readable_reg = stm32_sai_sub_readable_reg, 243 .volatile_reg = stm32_sai_sub_volatile_reg, 244 .writeable_reg = stm32_sai_sub_writeable_reg, 245 .fast_io = true, 246 .cache_type = REGCACHE_FLAT, 247 }; 248 249 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 250 .reg_bits = 32, 251 .reg_stride = 4, 252 .val_bits = 32, 253 .max_register = STM_SAI_PDMLY_REGX, 254 .readable_reg = stm32_sai_sub_readable_reg, 255 .volatile_reg = stm32_sai_sub_volatile_reg, 256 .writeable_reg = stm32_sai_sub_writeable_reg, 257 .fast_io = true, 258 .cache_type = REGCACHE_FLAT, 259 }; 260 261 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 262 struct snd_ctl_elem_info *uinfo) 263 { 264 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 265 uinfo->count = 1; 266 267 return 0; 268 } 269 270 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 271 struct snd_ctl_elem_value *uctl) 272 { 273 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 274 275 mutex_lock(&sai->ctrl_lock); 276 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 277 mutex_unlock(&sai->ctrl_lock); 278 279 return 0; 280 } 281 282 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *uctl) 284 { 285 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 286 287 mutex_lock(&sai->ctrl_lock); 288 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 289 mutex_unlock(&sai->ctrl_lock); 290 291 return 0; 292 } 293 294 static const struct snd_kcontrol_new iec958_ctls = { 295 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 296 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 297 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 298 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 299 .info = snd_pcm_iec958_info, 300 .get = snd_pcm_iec958_get, 301 .put = snd_pcm_iec958_put, 302 }; 303 304 struct stm32_sai_mclk_data { 305 struct clk_hw hw; 306 unsigned long freq; 307 struct stm32_sai_sub_data *sai_data; 308 }; 309 310 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 311 #define STM32_SAI_MAX_CLKS 1 312 313 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 314 unsigned long input_rate, 315 unsigned long output_rate) 316 { 317 int version = sai->pdata->conf.version; 318 int div; 319 320 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 321 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 322 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 323 return -EINVAL; 324 } 325 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 326 327 if (input_rate % div) 328 dev_dbg(&sai->pdev->dev, 329 "Rate not accurate. requested (%ld), actual (%ld)\n", 330 output_rate, input_rate / div); 331 332 return div; 333 } 334 335 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 336 unsigned int div) 337 { 338 int version = sai->pdata->conf.version; 339 int ret, cr1, mask; 340 341 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 342 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 343 return -EINVAL; 344 } 345 346 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 347 cr1 = SAI_XCR1_MCKDIV_SET(div); 348 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); 349 if (ret < 0) 350 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 351 352 return ret; 353 } 354 355 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, 356 unsigned int rate) 357 { 358 struct platform_device *pdev = sai->pdev; 359 struct clk *parent_clk = sai->pdata->clk_x8k; 360 int ret; 361 362 if (!(rate % SAI_RATE_11K)) 363 parent_clk = sai->pdata->clk_x11k; 364 365 ret = clk_set_parent(sai->sai_ck, parent_clk); 366 if (ret) 367 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 368 ret, ret == -EBUSY ? 369 "Active stream rates conflict\n" : "\n"); 370 371 return ret; 372 } 373 374 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 375 unsigned long *prate) 376 { 377 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 378 struct stm32_sai_sub_data *sai = mclk->sai_data; 379 int div; 380 381 div = stm32_sai_get_clk_div(sai, *prate, rate); 382 if (div < 0) 383 return div; 384 385 mclk->freq = *prate / div; 386 387 return mclk->freq; 388 } 389 390 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 391 unsigned long parent_rate) 392 { 393 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 394 395 return mclk->freq; 396 } 397 398 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 399 unsigned long parent_rate) 400 { 401 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 402 struct stm32_sai_sub_data *sai = mclk->sai_data; 403 int div, ret; 404 405 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 406 if (div < 0) 407 return div; 408 409 ret = stm32_sai_set_clk_div(sai, div); 410 if (ret) 411 return ret; 412 413 mclk->freq = rate; 414 415 return 0; 416 } 417 418 static int stm32_sai_mclk_enable(struct clk_hw *hw) 419 { 420 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 421 struct stm32_sai_sub_data *sai = mclk->sai_data; 422 423 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 424 425 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 426 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 427 } 428 429 static void stm32_sai_mclk_disable(struct clk_hw *hw) 430 { 431 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 432 struct stm32_sai_sub_data *sai = mclk->sai_data; 433 434 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 435 436 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 437 } 438 439 static const struct clk_ops mclk_ops = { 440 .enable = stm32_sai_mclk_enable, 441 .disable = stm32_sai_mclk_disable, 442 .recalc_rate = stm32_sai_mclk_recalc_rate, 443 .round_rate = stm32_sai_mclk_round_rate, 444 .set_rate = stm32_sai_mclk_set_rate, 445 }; 446 447 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 448 { 449 struct clk_hw *hw; 450 struct stm32_sai_mclk_data *mclk; 451 struct device *dev = &sai->pdev->dev; 452 const char *pname = __clk_get_name(sai->sai_ck); 453 char *mclk_name, *p, *s = (char *)pname; 454 int ret, i = 0; 455 456 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 457 if (!mclk) 458 return -ENOMEM; 459 460 mclk_name = devm_kcalloc(dev, sizeof(char), 461 SAI_MCLK_NAME_LEN, GFP_KERNEL); 462 if (!mclk_name) 463 return -ENOMEM; 464 465 /* 466 * Forge mclk clock name from parent clock name and suffix. 467 * String after "_" char is stripped in parent name. 468 */ 469 p = mclk_name; 470 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 471 *p++ = *s++; 472 i++; 473 } 474 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 475 476 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 477 mclk->sai_data = sai; 478 hw = &mclk->hw; 479 480 dev_dbg(dev, "Register master clock %s\n", mclk_name); 481 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 482 if (ret) { 483 dev_err(dev, "mclk register returned %d\n", ret); 484 return ret; 485 } 486 sai->sai_mclk = hw->clk; 487 488 /* register mclk provider */ 489 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 490 } 491 492 static irqreturn_t stm32_sai_isr(int irq, void *devid) 493 { 494 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 495 struct platform_device *pdev = sai->pdev; 496 unsigned int sr, imr, flags; 497 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 498 499 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr); 500 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr); 501 502 flags = sr & imr; 503 if (!flags) 504 return IRQ_NONE; 505 506 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 507 SAI_XCLRFR_MASK); 508 509 if (!sai->substream) { 510 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 511 return IRQ_NONE; 512 } 513 514 if (flags & SAI_XIMR_OVRUDRIE) { 515 dev_err(&pdev->dev, "IRQ %s\n", 516 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 517 status = SNDRV_PCM_STATE_XRUN; 518 } 519 520 if (flags & SAI_XIMR_MUTEDETIE) 521 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 522 523 if (flags & SAI_XIMR_WCKCFGIE) { 524 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 525 status = SNDRV_PCM_STATE_DISCONNECTED; 526 } 527 528 if (flags & SAI_XIMR_CNRDYIE) 529 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 530 531 if (flags & SAI_XIMR_AFSDETIE) { 532 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 533 status = SNDRV_PCM_STATE_XRUN; 534 } 535 536 if (flags & SAI_XIMR_LFSDETIE) { 537 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 538 status = SNDRV_PCM_STATE_XRUN; 539 } 540 541 spin_lock(&sai->irq_lock); 542 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 543 snd_pcm_stop_xrun(sai->substream); 544 spin_unlock(&sai->irq_lock); 545 546 return IRQ_HANDLED; 547 } 548 549 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 550 int clk_id, unsigned int freq, int dir) 551 { 552 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 553 int ret; 554 555 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 556 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 557 SAI_XCR1_NODIV, 558 freq ? 0 : SAI_XCR1_NODIV); 559 if (ret < 0) 560 return ret; 561 562 /* Assume shutdown if requested frequency is 0Hz */ 563 if (!freq) { 564 /* Release mclk rate only if rate was actually set */ 565 if (sai->mclk_rate) { 566 clk_rate_exclusive_put(sai->sai_mclk); 567 sai->mclk_rate = 0; 568 } 569 return 0; 570 } 571 572 /* If master clock is used, set parent clock now */ 573 ret = stm32_sai_set_parent_clock(sai, freq); 574 if (ret) 575 return ret; 576 577 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 578 if (ret) { 579 dev_err(cpu_dai->dev, 580 ret == -EBUSY ? 581 "Active streams have incompatible rates" : 582 "Could not set mclk rate\n"); 583 return ret; 584 } 585 586 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 587 sai->mclk_rate = freq; 588 } 589 590 return 0; 591 } 592 593 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 594 u32 rx_mask, int slots, int slot_width) 595 { 596 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 597 int slotr, slotr_mask, slot_size; 598 599 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 600 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 601 return 0; 602 } 603 604 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 605 tx_mask, rx_mask, slots, slot_width); 606 607 switch (slot_width) { 608 case 16: 609 slot_size = SAI_SLOT_SIZE_16; 610 break; 611 case 32: 612 slot_size = SAI_SLOT_SIZE_32; 613 break; 614 default: 615 slot_size = SAI_SLOT_SIZE_AUTO; 616 break; 617 } 618 619 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 620 SAI_XSLOTR_NBSLOT_SET(slots - 1); 621 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 622 623 /* tx/rx mask set in machine init, if slot number defined in DT */ 624 if (STM_SAI_IS_PLAYBACK(sai)) { 625 sai->slot_mask = tx_mask; 626 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 627 } 628 629 if (STM_SAI_IS_CAPTURE(sai)) { 630 sai->slot_mask = rx_mask; 631 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 632 } 633 634 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 635 636 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 637 638 sai->slot_width = slot_width; 639 sai->slots = slots; 640 641 return 0; 642 } 643 644 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 645 { 646 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 647 int cr1, frcr = 0; 648 int cr1_mask, frcr_mask = 0; 649 int ret; 650 651 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 652 653 /* Do not generate master by default */ 654 cr1 = SAI_XCR1_NODIV; 655 cr1_mask = SAI_XCR1_NODIV; 656 657 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 658 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 659 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 660 goto conf_update; 661 } 662 663 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 664 665 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 666 /* SCK active high for all protocols */ 667 case SND_SOC_DAIFMT_I2S: 668 cr1 |= SAI_XCR1_CKSTR; 669 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 670 break; 671 /* Left justified */ 672 case SND_SOC_DAIFMT_MSB: 673 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 674 break; 675 /* Right justified */ 676 case SND_SOC_DAIFMT_LSB: 677 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 678 break; 679 case SND_SOC_DAIFMT_DSP_A: 680 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 681 break; 682 case SND_SOC_DAIFMT_DSP_B: 683 frcr |= SAI_XFRCR_FSPOL; 684 break; 685 default: 686 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 687 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 688 return -EINVAL; 689 } 690 691 cr1_mask |= SAI_XCR1_CKSTR; 692 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 693 SAI_XFRCR_FSDEF; 694 695 /* DAI clock strobing. Invert setting previously set */ 696 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 697 case SND_SOC_DAIFMT_NB_NF: 698 break; 699 case SND_SOC_DAIFMT_IB_NF: 700 cr1 ^= SAI_XCR1_CKSTR; 701 break; 702 case SND_SOC_DAIFMT_NB_IF: 703 frcr ^= SAI_XFRCR_FSPOL; 704 break; 705 case SND_SOC_DAIFMT_IB_IF: 706 /* Invert fs & sck */ 707 cr1 ^= SAI_XCR1_CKSTR; 708 frcr ^= SAI_XFRCR_FSPOL; 709 break; 710 default: 711 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 712 fmt & SND_SOC_DAIFMT_INV_MASK); 713 return -EINVAL; 714 } 715 cr1_mask |= SAI_XCR1_CKSTR; 716 frcr_mask |= SAI_XFRCR_FSPOL; 717 718 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 719 720 /* DAI clock master masks */ 721 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 722 case SND_SOC_DAIFMT_CBM_CFM: 723 /* codec is master */ 724 cr1 |= SAI_XCR1_SLAVE; 725 sai->master = false; 726 break; 727 case SND_SOC_DAIFMT_CBS_CFS: 728 sai->master = true; 729 break; 730 default: 731 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 732 fmt & SND_SOC_DAIFMT_MASTER_MASK); 733 return -EINVAL; 734 } 735 736 /* Set slave mode if sub-block is synchronized with another SAI */ 737 if (sai->sync) { 738 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 739 cr1 |= SAI_XCR1_SLAVE; 740 sai->master = false; 741 } 742 743 cr1_mask |= SAI_XCR1_SLAVE; 744 745 conf_update: 746 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 747 if (ret < 0) { 748 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 749 return ret; 750 } 751 752 sai->fmt = fmt; 753 754 return 0; 755 } 756 757 static int stm32_sai_startup(struct snd_pcm_substream *substream, 758 struct snd_soc_dai *cpu_dai) 759 { 760 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 761 int imr, cr2, ret; 762 unsigned long flags; 763 764 spin_lock_irqsave(&sai->irq_lock, flags); 765 sai->substream = substream; 766 spin_unlock_irqrestore(&sai->irq_lock, flags); 767 768 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 769 snd_pcm_hw_constraint_mask64(substream->runtime, 770 SNDRV_PCM_HW_PARAM_FORMAT, 771 SNDRV_PCM_FMTBIT_S32_LE); 772 snd_pcm_hw_constraint_single(substream->runtime, 773 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 774 } 775 776 ret = clk_prepare_enable(sai->sai_ck); 777 if (ret < 0) { 778 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 779 return ret; 780 } 781 782 /* Enable ITs */ 783 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, 784 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 785 786 imr = SAI_XIMR_OVRUDRIE; 787 if (STM_SAI_IS_CAPTURE(sai)) { 788 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2); 789 if (cr2 & SAI_XCR2_MUTECNT_MASK) 790 imr |= SAI_XIMR_MUTEDETIE; 791 } 792 793 if (sai->master) 794 imr |= SAI_XIMR_WCKCFGIE; 795 else 796 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 797 798 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 799 SAI_XIMR_MASK, imr); 800 801 return 0; 802 } 803 804 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 805 struct snd_pcm_substream *substream, 806 struct snd_pcm_hw_params *params) 807 { 808 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 809 int cr1, cr1_mask, ret; 810 811 /* 812 * DMA bursts increment is set to 4 words. 813 * SAI fifo threshold is set to half fifo, to keep enough space 814 * for DMA incoming bursts. 815 */ 816 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, 817 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 818 SAI_XCR2_FFLUSH | 819 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 820 821 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 822 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 823 sai->spdif_frm_cnt = 0; 824 return 0; 825 } 826 827 /* Mode, data format and channel config */ 828 cr1_mask = SAI_XCR1_DS_MASK; 829 switch (params_format(params)) { 830 case SNDRV_PCM_FORMAT_S8: 831 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 832 break; 833 case SNDRV_PCM_FORMAT_S16_LE: 834 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 835 break; 836 case SNDRV_PCM_FORMAT_S32_LE: 837 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 838 break; 839 default: 840 dev_err(cpu_dai->dev, "Data format not supported"); 841 return -EINVAL; 842 } 843 844 cr1_mask |= SAI_XCR1_MONO; 845 if ((sai->slots == 2) && (params_channels(params) == 1)) 846 cr1 |= SAI_XCR1_MONO; 847 848 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 849 if (ret < 0) { 850 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 851 return ret; 852 } 853 854 return 0; 855 } 856 857 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 858 { 859 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 860 int slotr, slot_sz; 861 862 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr); 863 864 /* 865 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 866 * By default slot width = data size, if not forced from DT 867 */ 868 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 869 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 870 sai->slot_width = sai->data_size; 871 872 if (sai->slot_width < sai->data_size) { 873 dev_err(cpu_dai->dev, 874 "Data size %d larger than slot width\n", 875 sai->data_size); 876 return -EINVAL; 877 } 878 879 /* Slot number is set to 2, if not specified in DT */ 880 if (!sai->slots) 881 sai->slots = 2; 882 883 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 884 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 885 SAI_XSLOTR_NBSLOT_MASK, 886 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 887 888 /* Set default slots mask if not already set from DT */ 889 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 890 sai->slot_mask = (1 << sai->slots) - 1; 891 stm32_sai_sub_reg_up(sai, 892 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 893 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 894 } 895 896 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 897 sai->slots, sai->slot_width); 898 899 return 0; 900 } 901 902 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 903 { 904 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 905 int fs_active, offset, format; 906 int frcr, frcr_mask; 907 908 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 909 sai->fs_length = sai->slot_width * sai->slots; 910 911 fs_active = sai->fs_length / 2; 912 if ((format == SND_SOC_DAIFMT_DSP_A) || 913 (format == SND_SOC_DAIFMT_DSP_B)) 914 fs_active = 1; 915 916 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 917 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 918 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 919 920 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 921 sai->fs_length, fs_active); 922 923 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 924 925 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 926 offset = sai->slot_width - sai->data_size; 927 928 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 929 SAI_XSLOTR_FBOFF_MASK, 930 SAI_XSLOTR_FBOFF_SET(offset)); 931 } 932 } 933 934 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 935 { 936 unsigned char *cs = sai->iec958.status; 937 938 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 939 cs[1] = IEC958_AES1_CON_GENERAL; 940 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 941 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 942 } 943 944 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 945 struct snd_pcm_runtime *runtime) 946 { 947 if (!runtime) 948 return; 949 950 /* Force the sample rate according to runtime rate */ 951 mutex_lock(&sai->ctrl_lock); 952 switch (runtime->rate) { 953 case 22050: 954 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 955 break; 956 case 44100: 957 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 958 break; 959 case 88200: 960 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 961 break; 962 case 176400: 963 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 964 break; 965 case 24000: 966 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 967 break; 968 case 48000: 969 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 970 break; 971 case 96000: 972 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 973 break; 974 case 192000: 975 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 976 break; 977 case 32000: 978 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 979 break; 980 default: 981 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 982 break; 983 } 984 mutex_unlock(&sai->ctrl_lock); 985 } 986 987 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 988 struct snd_pcm_hw_params *params) 989 { 990 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 991 int div = 0, cr1 = 0; 992 int sai_clk_rate, mclk_ratio, den; 993 unsigned int rate = params_rate(params); 994 int ret; 995 996 if (!sai->sai_mclk) { 997 ret = stm32_sai_set_parent_clock(sai, rate); 998 if (ret) 999 return ret; 1000 } 1001 sai_clk_rate = clk_get_rate(sai->sai_ck); 1002 1003 if (STM_SAI_IS_F4(sai->pdata)) { 1004 /* mclk on (NODIV=0) 1005 * mclk_rate = 256 * fs 1006 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 1007 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 1008 * mclk off (NODIV=1) 1009 * MCKDIV ignored. sck = sai_ck 1010 */ 1011 if (!sai->mclk_rate) 1012 return 0; 1013 1014 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 1015 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1016 2 * sai->mclk_rate); 1017 if (div < 0) 1018 return div; 1019 } 1020 } else { 1021 /* 1022 * TDM mode : 1023 * mclk on 1024 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 1025 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 1026 * mclk off 1027 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 1028 * Note: NOMCK/NODIV correspond to same bit. 1029 */ 1030 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1031 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1032 rate * 128); 1033 if (div < 0) 1034 return div; 1035 } else { 1036 if (sai->mclk_rate) { 1037 mclk_ratio = sai->mclk_rate / rate; 1038 if (mclk_ratio == 512) { 1039 cr1 = SAI_XCR1_OSR; 1040 } else if (mclk_ratio != 256) { 1041 dev_err(cpu_dai->dev, 1042 "Wrong mclk ratio %d\n", 1043 mclk_ratio); 1044 return -EINVAL; 1045 } 1046 1047 stm32_sai_sub_reg_up(sai, 1048 STM_SAI_CR1_REGX, 1049 SAI_XCR1_OSR, cr1); 1050 1051 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1052 sai->mclk_rate); 1053 if (div < 0) 1054 return div; 1055 } else { 1056 /* mclk-fs not set, master clock not active */ 1057 den = sai->fs_length * params_rate(params); 1058 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1059 den); 1060 if (div < 0) 1061 return div; 1062 } 1063 } 1064 } 1065 1066 return stm32_sai_set_clk_div(sai, div); 1067 } 1068 1069 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1070 struct snd_pcm_hw_params *params, 1071 struct snd_soc_dai *cpu_dai) 1072 { 1073 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1074 int ret; 1075 1076 sai->data_size = params_width(params); 1077 1078 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1079 /* Rate not already set in runtime structure */ 1080 substream->runtime->rate = params_rate(params); 1081 stm32_sai_set_iec958_status(sai, substream->runtime); 1082 } else { 1083 ret = stm32_sai_set_slots(cpu_dai); 1084 if (ret < 0) 1085 return ret; 1086 stm32_sai_set_frame(cpu_dai); 1087 } 1088 1089 ret = stm32_sai_set_config(cpu_dai, substream, params); 1090 if (ret) 1091 return ret; 1092 1093 if (sai->master) 1094 ret = stm32_sai_configure_clock(cpu_dai, params); 1095 1096 return ret; 1097 } 1098 1099 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1100 struct snd_soc_dai *cpu_dai) 1101 { 1102 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1103 int ret; 1104 1105 switch (cmd) { 1106 case SNDRV_PCM_TRIGGER_START: 1107 case SNDRV_PCM_TRIGGER_RESUME: 1108 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1109 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1110 1111 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1112 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1113 1114 /* Enable SAI */ 1115 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1116 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1117 if (ret < 0) 1118 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1119 break; 1120 case SNDRV_PCM_TRIGGER_SUSPEND: 1121 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1122 case SNDRV_PCM_TRIGGER_STOP: 1123 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1124 1125 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 1126 SAI_XIMR_MASK, 0); 1127 1128 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1129 SAI_XCR1_SAIEN, 1130 (unsigned int)~SAI_XCR1_SAIEN); 1131 1132 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1133 SAI_XCR1_DMAEN, 1134 (unsigned int)~SAI_XCR1_DMAEN); 1135 if (ret < 0) 1136 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1137 1138 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1139 sai->spdif_frm_cnt = 0; 1140 break; 1141 default: 1142 return -EINVAL; 1143 } 1144 1145 return ret; 1146 } 1147 1148 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1149 struct snd_soc_dai *cpu_dai) 1150 { 1151 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1152 unsigned long flags; 1153 1154 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1155 1156 clk_disable_unprepare(sai->sai_ck); 1157 1158 spin_lock_irqsave(&sai->irq_lock, flags); 1159 sai->substream = NULL; 1160 spin_unlock_irqrestore(&sai->irq_lock, flags); 1161 } 1162 1163 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1164 struct snd_soc_dai *cpu_dai) 1165 { 1166 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1167 struct snd_kcontrol_new knew = iec958_ctls; 1168 1169 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1170 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1171 knew.device = rtd->pcm->device; 1172 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1173 } 1174 1175 return 0; 1176 } 1177 1178 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1179 { 1180 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1181 int cr1 = 0, cr1_mask, ret; 1182 1183 sai->cpu_dai = cpu_dai; 1184 1185 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1186 /* 1187 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1188 * as it allows bytes, half-word and words transfers. (See DMA fifos 1189 * constraints). 1190 */ 1191 sai->dma_params.maxburst = 4; 1192 if (sai->pdata->conf.fifo_size < 8) 1193 sai->dma_params.maxburst = 1; 1194 /* Buswidth will be set by framework at runtime */ 1195 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1196 1197 if (STM_SAI_IS_PLAYBACK(sai)) 1198 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1199 else 1200 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1201 1202 /* Next settings are not relevant for spdif mode */ 1203 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1204 return 0; 1205 1206 cr1_mask = SAI_XCR1_RX_TX; 1207 if (STM_SAI_IS_CAPTURE(sai)) 1208 cr1 |= SAI_XCR1_RX_TX; 1209 1210 /* Configure synchronization */ 1211 if (sai->sync == SAI_SYNC_EXTERNAL) { 1212 /* Configure synchro client and provider */ 1213 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1214 sai->synco, sai->synci); 1215 if (ret) 1216 return ret; 1217 } 1218 1219 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1220 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1221 1222 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 1223 } 1224 1225 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1226 .set_sysclk = stm32_sai_set_sysclk, 1227 .set_fmt = stm32_sai_set_dai_fmt, 1228 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1229 .startup = stm32_sai_startup, 1230 .hw_params = stm32_sai_hw_params, 1231 .trigger = stm32_sai_trigger, 1232 .shutdown = stm32_sai_shutdown, 1233 }; 1234 1235 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1236 int channel, unsigned long hwoff, 1237 void *buf, unsigned long bytes) 1238 { 1239 struct snd_pcm_runtime *runtime = substream->runtime; 1240 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1241 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 1242 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1243 int *ptr = (int *)(runtime->dma_area + hwoff + 1244 channel * (runtime->dma_bytes / runtime->channels)); 1245 ssize_t cnt = bytes_to_samples(runtime, bytes); 1246 unsigned int frm_cnt = sai->spdif_frm_cnt; 1247 unsigned int byte; 1248 unsigned int mask; 1249 1250 do { 1251 *ptr = ((*ptr >> 8) & 0x00ffffff); 1252 1253 /* Set channel status bit */ 1254 byte = frm_cnt >> 3; 1255 mask = 1 << (frm_cnt - (byte << 3)); 1256 if (sai->iec958.status[byte] & mask) 1257 *ptr |= 0x04000000; 1258 ptr++; 1259 1260 if (!(cnt % 2)) 1261 frm_cnt++; 1262 1263 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1264 frm_cnt = 0; 1265 } while (--cnt); 1266 sai->spdif_frm_cnt = frm_cnt; 1267 1268 return 0; 1269 } 1270 1271 /* No support of mmap in S/PDIF mode */ 1272 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = { 1273 .info = SNDRV_PCM_INFO_INTERLEAVED, 1274 .buffer_bytes_max = 8 * PAGE_SIZE, 1275 .period_bytes_min = 1024, 1276 .period_bytes_max = PAGE_SIZE, 1277 .periods_min = 2, 1278 .periods_max = 8, 1279 }; 1280 1281 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1282 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1283 .buffer_bytes_max = 8 * PAGE_SIZE, 1284 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1285 .period_bytes_max = PAGE_SIZE, 1286 .periods_min = 2, 1287 .periods_max = 8, 1288 }; 1289 1290 static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1291 .probe = stm32_sai_dai_probe, 1292 .pcm_new = stm32_sai_pcm_new, 1293 .id = 1, /* avoid call to fmt_single_name() */ 1294 .playback = { 1295 .channels_min = 1, 1296 .channels_max = 2, 1297 .rate_min = 8000, 1298 .rate_max = 192000, 1299 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1300 /* DMA does not support 24 bits transfers */ 1301 .formats = 1302 SNDRV_PCM_FMTBIT_S8 | 1303 SNDRV_PCM_FMTBIT_S16_LE | 1304 SNDRV_PCM_FMTBIT_S32_LE, 1305 }, 1306 .ops = &stm32_sai_pcm_dai_ops, 1307 }; 1308 1309 static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1310 .probe = stm32_sai_dai_probe, 1311 .id = 1, /* avoid call to fmt_single_name() */ 1312 .capture = { 1313 .channels_min = 1, 1314 .channels_max = 2, 1315 .rate_min = 8000, 1316 .rate_max = 192000, 1317 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1318 /* DMA does not support 24 bits transfers */ 1319 .formats = 1320 SNDRV_PCM_FMTBIT_S8 | 1321 SNDRV_PCM_FMTBIT_S16_LE | 1322 SNDRV_PCM_FMTBIT_S32_LE, 1323 }, 1324 .ops = &stm32_sai_pcm_dai_ops, 1325 }; 1326 1327 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1328 .pcm_hardware = &stm32_sai_pcm_hw, 1329 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1330 }; 1331 1332 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1333 .pcm_hardware = &stm32_sai_pcm_hw_spdif, 1334 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1335 .process = stm32_sai_pcm_process_spdif, 1336 }; 1337 1338 static const struct snd_soc_component_driver stm32_component = { 1339 .name = "stm32-sai", 1340 }; 1341 1342 static const struct of_device_id stm32_sai_sub_ids[] = { 1343 { .compatible = "st,stm32-sai-sub-a", 1344 .data = (void *)STM_SAI_A_ID}, 1345 { .compatible = "st,stm32-sai-sub-b", 1346 .data = (void *)STM_SAI_B_ID}, 1347 {} 1348 }; 1349 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1350 1351 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1352 struct stm32_sai_sub_data *sai) 1353 { 1354 struct device_node *np = pdev->dev.of_node; 1355 struct resource *res; 1356 void __iomem *base; 1357 struct of_phandle_args args; 1358 int ret; 1359 1360 if (!np) 1361 return -ENODEV; 1362 1363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1364 base = devm_ioremap_resource(&pdev->dev, res); 1365 if (IS_ERR(base)) 1366 return PTR_ERR(base); 1367 1368 sai->phys_addr = res->start; 1369 1370 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1371 /* Note: PDM registers not available for sub-block B */ 1372 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 1373 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1374 1375 /* 1376 * Do not manage peripheral clock through regmap framework as this 1377 * can lead to circular locking issue with sai master clock provider. 1378 * Manage peripheral clock directly in driver instead. 1379 */ 1380 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1381 sai->regmap_config); 1382 if (IS_ERR(sai->regmap)) { 1383 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 1384 return PTR_ERR(sai->regmap); 1385 } 1386 1387 /* Get direction property */ 1388 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1389 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1390 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1391 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1392 } else { 1393 dev_err(&pdev->dev, "Unsupported direction\n"); 1394 return -EINVAL; 1395 } 1396 1397 /* Get spdif iec60958 property */ 1398 sai->spdif = false; 1399 if (of_get_property(np, "st,iec60958", NULL)) { 1400 if (!STM_SAI_HAS_SPDIF(sai) || 1401 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1402 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1403 return -EINVAL; 1404 } 1405 stm32_sai_init_iec958_status(sai); 1406 sai->spdif = true; 1407 sai->master = true; 1408 } 1409 1410 /* Get synchronization property */ 1411 args.np = NULL; 1412 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1413 if (ret < 0 && ret != -ENOENT) { 1414 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1415 return ret; 1416 } 1417 1418 sai->sync = SAI_SYNC_NONE; 1419 if (args.np) { 1420 if (args.np == np) { 1421 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1422 of_node_put(args.np); 1423 return -EINVAL; 1424 } 1425 1426 sai->np_sync_provider = of_get_parent(args.np); 1427 if (!sai->np_sync_provider) { 1428 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1429 np); 1430 of_node_put(args.np); 1431 return -ENODEV; 1432 } 1433 1434 sai->sync = SAI_SYNC_INTERNAL; 1435 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1436 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1437 dev_err(&pdev->dev, 1438 "External synchro not supported\n"); 1439 of_node_put(args.np); 1440 return -EINVAL; 1441 } 1442 sai->sync = SAI_SYNC_EXTERNAL; 1443 1444 sai->synci = args.args[0]; 1445 if (sai->synci < 1 || 1446 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1447 dev_err(&pdev->dev, "Wrong SAI index\n"); 1448 of_node_put(args.np); 1449 return -EINVAL; 1450 } 1451 1452 if (of_property_match_string(args.np, "compatible", 1453 "st,stm32-sai-sub-a") >= 0) 1454 sai->synco = STM_SAI_SYNC_OUT_A; 1455 1456 if (of_property_match_string(args.np, "compatible", 1457 "st,stm32-sai-sub-b") >= 0) 1458 sai->synco = STM_SAI_SYNC_OUT_B; 1459 1460 if (!sai->synco) { 1461 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1462 of_node_put(args.np); 1463 return -EINVAL; 1464 } 1465 } 1466 1467 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1468 pdev->name, args.np->full_name); 1469 } 1470 1471 of_node_put(args.np); 1472 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1473 if (IS_ERR(sai->sai_ck)) { 1474 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 1475 return PTR_ERR(sai->sai_ck); 1476 } 1477 1478 ret = clk_prepare(sai->pdata->pclk); 1479 if (ret < 0) 1480 return ret; 1481 1482 if (STM_SAI_IS_F4(sai->pdata)) 1483 return 0; 1484 1485 /* Register mclk provider if requested */ 1486 if (of_find_property(np, "#clock-cells", NULL)) { 1487 ret = stm32_sai_add_mclk_provider(sai); 1488 if (ret < 0) 1489 return ret; 1490 } else { 1491 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 1492 if (IS_ERR(sai->sai_mclk)) { 1493 if (PTR_ERR(sai->sai_mclk) != -ENOENT) 1494 return PTR_ERR(sai->sai_mclk); 1495 sai->sai_mclk = NULL; 1496 } 1497 } 1498 1499 return 0; 1500 } 1501 1502 static int stm32_sai_sub_probe(struct platform_device *pdev) 1503 { 1504 struct stm32_sai_sub_data *sai; 1505 const struct of_device_id *of_id; 1506 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1507 int ret; 1508 1509 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1510 if (!sai) 1511 return -ENOMEM; 1512 1513 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1514 if (!of_id) 1515 return -EINVAL; 1516 sai->id = (uintptr_t)of_id->data; 1517 1518 sai->pdev = pdev; 1519 mutex_init(&sai->ctrl_lock); 1520 spin_lock_init(&sai->irq_lock); 1521 platform_set_drvdata(pdev, sai); 1522 1523 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1524 if (!sai->pdata) { 1525 dev_err(&pdev->dev, "Parent device data not available\n"); 1526 return -EINVAL; 1527 } 1528 1529 ret = stm32_sai_sub_parse_of(pdev, sai); 1530 if (ret) 1531 return ret; 1532 1533 if (STM_SAI_IS_PLAYBACK(sai)) 1534 sai->cpu_dai_drv = stm32_sai_playback_dai; 1535 else 1536 sai->cpu_dai_drv = stm32_sai_capture_dai; 1537 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1538 1539 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1540 IRQF_SHARED, dev_name(&pdev->dev), sai); 1541 if (ret) { 1542 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1543 return ret; 1544 } 1545 1546 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1547 &sai->cpu_dai_drv, 1); 1548 if (ret) 1549 return ret; 1550 1551 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1552 conf = &stm32_sai_pcm_config_spdif; 1553 1554 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1555 if (ret) { 1556 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1557 return ret; 1558 } 1559 1560 return 0; 1561 } 1562 1563 static int stm32_sai_sub_remove(struct platform_device *pdev) 1564 { 1565 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); 1566 1567 clk_unprepare(sai->pdata->pclk); 1568 1569 return 0; 1570 } 1571 1572 #ifdef CONFIG_PM_SLEEP 1573 static int stm32_sai_sub_suspend(struct device *dev) 1574 { 1575 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1576 int ret; 1577 1578 ret = clk_enable(sai->pdata->pclk); 1579 if (ret < 0) 1580 return ret; 1581 1582 regcache_cache_only(sai->regmap, true); 1583 regcache_mark_dirty(sai->regmap); 1584 1585 clk_disable(sai->pdata->pclk); 1586 1587 return 0; 1588 } 1589 1590 static int stm32_sai_sub_resume(struct device *dev) 1591 { 1592 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1593 int ret; 1594 1595 ret = clk_enable(sai->pdata->pclk); 1596 if (ret < 0) 1597 return ret; 1598 1599 regcache_cache_only(sai->regmap, false); 1600 ret = regcache_sync(sai->regmap); 1601 1602 clk_disable(sai->pdata->pclk); 1603 1604 return ret; 1605 } 1606 #endif /* CONFIG_PM_SLEEP */ 1607 1608 static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1609 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1610 }; 1611 1612 static struct platform_driver stm32_sai_sub_driver = { 1613 .driver = { 1614 .name = "st,stm32-sai-sub", 1615 .of_match_table = stm32_sai_sub_ids, 1616 .pm = &stm32_sai_sub_pm_ops, 1617 }, 1618 .probe = stm32_sai_sub_probe, 1619 .remove = stm32_sai_sub_remove, 1620 }; 1621 1622 module_platform_driver(stm32_sai_sub_driver); 1623 1624 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1625 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1626 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1627 MODULE_LICENSE("GPL v2"); 1628