1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clk-provider.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/regmap.h> 26 27 #include <sound/asoundef.h> 28 #include <sound/core.h> 29 #include <sound/dmaengine_pcm.h> 30 #include <sound/pcm_params.h> 31 32 #include "stm32_sai.h" 33 34 #define SAI_FREE_PROTOCOL 0x0 35 #define SAI_SPDIF_PROTOCOL 0x1 36 37 #define SAI_SLOT_SIZE_AUTO 0x0 38 #define SAI_SLOT_SIZE_16 0x1 39 #define SAI_SLOT_SIZE_32 0x2 40 41 #define SAI_DATASIZE_8 0x2 42 #define SAI_DATASIZE_10 0x3 43 #define SAI_DATASIZE_16 0x4 44 #define SAI_DATASIZE_20 0x5 45 #define SAI_DATASIZE_24 0x6 46 #define SAI_DATASIZE_32 0x7 47 48 #define STM_SAI_FIFO_SIZE 8 49 #define STM_SAI_DAI_NAME_SIZE 15 50 51 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 52 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 53 54 #define STM_SAI_A_ID 0x0 55 #define STM_SAI_B_ID 0x1 56 57 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 58 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 59 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 60 61 #define SAI_SYNC_NONE 0x0 62 #define SAI_SYNC_INTERNAL 0x1 63 #define SAI_SYNC_EXTERNAL 0x2 64 65 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 66 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif) 67 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 68 69 #define SAI_IEC60958_BLOCK_FRAMES 192 70 #define SAI_IEC60958_STATUS_BYTES 24 71 72 #define SAI_MCLK_NAME_LEN 32 73 74 /** 75 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 76 * @pdev: device data pointer 77 * @regmap: SAI register map pointer 78 * @regmap_config: SAI sub block register map configuration pointer 79 * @dma_params: dma configuration data for rx or tx channel 80 * @cpu_dai_drv: DAI driver data pointer 81 * @cpu_dai: DAI runtime data pointer 82 * @substream: PCM substream data pointer 83 * @pdata: SAI block parent data pointer 84 * @np_sync_provider: synchronization provider node 85 * @sai_ck: kernel clock feeding the SAI clock generator 86 * @sai_mclk: master clock from SAI mclk provider 87 * @phys_addr: SAI registers physical base address 88 * @mclk_rate: SAI block master clock frequency (Hz). set at init 89 * @id: SAI sub block id corresponding to sub-block A or B 90 * @dir: SAI block direction (playback or capture). set at init 91 * @master: SAI block mode flag. (true=master, false=slave) set at init 92 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 93 * @fmt: SAI block format. relevant only for custom protocols. set at init 94 * @sync: SAI block synchronization mode. (none, internal or external) 95 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 96 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 97 * @fs_length: frame synchronization length. depends on protocol settings 98 * @slots: rx or tx slot number 99 * @slot_width: rx or tx slot width in bits 100 * @slot_mask: rx or tx active slots mask. set at init or at runtime 101 * @data_size: PCM data width. corresponds to PCM substream width. 102 * @spdif_frm_cnt: S/PDIF playback frame counter 103 * @snd_aes_iec958: iec958 data 104 * @ctrl_lock: control lock 105 */ 106 struct stm32_sai_sub_data { 107 struct platform_device *pdev; 108 struct regmap *regmap; 109 const struct regmap_config *regmap_config; 110 struct snd_dmaengine_dai_dma_data dma_params; 111 struct snd_soc_dai_driver *cpu_dai_drv; 112 struct snd_soc_dai *cpu_dai; 113 struct snd_pcm_substream *substream; 114 struct stm32_sai_data *pdata; 115 struct device_node *np_sync_provider; 116 struct clk *sai_ck; 117 struct clk *sai_mclk; 118 dma_addr_t phys_addr; 119 unsigned int mclk_rate; 120 unsigned int id; 121 int dir; 122 bool master; 123 bool spdif; 124 int fmt; 125 int sync; 126 int synco; 127 int synci; 128 int fs_length; 129 int slots; 130 int slot_width; 131 int slot_mask; 132 int data_size; 133 unsigned int spdif_frm_cnt; 134 struct snd_aes_iec958 iec958; 135 struct mutex ctrl_lock; /* protect resources accessed by controls */ 136 }; 137 138 enum stm32_sai_fifo_th { 139 STM_SAI_FIFO_TH_EMPTY, 140 STM_SAI_FIFO_TH_QUARTER, 141 STM_SAI_FIFO_TH_HALF, 142 STM_SAI_FIFO_TH_3_QUARTER, 143 STM_SAI_FIFO_TH_FULL, 144 }; 145 146 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 147 { 148 switch (reg) { 149 case STM_SAI_CR1_REGX: 150 case STM_SAI_CR2_REGX: 151 case STM_SAI_FRCR_REGX: 152 case STM_SAI_SLOTR_REGX: 153 case STM_SAI_IMR_REGX: 154 case STM_SAI_SR_REGX: 155 case STM_SAI_CLRFR_REGX: 156 case STM_SAI_DR_REGX: 157 case STM_SAI_PDMCR_REGX: 158 case STM_SAI_PDMLY_REGX: 159 return true; 160 default: 161 return false; 162 } 163 } 164 165 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 166 { 167 switch (reg) { 168 case STM_SAI_DR_REGX: 169 return true; 170 default: 171 return false; 172 } 173 } 174 175 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 176 { 177 switch (reg) { 178 case STM_SAI_CR1_REGX: 179 case STM_SAI_CR2_REGX: 180 case STM_SAI_FRCR_REGX: 181 case STM_SAI_SLOTR_REGX: 182 case STM_SAI_IMR_REGX: 183 case STM_SAI_SR_REGX: 184 case STM_SAI_CLRFR_REGX: 185 case STM_SAI_DR_REGX: 186 case STM_SAI_PDMCR_REGX: 187 case STM_SAI_PDMLY_REGX: 188 return true; 189 default: 190 return false; 191 } 192 } 193 194 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 195 .reg_bits = 32, 196 .reg_stride = 4, 197 .val_bits = 32, 198 .max_register = STM_SAI_DR_REGX, 199 .readable_reg = stm32_sai_sub_readable_reg, 200 .volatile_reg = stm32_sai_sub_volatile_reg, 201 .writeable_reg = stm32_sai_sub_writeable_reg, 202 .fast_io = true, 203 }; 204 205 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 206 .reg_bits = 32, 207 .reg_stride = 4, 208 .val_bits = 32, 209 .max_register = STM_SAI_PDMLY_REGX, 210 .readable_reg = stm32_sai_sub_readable_reg, 211 .volatile_reg = stm32_sai_sub_volatile_reg, 212 .writeable_reg = stm32_sai_sub_writeable_reg, 213 .fast_io = true, 214 }; 215 216 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 217 struct snd_ctl_elem_info *uinfo) 218 { 219 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 220 uinfo->count = 1; 221 222 return 0; 223 } 224 225 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 226 struct snd_ctl_elem_value *uctl) 227 { 228 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 229 230 mutex_lock(&sai->ctrl_lock); 231 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 232 mutex_unlock(&sai->ctrl_lock); 233 234 return 0; 235 } 236 237 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 238 struct snd_ctl_elem_value *uctl) 239 { 240 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 241 242 mutex_lock(&sai->ctrl_lock); 243 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 244 mutex_unlock(&sai->ctrl_lock); 245 246 return 0; 247 } 248 249 static const struct snd_kcontrol_new iec958_ctls = { 250 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 251 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 252 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 253 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 254 .info = snd_pcm_iec958_info, 255 .get = snd_pcm_iec958_get, 256 .put = snd_pcm_iec958_put, 257 }; 258 259 struct stm32_sai_mclk_data { 260 struct clk_hw hw; 261 unsigned long freq; 262 struct stm32_sai_sub_data *sai_data; 263 }; 264 265 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 266 #define STM32_SAI_MAX_CLKS 1 267 268 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 269 unsigned long input_rate, 270 unsigned long output_rate) 271 { 272 int version = sai->pdata->conf->version; 273 int div; 274 275 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 276 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 277 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 278 return -EINVAL; 279 } 280 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 281 282 if (input_rate % div) 283 dev_dbg(&sai->pdev->dev, 284 "Rate not accurate. requested (%ld), actual (%ld)\n", 285 output_rate, input_rate / div); 286 287 return div; 288 } 289 290 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 291 unsigned int div) 292 { 293 int version = sai->pdata->conf->version; 294 int ret, cr1, mask; 295 296 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 297 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 298 return -EINVAL; 299 } 300 301 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 302 cr1 = SAI_XCR1_MCKDIV_SET(div); 303 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 304 if (ret < 0) 305 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 306 307 return ret; 308 } 309 310 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 311 unsigned long *prate) 312 { 313 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 314 struct stm32_sai_sub_data *sai = mclk->sai_data; 315 int div; 316 317 div = stm32_sai_get_clk_div(sai, *prate, rate); 318 if (div < 0) 319 return div; 320 321 mclk->freq = *prate / div; 322 323 return mclk->freq; 324 } 325 326 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 327 unsigned long parent_rate) 328 { 329 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 330 331 return mclk->freq; 332 } 333 334 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 335 unsigned long parent_rate) 336 { 337 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 338 struct stm32_sai_sub_data *sai = mclk->sai_data; 339 int div, ret; 340 341 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 342 if (div < 0) 343 return div; 344 345 ret = stm32_sai_set_clk_div(sai, div); 346 if (ret) 347 return ret; 348 349 mclk->freq = rate; 350 351 return 0; 352 } 353 354 static int stm32_sai_mclk_enable(struct clk_hw *hw) 355 { 356 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 357 struct stm32_sai_sub_data *sai = mclk->sai_data; 358 359 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 360 361 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 362 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 363 } 364 365 static void stm32_sai_mclk_disable(struct clk_hw *hw) 366 { 367 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 368 struct stm32_sai_sub_data *sai = mclk->sai_data; 369 370 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 371 372 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 373 } 374 375 static const struct clk_ops mclk_ops = { 376 .enable = stm32_sai_mclk_enable, 377 .disable = stm32_sai_mclk_disable, 378 .recalc_rate = stm32_sai_mclk_recalc_rate, 379 .round_rate = stm32_sai_mclk_round_rate, 380 .set_rate = stm32_sai_mclk_set_rate, 381 }; 382 383 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 384 { 385 struct clk_hw *hw; 386 struct stm32_sai_mclk_data *mclk; 387 struct device *dev = &sai->pdev->dev; 388 const char *pname = __clk_get_name(sai->sai_ck); 389 char *mclk_name, *p, *s = (char *)pname; 390 int ret, i = 0; 391 392 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 393 if (!mclk) 394 return -ENOMEM; 395 396 mclk_name = devm_kcalloc(dev, sizeof(char), 397 SAI_MCLK_NAME_LEN, GFP_KERNEL); 398 if (!mclk_name) 399 return -ENOMEM; 400 401 /* 402 * Forge mclk clock name from parent clock name and suffix. 403 * String after "_" char is stripped in parent name. 404 */ 405 p = mclk_name; 406 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 407 *p++ = *s++; 408 i++; 409 } 410 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 411 412 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 413 mclk->sai_data = sai; 414 hw = &mclk->hw; 415 416 dev_dbg(dev, "Register master clock %s\n", mclk_name); 417 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 418 if (ret) { 419 dev_err(dev, "mclk register returned %d\n", ret); 420 return ret; 421 } 422 sai->sai_mclk = hw->clk; 423 424 /* register mclk provider */ 425 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 426 } 427 428 static irqreturn_t stm32_sai_isr(int irq, void *devid) 429 { 430 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 431 struct platform_device *pdev = sai->pdev; 432 unsigned int sr, imr, flags; 433 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 434 435 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 436 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 437 438 flags = sr & imr; 439 if (!flags) 440 return IRQ_NONE; 441 442 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 443 SAI_XCLRFR_MASK); 444 445 if (!sai->substream) { 446 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 447 return IRQ_NONE; 448 } 449 450 if (flags & SAI_XIMR_OVRUDRIE) { 451 dev_err(&pdev->dev, "IRQ %s\n", 452 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 453 status = SNDRV_PCM_STATE_XRUN; 454 } 455 456 if (flags & SAI_XIMR_MUTEDETIE) 457 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 458 459 if (flags & SAI_XIMR_WCKCFGIE) { 460 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 461 status = SNDRV_PCM_STATE_DISCONNECTED; 462 } 463 464 if (flags & SAI_XIMR_CNRDYIE) 465 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 466 467 if (flags & SAI_XIMR_AFSDETIE) { 468 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 469 status = SNDRV_PCM_STATE_XRUN; 470 } 471 472 if (flags & SAI_XIMR_LFSDETIE) { 473 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 474 status = SNDRV_PCM_STATE_XRUN; 475 } 476 477 if (status != SNDRV_PCM_STATE_RUNNING) 478 snd_pcm_stop_xrun(sai->substream); 479 480 return IRQ_HANDLED; 481 } 482 483 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 484 int clk_id, unsigned int freq, int dir) 485 { 486 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 487 int ret; 488 489 if (dir == SND_SOC_CLOCK_OUT) { 490 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 491 SAI_XCR1_NODIV, 492 (unsigned int)~SAI_XCR1_NODIV); 493 if (ret < 0) 494 return ret; 495 496 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 497 sai->mclk_rate = freq; 498 499 if (sai->sai_mclk) { 500 ret = clk_set_rate_exclusive(sai->sai_mclk, 501 sai->mclk_rate); 502 if (ret) { 503 dev_err(cpu_dai->dev, 504 "Could not set mclk rate\n"); 505 return ret; 506 } 507 } 508 } 509 510 return 0; 511 } 512 513 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 514 u32 rx_mask, int slots, int slot_width) 515 { 516 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 517 int slotr, slotr_mask, slot_size; 518 519 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 520 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 521 return 0; 522 } 523 524 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 525 tx_mask, rx_mask, slots, slot_width); 526 527 switch (slot_width) { 528 case 16: 529 slot_size = SAI_SLOT_SIZE_16; 530 break; 531 case 32: 532 slot_size = SAI_SLOT_SIZE_32; 533 break; 534 default: 535 slot_size = SAI_SLOT_SIZE_AUTO; 536 break; 537 } 538 539 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 540 SAI_XSLOTR_NBSLOT_SET(slots - 1); 541 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 542 543 /* tx/rx mask set in machine init, if slot number defined in DT */ 544 if (STM_SAI_IS_PLAYBACK(sai)) { 545 sai->slot_mask = tx_mask; 546 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 547 } 548 549 if (STM_SAI_IS_CAPTURE(sai)) { 550 sai->slot_mask = rx_mask; 551 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 552 } 553 554 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 555 556 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 557 558 sai->slot_width = slot_width; 559 sai->slots = slots; 560 561 return 0; 562 } 563 564 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 565 { 566 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 567 int cr1, frcr = 0; 568 int cr1_mask, frcr_mask = 0; 569 int ret; 570 571 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 572 573 /* Do not generate master by default */ 574 cr1 = SAI_XCR1_NODIV; 575 cr1_mask = SAI_XCR1_NODIV; 576 577 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 578 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 579 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 580 goto conf_update; 581 } 582 583 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 584 585 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 586 /* SCK active high for all protocols */ 587 case SND_SOC_DAIFMT_I2S: 588 cr1 |= SAI_XCR1_CKSTR; 589 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 590 break; 591 /* Left justified */ 592 case SND_SOC_DAIFMT_MSB: 593 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 594 break; 595 /* Right justified */ 596 case SND_SOC_DAIFMT_LSB: 597 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 598 break; 599 case SND_SOC_DAIFMT_DSP_A: 600 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 601 break; 602 case SND_SOC_DAIFMT_DSP_B: 603 frcr |= SAI_XFRCR_FSPOL; 604 break; 605 default: 606 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 607 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 608 return -EINVAL; 609 } 610 611 cr1_mask |= SAI_XCR1_CKSTR; 612 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 613 SAI_XFRCR_FSDEF; 614 615 /* DAI clock strobing. Invert setting previously set */ 616 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 617 case SND_SOC_DAIFMT_NB_NF: 618 break; 619 case SND_SOC_DAIFMT_IB_NF: 620 cr1 ^= SAI_XCR1_CKSTR; 621 break; 622 case SND_SOC_DAIFMT_NB_IF: 623 frcr ^= SAI_XFRCR_FSPOL; 624 break; 625 case SND_SOC_DAIFMT_IB_IF: 626 /* Invert fs & sck */ 627 cr1 ^= SAI_XCR1_CKSTR; 628 frcr ^= SAI_XFRCR_FSPOL; 629 break; 630 default: 631 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 632 fmt & SND_SOC_DAIFMT_INV_MASK); 633 return -EINVAL; 634 } 635 cr1_mask |= SAI_XCR1_CKSTR; 636 frcr_mask |= SAI_XFRCR_FSPOL; 637 638 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 639 640 /* DAI clock master masks */ 641 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 642 case SND_SOC_DAIFMT_CBM_CFM: 643 /* codec is master */ 644 cr1 |= SAI_XCR1_SLAVE; 645 sai->master = false; 646 break; 647 case SND_SOC_DAIFMT_CBS_CFS: 648 sai->master = true; 649 break; 650 default: 651 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 652 fmt & SND_SOC_DAIFMT_MASTER_MASK); 653 return -EINVAL; 654 } 655 656 /* Set slave mode if sub-block is synchronized with another SAI */ 657 if (sai->sync) { 658 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 659 cr1 |= SAI_XCR1_SLAVE; 660 sai->master = false; 661 } 662 663 cr1_mask |= SAI_XCR1_SLAVE; 664 665 conf_update: 666 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 667 if (ret < 0) { 668 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 669 return ret; 670 } 671 672 sai->fmt = fmt; 673 674 return 0; 675 } 676 677 static int stm32_sai_startup(struct snd_pcm_substream *substream, 678 struct snd_soc_dai *cpu_dai) 679 { 680 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 681 int imr, cr2, ret; 682 683 sai->substream = substream; 684 685 ret = clk_prepare_enable(sai->sai_ck); 686 if (ret < 0) { 687 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 688 return ret; 689 } 690 691 /* Enable ITs */ 692 693 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 694 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 695 696 imr = SAI_XIMR_OVRUDRIE; 697 if (STM_SAI_IS_CAPTURE(sai)) { 698 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 699 if (cr2 & SAI_XCR2_MUTECNT_MASK) 700 imr |= SAI_XIMR_MUTEDETIE; 701 } 702 703 if (sai->master) 704 imr |= SAI_XIMR_WCKCFGIE; 705 else 706 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 707 708 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 709 SAI_XIMR_MASK, imr); 710 711 return 0; 712 } 713 714 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 715 struct snd_pcm_substream *substream, 716 struct snd_pcm_hw_params *params) 717 { 718 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 719 int cr1, cr1_mask, ret; 720 721 /* 722 * DMA bursts increment is set to 4 words. 723 * SAI fifo threshold is set to half fifo, to keep enough space 724 * for DMA incoming bursts. 725 */ 726 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 727 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 728 SAI_XCR2_FFLUSH | 729 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 730 731 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 732 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 733 sai->spdif_frm_cnt = 0; 734 return 0; 735 } 736 737 /* Mode, data format and channel config */ 738 cr1_mask = SAI_XCR1_DS_MASK; 739 switch (params_format(params)) { 740 case SNDRV_PCM_FORMAT_S8: 741 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 742 break; 743 case SNDRV_PCM_FORMAT_S16_LE: 744 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 745 break; 746 case SNDRV_PCM_FORMAT_S32_LE: 747 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 748 break; 749 default: 750 dev_err(cpu_dai->dev, "Data format not supported"); 751 return -EINVAL; 752 } 753 754 cr1_mask |= SAI_XCR1_MONO; 755 if ((sai->slots == 2) && (params_channels(params) == 1)) 756 cr1 |= SAI_XCR1_MONO; 757 758 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 759 if (ret < 0) { 760 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 761 return ret; 762 } 763 764 return 0; 765 } 766 767 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 768 { 769 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 770 int slotr, slot_sz; 771 772 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 773 774 /* 775 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 776 * By default slot width = data size, if not forced from DT 777 */ 778 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 779 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 780 sai->slot_width = sai->data_size; 781 782 if (sai->slot_width < sai->data_size) { 783 dev_err(cpu_dai->dev, 784 "Data size %d larger than slot width\n", 785 sai->data_size); 786 return -EINVAL; 787 } 788 789 /* Slot number is set to 2, if not specified in DT */ 790 if (!sai->slots) 791 sai->slots = 2; 792 793 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 794 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 795 SAI_XSLOTR_NBSLOT_MASK, 796 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 797 798 /* Set default slots mask if not already set from DT */ 799 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 800 sai->slot_mask = (1 << sai->slots) - 1; 801 regmap_update_bits(sai->regmap, 802 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 803 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 804 } 805 806 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 807 sai->slots, sai->slot_width); 808 809 return 0; 810 } 811 812 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 813 { 814 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 815 int fs_active, offset, format; 816 int frcr, frcr_mask; 817 818 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 819 sai->fs_length = sai->slot_width * sai->slots; 820 821 fs_active = sai->fs_length / 2; 822 if ((format == SND_SOC_DAIFMT_DSP_A) || 823 (format == SND_SOC_DAIFMT_DSP_B)) 824 fs_active = 1; 825 826 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 827 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 828 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 829 830 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 831 sai->fs_length, fs_active); 832 833 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 834 835 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 836 offset = sai->slot_width - sai->data_size; 837 838 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 839 SAI_XSLOTR_FBOFF_MASK, 840 SAI_XSLOTR_FBOFF_SET(offset)); 841 } 842 } 843 844 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 845 { 846 unsigned char *cs = sai->iec958.status; 847 848 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 849 cs[1] = IEC958_AES1_CON_GENERAL; 850 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 851 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 852 } 853 854 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 855 struct snd_pcm_runtime *runtime) 856 { 857 if (!runtime) 858 return; 859 860 /* Force the sample rate according to runtime rate */ 861 mutex_lock(&sai->ctrl_lock); 862 switch (runtime->rate) { 863 case 22050: 864 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 865 break; 866 case 44100: 867 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 868 break; 869 case 88200: 870 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 871 break; 872 case 176400: 873 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 874 break; 875 case 24000: 876 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 877 break; 878 case 48000: 879 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 880 break; 881 case 96000: 882 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 883 break; 884 case 192000: 885 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 886 break; 887 case 32000: 888 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 889 break; 890 default: 891 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 892 break; 893 } 894 mutex_unlock(&sai->ctrl_lock); 895 } 896 897 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 898 struct snd_pcm_hw_params *params) 899 { 900 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 901 int cr1, mask, div = 0; 902 int sai_clk_rate, mclk_ratio, den; 903 unsigned int rate = params_rate(params); 904 905 if (!(rate % 11025)) 906 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k); 907 else 908 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k); 909 sai_clk_rate = clk_get_rate(sai->sai_ck); 910 911 if (STM_SAI_IS_F4(sai->pdata)) { 912 /* mclk on (NODIV=0) 913 * mclk_rate = 256 * fs 914 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 915 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 916 * mclk off (NODIV=1) 917 * MCKDIV ignored. sck = sai_ck 918 */ 919 if (!sai->mclk_rate) 920 return 0; 921 922 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 923 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 924 2 * sai->mclk_rate); 925 if (div < 0) 926 return div; 927 } 928 } else { 929 /* 930 * TDM mode : 931 * mclk on 932 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 933 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 934 * mclk off 935 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 936 * Note: NOMCK/NODIV correspond to same bit. 937 */ 938 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 939 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 940 rate * 128); 941 if (div < 0) 942 return div; 943 } else { 944 if (sai->mclk_rate) { 945 mclk_ratio = sai->mclk_rate / rate; 946 if (mclk_ratio == 512) { 947 mask = SAI_XCR1_OSR; 948 cr1 = SAI_XCR1_OSR; 949 } else if (mclk_ratio != 256) { 950 dev_err(cpu_dai->dev, 951 "Wrong mclk ratio %d\n", 952 mclk_ratio); 953 return -EINVAL; 954 } 955 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 956 sai->mclk_rate); 957 if (div < 0) 958 return div; 959 } else { 960 /* mclk-fs not set, master clock not active */ 961 den = sai->fs_length * params_rate(params); 962 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 963 den); 964 if (div < 0) 965 return div; 966 } 967 } 968 } 969 970 return stm32_sai_set_clk_div(sai, div); 971 } 972 973 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 974 struct snd_pcm_hw_params *params, 975 struct snd_soc_dai *cpu_dai) 976 { 977 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 978 int ret; 979 980 sai->data_size = params_width(params); 981 982 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 983 /* Rate not already set in runtime structure */ 984 substream->runtime->rate = params_rate(params); 985 stm32_sai_set_iec958_status(sai, substream->runtime); 986 } else { 987 ret = stm32_sai_set_slots(cpu_dai); 988 if (ret < 0) 989 return ret; 990 stm32_sai_set_frame(cpu_dai); 991 } 992 993 ret = stm32_sai_set_config(cpu_dai, substream, params); 994 if (ret) 995 return ret; 996 997 if (sai->master) 998 ret = stm32_sai_configure_clock(cpu_dai, params); 999 1000 return ret; 1001 } 1002 1003 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1004 struct snd_soc_dai *cpu_dai) 1005 { 1006 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1007 int ret; 1008 1009 switch (cmd) { 1010 case SNDRV_PCM_TRIGGER_START: 1011 case SNDRV_PCM_TRIGGER_RESUME: 1012 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1013 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1014 1015 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1016 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1017 1018 /* Enable SAI */ 1019 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1020 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1021 if (ret < 0) 1022 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1023 break; 1024 case SNDRV_PCM_TRIGGER_SUSPEND: 1025 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1026 case SNDRV_PCM_TRIGGER_STOP: 1027 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1028 1029 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 1030 SAI_XIMR_MASK, 0); 1031 1032 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1033 SAI_XCR1_SAIEN, 1034 (unsigned int)~SAI_XCR1_SAIEN); 1035 1036 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1037 SAI_XCR1_DMAEN, 1038 (unsigned int)~SAI_XCR1_DMAEN); 1039 if (ret < 0) 1040 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1041 1042 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1043 sai->spdif_frm_cnt = 0; 1044 break; 1045 default: 1046 return -EINVAL; 1047 } 1048 1049 return ret; 1050 } 1051 1052 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1053 struct snd_soc_dai *cpu_dai) 1054 { 1055 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1056 1057 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1058 1059 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 1060 SAI_XCR1_NODIV); 1061 1062 clk_disable_unprepare(sai->sai_ck); 1063 1064 clk_rate_exclusive_put(sai->sai_mclk); 1065 1066 sai->substream = NULL; 1067 } 1068 1069 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1070 struct snd_soc_dai *cpu_dai) 1071 { 1072 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1073 1074 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1075 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1076 return snd_ctl_add(rtd->pcm->card, 1077 snd_ctl_new1(&iec958_ctls, sai)); 1078 } 1079 1080 return 0; 1081 } 1082 1083 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1084 { 1085 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1086 int cr1 = 0, cr1_mask; 1087 1088 sai->cpu_dai = cpu_dai; 1089 1090 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1091 /* 1092 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1093 * as it allows bytes, half-word and words transfers. (See DMA fifos 1094 * constraints). 1095 */ 1096 sai->dma_params.maxburst = 4; 1097 /* Buswidth will be set by framework at runtime */ 1098 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1099 1100 if (STM_SAI_IS_PLAYBACK(sai)) 1101 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1102 else 1103 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1104 1105 /* Next settings are not relevant for spdif mode */ 1106 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1107 return 0; 1108 1109 cr1_mask = SAI_XCR1_RX_TX; 1110 if (STM_SAI_IS_CAPTURE(sai)) 1111 cr1 |= SAI_XCR1_RX_TX; 1112 1113 /* Configure synchronization */ 1114 if (sai->sync == SAI_SYNC_EXTERNAL) { 1115 /* Configure synchro client and provider */ 1116 sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1117 sai->synco, sai->synci); 1118 } 1119 1120 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1121 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1122 1123 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 1124 } 1125 1126 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1127 .set_sysclk = stm32_sai_set_sysclk, 1128 .set_fmt = stm32_sai_set_dai_fmt, 1129 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1130 .startup = stm32_sai_startup, 1131 .hw_params = stm32_sai_hw_params, 1132 .trigger = stm32_sai_trigger, 1133 .shutdown = stm32_sai_shutdown, 1134 }; 1135 1136 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1137 int channel, unsigned long hwoff, 1138 void *buf, unsigned long bytes) 1139 { 1140 struct snd_pcm_runtime *runtime = substream->runtime; 1141 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1142 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 1143 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1144 int *ptr = (int *)(runtime->dma_area + hwoff + 1145 channel * (runtime->dma_bytes / runtime->channels)); 1146 ssize_t cnt = bytes_to_samples(runtime, bytes); 1147 unsigned int frm_cnt = sai->spdif_frm_cnt; 1148 unsigned int byte; 1149 unsigned int mask; 1150 1151 do { 1152 *ptr = ((*ptr >> 8) & 0x00ffffff); 1153 1154 /* Set channel status bit */ 1155 byte = frm_cnt >> 3; 1156 mask = 1 << (frm_cnt - (byte << 3)); 1157 if (sai->iec958.status[byte] & mask) 1158 *ptr |= 0x04000000; 1159 ptr++; 1160 1161 if (!(cnt % 2)) 1162 frm_cnt++; 1163 1164 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1165 frm_cnt = 0; 1166 } while (--cnt); 1167 sai->spdif_frm_cnt = frm_cnt; 1168 1169 return 0; 1170 } 1171 1172 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1173 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1174 .buffer_bytes_max = 8 * PAGE_SIZE, 1175 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1176 .period_bytes_max = PAGE_SIZE, 1177 .periods_min = 2, 1178 .periods_max = 8, 1179 }; 1180 1181 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 1182 { 1183 .probe = stm32_sai_dai_probe, 1184 .pcm_new = stm32_sai_pcm_new, 1185 .id = 1, /* avoid call to fmt_single_name() */ 1186 .playback = { 1187 .channels_min = 1, 1188 .channels_max = 2, 1189 .rate_min = 8000, 1190 .rate_max = 192000, 1191 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1192 /* DMA does not support 24 bits transfers */ 1193 .formats = 1194 SNDRV_PCM_FMTBIT_S8 | 1195 SNDRV_PCM_FMTBIT_S16_LE | 1196 SNDRV_PCM_FMTBIT_S32_LE, 1197 }, 1198 .ops = &stm32_sai_pcm_dai_ops, 1199 } 1200 }; 1201 1202 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 1203 { 1204 .probe = stm32_sai_dai_probe, 1205 .id = 1, /* avoid call to fmt_single_name() */ 1206 .capture = { 1207 .channels_min = 1, 1208 .channels_max = 2, 1209 .rate_min = 8000, 1210 .rate_max = 192000, 1211 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1212 /* DMA does not support 24 bits transfers */ 1213 .formats = 1214 SNDRV_PCM_FMTBIT_S8 | 1215 SNDRV_PCM_FMTBIT_S16_LE | 1216 SNDRV_PCM_FMTBIT_S32_LE, 1217 }, 1218 .ops = &stm32_sai_pcm_dai_ops, 1219 } 1220 }; 1221 1222 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1223 .pcm_hardware = &stm32_sai_pcm_hw, 1224 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1225 }; 1226 1227 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1228 .pcm_hardware = &stm32_sai_pcm_hw, 1229 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1230 .process = stm32_sai_pcm_process_spdif, 1231 }; 1232 1233 static const struct snd_soc_component_driver stm32_component = { 1234 .name = "stm32-sai", 1235 }; 1236 1237 static const struct of_device_id stm32_sai_sub_ids[] = { 1238 { .compatible = "st,stm32-sai-sub-a", 1239 .data = (void *)STM_SAI_A_ID}, 1240 { .compatible = "st,stm32-sai-sub-b", 1241 .data = (void *)STM_SAI_B_ID}, 1242 {} 1243 }; 1244 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1245 1246 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1247 struct stm32_sai_sub_data *sai) 1248 { 1249 struct device_node *np = pdev->dev.of_node; 1250 struct resource *res; 1251 void __iomem *base; 1252 struct of_phandle_args args; 1253 int ret; 1254 1255 if (!np) 1256 return -ENODEV; 1257 1258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1259 base = devm_ioremap_resource(&pdev->dev, res); 1260 if (IS_ERR(base)) 1261 return PTR_ERR(base); 1262 1263 sai->phys_addr = res->start; 1264 1265 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1266 /* Note: PDM registers not available for H7 sub-block B */ 1267 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 1268 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1269 1270 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 1271 base, sai->regmap_config); 1272 if (IS_ERR(sai->regmap)) { 1273 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 1274 return PTR_ERR(sai->regmap); 1275 } 1276 1277 /* Get direction property */ 1278 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1279 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1280 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1281 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1282 } else { 1283 dev_err(&pdev->dev, "Unsupported direction\n"); 1284 return -EINVAL; 1285 } 1286 1287 /* Get spdif iec60958 property */ 1288 sai->spdif = false; 1289 if (of_get_property(np, "st,iec60958", NULL)) { 1290 if (!STM_SAI_HAS_SPDIF(sai) || 1291 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1292 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1293 return -EINVAL; 1294 } 1295 stm32_sai_init_iec958_status(sai); 1296 sai->spdif = true; 1297 sai->master = true; 1298 } 1299 1300 /* Get synchronization property */ 1301 args.np = NULL; 1302 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1303 if (ret < 0 && ret != -ENOENT) { 1304 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1305 return ret; 1306 } 1307 1308 sai->sync = SAI_SYNC_NONE; 1309 if (args.np) { 1310 if (args.np == np) { 1311 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1312 of_node_put(args.np); 1313 return -EINVAL; 1314 } 1315 1316 sai->np_sync_provider = of_get_parent(args.np); 1317 if (!sai->np_sync_provider) { 1318 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1319 np); 1320 of_node_put(args.np); 1321 return -ENODEV; 1322 } 1323 1324 sai->sync = SAI_SYNC_INTERNAL; 1325 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1326 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1327 dev_err(&pdev->dev, 1328 "External synchro not supported\n"); 1329 of_node_put(args.np); 1330 return -EINVAL; 1331 } 1332 sai->sync = SAI_SYNC_EXTERNAL; 1333 1334 sai->synci = args.args[0]; 1335 if (sai->synci < 1 || 1336 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1337 dev_err(&pdev->dev, "Wrong SAI index\n"); 1338 of_node_put(args.np); 1339 return -EINVAL; 1340 } 1341 1342 if (of_property_match_string(args.np, "compatible", 1343 "st,stm32-sai-sub-a") >= 0) 1344 sai->synco = STM_SAI_SYNC_OUT_A; 1345 1346 if (of_property_match_string(args.np, "compatible", 1347 "st,stm32-sai-sub-b") >= 0) 1348 sai->synco = STM_SAI_SYNC_OUT_B; 1349 1350 if (!sai->synco) { 1351 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1352 of_node_put(args.np); 1353 return -EINVAL; 1354 } 1355 } 1356 1357 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1358 pdev->name, args.np->full_name); 1359 } 1360 1361 of_node_put(args.np); 1362 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1363 if (IS_ERR(sai->sai_ck)) { 1364 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 1365 return PTR_ERR(sai->sai_ck); 1366 } 1367 1368 if (STM_SAI_IS_F4(sai->pdata)) 1369 return 0; 1370 1371 /* Register mclk provider if requested */ 1372 if (of_find_property(np, "#clock-cells", NULL)) { 1373 ret = stm32_sai_add_mclk_provider(sai); 1374 if (ret < 0) 1375 return ret; 1376 } else { 1377 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 1378 if (IS_ERR(sai->sai_mclk)) { 1379 if (PTR_ERR(sai->sai_mclk) != -ENOENT) 1380 return PTR_ERR(sai->sai_mclk); 1381 sai->sai_mclk = NULL; 1382 } 1383 } 1384 1385 return 0; 1386 } 1387 1388 static int stm32_sai_sub_dais_init(struct platform_device *pdev, 1389 struct stm32_sai_sub_data *sai) 1390 { 1391 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 1392 sizeof(struct snd_soc_dai_driver), 1393 GFP_KERNEL); 1394 if (!sai->cpu_dai_drv) 1395 return -ENOMEM; 1396 1397 sai->cpu_dai_drv->name = dev_name(&pdev->dev); 1398 if (STM_SAI_IS_PLAYBACK(sai)) { 1399 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 1400 sizeof(stm32_sai_playback_dai)); 1401 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 1402 } else { 1403 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 1404 sizeof(stm32_sai_capture_dai)); 1405 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 1406 } 1407 1408 return 0; 1409 } 1410 1411 static int stm32_sai_sub_probe(struct platform_device *pdev) 1412 { 1413 struct stm32_sai_sub_data *sai; 1414 const struct of_device_id *of_id; 1415 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1416 int ret; 1417 1418 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1419 if (!sai) 1420 return -ENOMEM; 1421 1422 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1423 if (!of_id) 1424 return -EINVAL; 1425 sai->id = (uintptr_t)of_id->data; 1426 1427 sai->pdev = pdev; 1428 mutex_init(&sai->ctrl_lock); 1429 platform_set_drvdata(pdev, sai); 1430 1431 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1432 if (!sai->pdata) { 1433 dev_err(&pdev->dev, "Parent device data not available\n"); 1434 return -EINVAL; 1435 } 1436 1437 ret = stm32_sai_sub_parse_of(pdev, sai); 1438 if (ret) 1439 return ret; 1440 1441 ret = stm32_sai_sub_dais_init(pdev, sai); 1442 if (ret) 1443 return ret; 1444 1445 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1446 IRQF_SHARED, dev_name(&pdev->dev), sai); 1447 if (ret) { 1448 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1449 return ret; 1450 } 1451 1452 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1453 sai->cpu_dai_drv, 1); 1454 if (ret) 1455 return ret; 1456 1457 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1458 conf = &stm32_sai_pcm_config_spdif; 1459 1460 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1461 if (ret) { 1462 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1463 return ret; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static struct platform_driver stm32_sai_sub_driver = { 1470 .driver = { 1471 .name = "st,stm32-sai-sub", 1472 .of_match_table = stm32_sai_sub_ids, 1473 }, 1474 .probe = stm32_sai_sub_probe, 1475 }; 1476 1477 module_platform_driver(stm32_sai_sub_driver); 1478 1479 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1480 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1481 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1482 MODULE_LICENSE("GPL v2"); 1483