1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/regmap.h> 25 26 #include <sound/asoundef.h> 27 #include <sound/core.h> 28 #include <sound/dmaengine_pcm.h> 29 #include <sound/pcm_params.h> 30 31 #include "stm32_sai.h" 32 33 #define SAI_FREE_PROTOCOL 0x0 34 #define SAI_SPDIF_PROTOCOL 0x1 35 36 #define SAI_SLOT_SIZE_AUTO 0x0 37 #define SAI_SLOT_SIZE_16 0x1 38 #define SAI_SLOT_SIZE_32 0x2 39 40 #define SAI_DATASIZE_8 0x2 41 #define SAI_DATASIZE_10 0x3 42 #define SAI_DATASIZE_16 0x4 43 #define SAI_DATASIZE_20 0x5 44 #define SAI_DATASIZE_24 0x6 45 #define SAI_DATASIZE_32 0x7 46 47 #define STM_SAI_FIFO_SIZE 8 48 #define STM_SAI_DAI_NAME_SIZE 15 49 50 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 51 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 52 53 #define STM_SAI_A_ID 0x0 54 #define STM_SAI_B_ID 0x1 55 56 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 57 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 58 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 59 60 #define SAI_SYNC_NONE 0x0 61 #define SAI_SYNC_INTERNAL 0x1 62 #define SAI_SYNC_EXTERNAL 0x2 63 64 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 65 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif) 66 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 67 68 #define SAI_IEC60958_BLOCK_FRAMES 192 69 #define SAI_IEC60958_STATUS_BYTES 24 70 71 /** 72 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 73 * @pdev: device data pointer 74 * @regmap: SAI register map pointer 75 * @regmap_config: SAI sub block register map configuration pointer 76 * @dma_params: dma configuration data for rx or tx channel 77 * @cpu_dai_drv: DAI driver data pointer 78 * @cpu_dai: DAI runtime data pointer 79 * @substream: PCM substream data pointer 80 * @pdata: SAI block parent data pointer 81 * @np_sync_provider: synchronization provider node 82 * @sai_ck: kernel clock feeding the SAI clock generator 83 * @phys_addr: SAI registers physical base address 84 * @mclk_rate: SAI block master clock frequency (Hz). set at init 85 * @id: SAI sub block id corresponding to sub-block A or B 86 * @dir: SAI block direction (playback or capture). set at init 87 * @master: SAI block mode flag. (true=master, false=slave) set at init 88 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 89 * @fmt: SAI block format. relevant only for custom protocols. set at init 90 * @sync: SAI block synchronization mode. (none, internal or external) 91 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 92 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 93 * @fs_length: frame synchronization length. depends on protocol settings 94 * @slots: rx or tx slot number 95 * @slot_width: rx or tx slot width in bits 96 * @slot_mask: rx or tx active slots mask. set at init or at runtime 97 * @data_size: PCM data width. corresponds to PCM substream width. 98 * @spdif_frm_cnt: S/PDIF playback frame counter 99 * @spdif_status_bits: S/PDIF status bits 100 */ 101 struct stm32_sai_sub_data { 102 struct platform_device *pdev; 103 struct regmap *regmap; 104 const struct regmap_config *regmap_config; 105 struct snd_dmaengine_dai_dma_data dma_params; 106 struct snd_soc_dai_driver *cpu_dai_drv; 107 struct snd_soc_dai *cpu_dai; 108 struct snd_pcm_substream *substream; 109 struct stm32_sai_data *pdata; 110 struct device_node *np_sync_provider; 111 struct clk *sai_ck; 112 dma_addr_t phys_addr; 113 unsigned int mclk_rate; 114 unsigned int id; 115 int dir; 116 bool master; 117 bool spdif; 118 int fmt; 119 int sync; 120 int synco; 121 int synci; 122 int fs_length; 123 int slots; 124 int slot_width; 125 int slot_mask; 126 int data_size; 127 unsigned int spdif_frm_cnt; 128 unsigned char spdif_status_bits[SAI_IEC60958_STATUS_BYTES]; 129 }; 130 131 enum stm32_sai_fifo_th { 132 STM_SAI_FIFO_TH_EMPTY, 133 STM_SAI_FIFO_TH_QUARTER, 134 STM_SAI_FIFO_TH_HALF, 135 STM_SAI_FIFO_TH_3_QUARTER, 136 STM_SAI_FIFO_TH_FULL, 137 }; 138 139 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 140 { 141 switch (reg) { 142 case STM_SAI_CR1_REGX: 143 case STM_SAI_CR2_REGX: 144 case STM_SAI_FRCR_REGX: 145 case STM_SAI_SLOTR_REGX: 146 case STM_SAI_IMR_REGX: 147 case STM_SAI_SR_REGX: 148 case STM_SAI_CLRFR_REGX: 149 case STM_SAI_DR_REGX: 150 case STM_SAI_PDMCR_REGX: 151 case STM_SAI_PDMLY_REGX: 152 return true; 153 default: 154 return false; 155 } 156 } 157 158 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 159 { 160 switch (reg) { 161 case STM_SAI_DR_REGX: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 169 { 170 switch (reg) { 171 case STM_SAI_CR1_REGX: 172 case STM_SAI_CR2_REGX: 173 case STM_SAI_FRCR_REGX: 174 case STM_SAI_SLOTR_REGX: 175 case STM_SAI_IMR_REGX: 176 case STM_SAI_SR_REGX: 177 case STM_SAI_CLRFR_REGX: 178 case STM_SAI_DR_REGX: 179 case STM_SAI_PDMCR_REGX: 180 case STM_SAI_PDMLY_REGX: 181 return true; 182 default: 183 return false; 184 } 185 } 186 187 static const unsigned char default_status_bits[SAI_IEC60958_STATUS_BYTES] = { 188 0, 0, 0, IEC958_AES3_CON_FS_48000, 189 }; 190 191 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 192 .reg_bits = 32, 193 .reg_stride = 4, 194 .val_bits = 32, 195 .max_register = STM_SAI_DR_REGX, 196 .readable_reg = stm32_sai_sub_readable_reg, 197 .volatile_reg = stm32_sai_sub_volatile_reg, 198 .writeable_reg = stm32_sai_sub_writeable_reg, 199 .fast_io = true, 200 }; 201 202 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 203 .reg_bits = 32, 204 .reg_stride = 4, 205 .val_bits = 32, 206 .max_register = STM_SAI_PDMLY_REGX, 207 .readable_reg = stm32_sai_sub_readable_reg, 208 .volatile_reg = stm32_sai_sub_volatile_reg, 209 .writeable_reg = stm32_sai_sub_writeable_reg, 210 .fast_io = true, 211 }; 212 213 static irqreturn_t stm32_sai_isr(int irq, void *devid) 214 { 215 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 216 struct platform_device *pdev = sai->pdev; 217 unsigned int sr, imr, flags; 218 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 219 220 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 221 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 222 223 flags = sr & imr; 224 if (!flags) 225 return IRQ_NONE; 226 227 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 228 SAI_XCLRFR_MASK); 229 230 if (!sai->substream) { 231 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 232 return IRQ_NONE; 233 } 234 235 if (flags & SAI_XIMR_OVRUDRIE) { 236 dev_err(&pdev->dev, "IRQ %s\n", 237 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 238 status = SNDRV_PCM_STATE_XRUN; 239 } 240 241 if (flags & SAI_XIMR_MUTEDETIE) 242 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 243 244 if (flags & SAI_XIMR_WCKCFGIE) { 245 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 246 status = SNDRV_PCM_STATE_DISCONNECTED; 247 } 248 249 if (flags & SAI_XIMR_CNRDYIE) 250 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 251 252 if (flags & SAI_XIMR_AFSDETIE) { 253 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 254 status = SNDRV_PCM_STATE_XRUN; 255 } 256 257 if (flags & SAI_XIMR_LFSDETIE) { 258 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 259 status = SNDRV_PCM_STATE_XRUN; 260 } 261 262 if (status != SNDRV_PCM_STATE_RUNNING) { 263 snd_pcm_stream_lock(sai->substream); 264 snd_pcm_stop(sai->substream, SNDRV_PCM_STATE_XRUN); 265 snd_pcm_stream_unlock(sai->substream); 266 } 267 268 return IRQ_HANDLED; 269 } 270 271 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 272 int clk_id, unsigned int freq, int dir) 273 { 274 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 275 int ret; 276 277 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) { 278 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 279 SAI_XCR1_NODIV, 280 (unsigned int)~SAI_XCR1_NODIV); 281 if (ret < 0) 282 return ret; 283 284 sai->mclk_rate = freq; 285 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 286 } 287 288 return 0; 289 } 290 291 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 292 u32 rx_mask, int slots, int slot_width) 293 { 294 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 295 int slotr, slotr_mask, slot_size; 296 297 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 298 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 299 return 0; 300 } 301 302 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 303 tx_mask, rx_mask, slots, slot_width); 304 305 switch (slot_width) { 306 case 16: 307 slot_size = SAI_SLOT_SIZE_16; 308 break; 309 case 32: 310 slot_size = SAI_SLOT_SIZE_32; 311 break; 312 default: 313 slot_size = SAI_SLOT_SIZE_AUTO; 314 break; 315 } 316 317 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 318 SAI_XSLOTR_NBSLOT_SET(slots - 1); 319 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 320 321 /* tx/rx mask set in machine init, if slot number defined in DT */ 322 if (STM_SAI_IS_PLAYBACK(sai)) { 323 sai->slot_mask = tx_mask; 324 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 325 } 326 327 if (STM_SAI_IS_CAPTURE(sai)) { 328 sai->slot_mask = rx_mask; 329 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 330 } 331 332 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 333 334 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 335 336 sai->slot_width = slot_width; 337 sai->slots = slots; 338 339 return 0; 340 } 341 342 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 343 { 344 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 345 int cr1, frcr = 0; 346 int cr1_mask, frcr_mask = 0; 347 int ret; 348 349 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 350 351 /* Do not generate master by default */ 352 cr1 = SAI_XCR1_NODIV; 353 cr1_mask = SAI_XCR1_NODIV; 354 355 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 356 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 357 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 358 goto conf_update; 359 } 360 361 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 362 363 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 364 /* SCK active high for all protocols */ 365 case SND_SOC_DAIFMT_I2S: 366 cr1 |= SAI_XCR1_CKSTR; 367 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 368 break; 369 /* Left justified */ 370 case SND_SOC_DAIFMT_MSB: 371 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 372 break; 373 /* Right justified */ 374 case SND_SOC_DAIFMT_LSB: 375 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 376 break; 377 case SND_SOC_DAIFMT_DSP_A: 378 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 379 break; 380 case SND_SOC_DAIFMT_DSP_B: 381 frcr |= SAI_XFRCR_FSPOL; 382 break; 383 default: 384 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 385 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 386 return -EINVAL; 387 } 388 389 cr1_mask |= SAI_XCR1_CKSTR; 390 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 391 SAI_XFRCR_FSDEF; 392 393 /* DAI clock strobing. Invert setting previously set */ 394 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 395 case SND_SOC_DAIFMT_NB_NF: 396 break; 397 case SND_SOC_DAIFMT_IB_NF: 398 cr1 ^= SAI_XCR1_CKSTR; 399 break; 400 case SND_SOC_DAIFMT_NB_IF: 401 frcr ^= SAI_XFRCR_FSPOL; 402 break; 403 case SND_SOC_DAIFMT_IB_IF: 404 /* Invert fs & sck */ 405 cr1 ^= SAI_XCR1_CKSTR; 406 frcr ^= SAI_XFRCR_FSPOL; 407 break; 408 default: 409 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 410 fmt & SND_SOC_DAIFMT_INV_MASK); 411 return -EINVAL; 412 } 413 cr1_mask |= SAI_XCR1_CKSTR; 414 frcr_mask |= SAI_XFRCR_FSPOL; 415 416 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 417 418 /* DAI clock master masks */ 419 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 420 case SND_SOC_DAIFMT_CBM_CFM: 421 /* codec is master */ 422 cr1 |= SAI_XCR1_SLAVE; 423 sai->master = false; 424 break; 425 case SND_SOC_DAIFMT_CBS_CFS: 426 sai->master = true; 427 break; 428 default: 429 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 430 fmt & SND_SOC_DAIFMT_MASTER_MASK); 431 return -EINVAL; 432 } 433 434 /* Set slave mode if sub-block is synchronized with another SAI */ 435 if (sai->sync) { 436 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 437 cr1 |= SAI_XCR1_SLAVE; 438 sai->master = false; 439 } 440 441 cr1_mask |= SAI_XCR1_SLAVE; 442 443 conf_update: 444 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 445 if (ret < 0) { 446 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 447 return ret; 448 } 449 450 sai->fmt = fmt; 451 452 return 0; 453 } 454 455 static int stm32_sai_startup(struct snd_pcm_substream *substream, 456 struct snd_soc_dai *cpu_dai) 457 { 458 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 459 int imr, cr2, ret; 460 461 sai->substream = substream; 462 463 ret = clk_prepare_enable(sai->sai_ck); 464 if (ret < 0) { 465 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 466 return ret; 467 } 468 469 /* Enable ITs */ 470 471 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 472 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 473 474 imr = SAI_XIMR_OVRUDRIE; 475 if (STM_SAI_IS_CAPTURE(sai)) { 476 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 477 if (cr2 & SAI_XCR2_MUTECNT_MASK) 478 imr |= SAI_XIMR_MUTEDETIE; 479 } 480 481 if (sai->master) 482 imr |= SAI_XIMR_WCKCFGIE; 483 else 484 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 485 486 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 487 SAI_XIMR_MASK, imr); 488 489 return 0; 490 } 491 492 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 493 struct snd_pcm_substream *substream, 494 struct snd_pcm_hw_params *params) 495 { 496 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 497 int cr1, cr1_mask, ret; 498 499 /* 500 * DMA bursts increment is set to 4 words. 501 * SAI fifo threshold is set to half fifo, to keep enough space 502 * for DMA incoming bursts. 503 */ 504 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 505 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 506 SAI_XCR2_FFLUSH | 507 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 508 509 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 510 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 511 sai->spdif_frm_cnt = 0; 512 return 0; 513 } 514 515 /* Mode, data format and channel config */ 516 cr1_mask = SAI_XCR1_DS_MASK; 517 switch (params_format(params)) { 518 case SNDRV_PCM_FORMAT_S8: 519 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 520 break; 521 case SNDRV_PCM_FORMAT_S16_LE: 522 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 523 break; 524 case SNDRV_PCM_FORMAT_S32_LE: 525 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 526 break; 527 default: 528 dev_err(cpu_dai->dev, "Data format not supported"); 529 return -EINVAL; 530 } 531 532 cr1_mask |= SAI_XCR1_MONO; 533 if ((sai->slots == 2) && (params_channels(params) == 1)) 534 cr1 |= SAI_XCR1_MONO; 535 536 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 537 if (ret < 0) { 538 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 539 return ret; 540 } 541 542 return 0; 543 } 544 545 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 546 { 547 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 548 int slotr, slot_sz; 549 550 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 551 552 /* 553 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 554 * By default slot width = data size, if not forced from DT 555 */ 556 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 557 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 558 sai->slot_width = sai->data_size; 559 560 if (sai->slot_width < sai->data_size) { 561 dev_err(cpu_dai->dev, 562 "Data size %d larger than slot width\n", 563 sai->data_size); 564 return -EINVAL; 565 } 566 567 /* Slot number is set to 2, if not specified in DT */ 568 if (!sai->slots) 569 sai->slots = 2; 570 571 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 572 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 573 SAI_XSLOTR_NBSLOT_MASK, 574 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 575 576 /* Set default slots mask if not already set from DT */ 577 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 578 sai->slot_mask = (1 << sai->slots) - 1; 579 regmap_update_bits(sai->regmap, 580 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 581 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 582 } 583 584 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 585 sai->slots, sai->slot_width); 586 587 return 0; 588 } 589 590 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 591 { 592 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 593 int fs_active, offset, format; 594 int frcr, frcr_mask; 595 596 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 597 sai->fs_length = sai->slot_width * sai->slots; 598 599 fs_active = sai->fs_length / 2; 600 if ((format == SND_SOC_DAIFMT_DSP_A) || 601 (format == SND_SOC_DAIFMT_DSP_B)) 602 fs_active = 1; 603 604 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 605 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 606 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 607 608 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 609 sai->fs_length, fs_active); 610 611 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 612 613 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 614 offset = sai->slot_width - sai->data_size; 615 616 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 617 SAI_XSLOTR_FBOFF_MASK, 618 SAI_XSLOTR_FBOFF_SET(offset)); 619 } 620 } 621 622 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 623 struct snd_pcm_hw_params *params) 624 { 625 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 626 int cr1, mask, div = 0; 627 int sai_clk_rate, mclk_ratio, den, ret; 628 int version = sai->pdata->conf->version; 629 unsigned int rate = params_rate(params); 630 631 if (!sai->mclk_rate) { 632 dev_err(cpu_dai->dev, "Mclk rate is null\n"); 633 return -EINVAL; 634 } 635 636 if (!(rate % 11025)) 637 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k); 638 else 639 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k); 640 sai_clk_rate = clk_get_rate(sai->sai_ck); 641 642 if (STM_SAI_IS_F4(sai->pdata)) { 643 /* 644 * mclk_rate = 256 * fs 645 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 646 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 647 */ 648 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) 649 div = DIV_ROUND_CLOSEST(sai_clk_rate, 650 2 * sai->mclk_rate); 651 } else { 652 /* 653 * TDM mode : 654 * mclk on 655 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 656 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 657 * mclk off 658 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 659 * Note: NOMCK/NODIV correspond to same bit. 660 */ 661 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 662 div = DIV_ROUND_CLOSEST(sai_clk_rate, 663 (params_rate(params) * 128)); 664 } else { 665 if (sai->mclk_rate) { 666 mclk_ratio = sai->mclk_rate / rate; 667 if (mclk_ratio == 512) { 668 mask = SAI_XCR1_OSR; 669 cr1 = SAI_XCR1_OSR; 670 } else if (mclk_ratio != 256) { 671 dev_err(cpu_dai->dev, 672 "Wrong mclk ratio %d\n", 673 mclk_ratio); 674 return -EINVAL; 675 } 676 div = DIV_ROUND_CLOSEST(sai_clk_rate, 677 sai->mclk_rate); 678 } else { 679 /* mclk-fs not set, master clock not active */ 680 den = sai->fs_length * params_rate(params); 681 div = DIV_ROUND_CLOSEST(sai_clk_rate, den); 682 } 683 } 684 } 685 686 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 687 dev_err(cpu_dai->dev, "Divider %d out of range\n", div); 688 return -EINVAL; 689 } 690 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div); 691 692 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 693 cr1 = SAI_XCR1_MCKDIV_SET(div); 694 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 695 if (ret < 0) { 696 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 697 return ret; 698 } 699 700 return 0; 701 } 702 703 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 704 struct snd_pcm_hw_params *params, 705 struct snd_soc_dai *cpu_dai) 706 { 707 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 708 int ret; 709 710 sai->data_size = params_width(params); 711 712 if (!STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 713 ret = stm32_sai_set_slots(cpu_dai); 714 if (ret < 0) 715 return ret; 716 stm32_sai_set_frame(cpu_dai); 717 } 718 719 ret = stm32_sai_set_config(cpu_dai, substream, params); 720 if (ret) 721 return ret; 722 723 if (sai->master) 724 ret = stm32_sai_configure_clock(cpu_dai, params); 725 726 return ret; 727 } 728 729 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 730 struct snd_soc_dai *cpu_dai) 731 { 732 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 733 int ret; 734 735 switch (cmd) { 736 case SNDRV_PCM_TRIGGER_START: 737 case SNDRV_PCM_TRIGGER_RESUME: 738 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 739 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 740 741 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 742 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 743 744 /* Enable SAI */ 745 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 746 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 747 if (ret < 0) 748 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 749 break; 750 case SNDRV_PCM_TRIGGER_SUSPEND: 751 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 752 case SNDRV_PCM_TRIGGER_STOP: 753 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 754 755 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 756 SAI_XIMR_MASK, 0); 757 758 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 759 SAI_XCR1_SAIEN, 760 (unsigned int)~SAI_XCR1_SAIEN); 761 762 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 763 SAI_XCR1_DMAEN, 764 (unsigned int)~SAI_XCR1_DMAEN); 765 if (ret < 0) 766 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 767 768 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 769 sai->spdif_frm_cnt = 0; 770 break; 771 default: 772 return -EINVAL; 773 } 774 775 return ret; 776 } 777 778 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 779 struct snd_soc_dai *cpu_dai) 780 { 781 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 782 783 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 784 785 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 786 SAI_XCR1_NODIV); 787 788 clk_disable_unprepare(sai->sai_ck); 789 sai->substream = NULL; 790 } 791 792 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 793 { 794 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 795 int cr1 = 0, cr1_mask; 796 797 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 798 /* 799 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 800 * as it allows bytes, half-word and words transfers. (See DMA fifos 801 * constraints). 802 */ 803 sai->dma_params.maxburst = 4; 804 /* Buswidth will be set by framework at runtime */ 805 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 806 807 if (STM_SAI_IS_PLAYBACK(sai)) 808 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 809 else 810 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 811 812 cr1_mask = SAI_XCR1_RX_TX; 813 if (STM_SAI_IS_CAPTURE(sai)) 814 cr1 |= SAI_XCR1_RX_TX; 815 816 /* Configure synchronization */ 817 if (sai->sync == SAI_SYNC_EXTERNAL) { 818 /* Configure synchro client and provider */ 819 sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 820 sai->synco, sai->synci); 821 } 822 823 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 824 memcpy(sai->spdif_status_bits, default_status_bits, 825 sizeof(default_status_bits)); 826 827 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 828 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 829 830 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 831 } 832 833 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 834 .set_sysclk = stm32_sai_set_sysclk, 835 .set_fmt = stm32_sai_set_dai_fmt, 836 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 837 .startup = stm32_sai_startup, 838 .hw_params = stm32_sai_hw_params, 839 .trigger = stm32_sai_trigger, 840 .shutdown = stm32_sai_shutdown, 841 }; 842 843 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 844 int channel, unsigned long hwoff, 845 void *buf, unsigned long bytes) 846 { 847 struct snd_pcm_runtime *runtime = substream->runtime; 848 struct snd_soc_pcm_runtime *rtd = substream->private_data; 849 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 850 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 851 int *ptr = (int *)(runtime->dma_area + hwoff + 852 channel * (runtime->dma_bytes / runtime->channels)); 853 ssize_t cnt = bytes_to_samples(runtime, bytes); 854 unsigned int frm_cnt = sai->spdif_frm_cnt; 855 unsigned int byte; 856 unsigned int mask; 857 858 do { 859 *ptr = ((*ptr >> 8) & 0x00ffffff); 860 861 /* Set channel status bit */ 862 byte = frm_cnt >> 3; 863 mask = 1 << (frm_cnt - (byte << 3)); 864 if (sai->spdif_status_bits[byte] & mask) 865 *ptr |= 0x04000000; 866 ptr++; 867 868 if (!(cnt % 2)) 869 frm_cnt++; 870 871 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 872 frm_cnt = 0; 873 } while (--cnt); 874 sai->spdif_frm_cnt = frm_cnt; 875 876 return 0; 877 } 878 879 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 880 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 881 .buffer_bytes_max = 8 * PAGE_SIZE, 882 .period_bytes_min = 1024, /* 5ms at 48kHz */ 883 .period_bytes_max = PAGE_SIZE, 884 .periods_min = 2, 885 .periods_max = 8, 886 }; 887 888 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 889 { 890 .probe = stm32_sai_dai_probe, 891 .id = 1, /* avoid call to fmt_single_name() */ 892 .playback = { 893 .channels_min = 1, 894 .channels_max = 2, 895 .rate_min = 8000, 896 .rate_max = 192000, 897 .rates = SNDRV_PCM_RATE_CONTINUOUS, 898 /* DMA does not support 24 bits transfers */ 899 .formats = 900 SNDRV_PCM_FMTBIT_S8 | 901 SNDRV_PCM_FMTBIT_S16_LE | 902 SNDRV_PCM_FMTBIT_S32_LE, 903 }, 904 .ops = &stm32_sai_pcm_dai_ops, 905 } 906 }; 907 908 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 909 { 910 .probe = stm32_sai_dai_probe, 911 .id = 1, /* avoid call to fmt_single_name() */ 912 .capture = { 913 .channels_min = 1, 914 .channels_max = 2, 915 .rate_min = 8000, 916 .rate_max = 192000, 917 .rates = SNDRV_PCM_RATE_CONTINUOUS, 918 /* DMA does not support 24 bits transfers */ 919 .formats = 920 SNDRV_PCM_FMTBIT_S8 | 921 SNDRV_PCM_FMTBIT_S16_LE | 922 SNDRV_PCM_FMTBIT_S32_LE, 923 }, 924 .ops = &stm32_sai_pcm_dai_ops, 925 } 926 }; 927 928 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 929 .pcm_hardware = &stm32_sai_pcm_hw, 930 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 931 }; 932 933 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 934 .pcm_hardware = &stm32_sai_pcm_hw, 935 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 936 .process = stm32_sai_pcm_process_spdif, 937 }; 938 939 static const struct snd_soc_component_driver stm32_component = { 940 .name = "stm32-sai", 941 }; 942 943 static const struct of_device_id stm32_sai_sub_ids[] = { 944 { .compatible = "st,stm32-sai-sub-a", 945 .data = (void *)STM_SAI_A_ID}, 946 { .compatible = "st,stm32-sai-sub-b", 947 .data = (void *)STM_SAI_B_ID}, 948 {} 949 }; 950 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 951 952 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 953 struct stm32_sai_sub_data *sai) 954 { 955 struct device_node *np = pdev->dev.of_node; 956 struct resource *res; 957 void __iomem *base; 958 struct of_phandle_args args; 959 int ret; 960 961 if (!np) 962 return -ENODEV; 963 964 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 965 base = devm_ioremap_resource(&pdev->dev, res); 966 if (IS_ERR(base)) 967 return PTR_ERR(base); 968 969 sai->phys_addr = res->start; 970 971 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 972 /* Note: PDM registers not available for H7 sub-block B */ 973 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 974 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 975 976 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 977 base, sai->regmap_config); 978 if (IS_ERR(sai->regmap)) { 979 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 980 return PTR_ERR(sai->regmap); 981 } 982 983 /* Get direction property */ 984 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 985 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 986 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 987 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 988 } else { 989 dev_err(&pdev->dev, "Unsupported direction\n"); 990 return -EINVAL; 991 } 992 993 /* Get spdif iec60958 property */ 994 sai->spdif = false; 995 if (of_get_property(np, "st,iec60958", NULL)) { 996 if (!STM_SAI_HAS_SPDIF(sai) || 997 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 998 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 999 return -EINVAL; 1000 } 1001 sai->spdif = true; 1002 sai->master = true; 1003 } 1004 1005 /* Get synchronization property */ 1006 args.np = NULL; 1007 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1008 if (ret < 0 && ret != -ENOENT) { 1009 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1010 return ret; 1011 } 1012 1013 sai->sync = SAI_SYNC_NONE; 1014 if (args.np) { 1015 if (args.np == np) { 1016 dev_err(&pdev->dev, "%s sync own reference\n", 1017 np->name); 1018 of_node_put(args.np); 1019 return -EINVAL; 1020 } 1021 1022 sai->np_sync_provider = of_get_parent(args.np); 1023 if (!sai->np_sync_provider) { 1024 dev_err(&pdev->dev, "%s parent node not found\n", 1025 np->name); 1026 of_node_put(args.np); 1027 return -ENODEV; 1028 } 1029 1030 sai->sync = SAI_SYNC_INTERNAL; 1031 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1032 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1033 dev_err(&pdev->dev, 1034 "External synchro not supported\n"); 1035 of_node_put(args.np); 1036 return -EINVAL; 1037 } 1038 sai->sync = SAI_SYNC_EXTERNAL; 1039 1040 sai->synci = args.args[0]; 1041 if (sai->synci < 1 || 1042 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1043 dev_err(&pdev->dev, "Wrong SAI index\n"); 1044 of_node_put(args.np); 1045 return -EINVAL; 1046 } 1047 1048 if (of_property_match_string(args.np, "compatible", 1049 "st,stm32-sai-sub-a") >= 0) 1050 sai->synco = STM_SAI_SYNC_OUT_A; 1051 1052 if (of_property_match_string(args.np, "compatible", 1053 "st,stm32-sai-sub-b") >= 0) 1054 sai->synco = STM_SAI_SYNC_OUT_B; 1055 1056 if (!sai->synco) { 1057 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1058 of_node_put(args.np); 1059 return -EINVAL; 1060 } 1061 } 1062 1063 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1064 pdev->name, args.np->full_name); 1065 } 1066 1067 of_node_put(args.np); 1068 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1069 if (IS_ERR(sai->sai_ck)) { 1070 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 1071 return PTR_ERR(sai->sai_ck); 1072 } 1073 1074 return 0; 1075 } 1076 1077 static int stm32_sai_sub_dais_init(struct platform_device *pdev, 1078 struct stm32_sai_sub_data *sai) 1079 { 1080 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 1081 sizeof(struct snd_soc_dai_driver), 1082 GFP_KERNEL); 1083 if (!sai->cpu_dai_drv) 1084 return -ENOMEM; 1085 1086 sai->cpu_dai_drv->name = dev_name(&pdev->dev); 1087 if (STM_SAI_IS_PLAYBACK(sai)) { 1088 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 1089 sizeof(stm32_sai_playback_dai)); 1090 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 1091 } else { 1092 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 1093 sizeof(stm32_sai_capture_dai)); 1094 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 1095 } 1096 1097 return 0; 1098 } 1099 1100 static int stm32_sai_sub_probe(struct platform_device *pdev) 1101 { 1102 struct stm32_sai_sub_data *sai; 1103 const struct of_device_id *of_id; 1104 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1105 int ret; 1106 1107 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1108 if (!sai) 1109 return -ENOMEM; 1110 1111 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1112 if (!of_id) 1113 return -EINVAL; 1114 sai->id = (uintptr_t)of_id->data; 1115 1116 sai->pdev = pdev; 1117 platform_set_drvdata(pdev, sai); 1118 1119 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1120 if (!sai->pdata) { 1121 dev_err(&pdev->dev, "Parent device data not available\n"); 1122 return -EINVAL; 1123 } 1124 1125 ret = stm32_sai_sub_parse_of(pdev, sai); 1126 if (ret) 1127 return ret; 1128 1129 ret = stm32_sai_sub_dais_init(pdev, sai); 1130 if (ret) 1131 return ret; 1132 1133 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1134 IRQF_SHARED, dev_name(&pdev->dev), sai); 1135 if (ret) { 1136 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1137 return ret; 1138 } 1139 1140 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1141 sai->cpu_dai_drv, 1); 1142 if (ret) 1143 return ret; 1144 1145 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1146 conf = &stm32_sai_pcm_config_spdif; 1147 1148 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1149 if (ret) { 1150 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1151 return ret; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static struct platform_driver stm32_sai_sub_driver = { 1158 .driver = { 1159 .name = "st,stm32-sai-sub", 1160 .of_match_table = stm32_sai_sub_ids, 1161 }, 1162 .probe = stm32_sai_sub_probe, 1163 }; 1164 1165 module_platform_driver(stm32_sai_sub_driver); 1166 1167 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1168 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1169 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1170 MODULE_LICENSE("GPL v2"); 1171