1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/regmap.h> 16 17 #include <sound/asoundef.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 22 #include "stm32_sai.h" 23 24 #define SAI_FREE_PROTOCOL 0x0 25 #define SAI_SPDIF_PROTOCOL 0x1 26 27 #define SAI_SLOT_SIZE_AUTO 0x0 28 #define SAI_SLOT_SIZE_16 0x1 29 #define SAI_SLOT_SIZE_32 0x2 30 31 #define SAI_DATASIZE_8 0x2 32 #define SAI_DATASIZE_10 0x3 33 #define SAI_DATASIZE_16 0x4 34 #define SAI_DATASIZE_20 0x5 35 #define SAI_DATASIZE_24 0x6 36 #define SAI_DATASIZE_32 0x7 37 38 #define STM_SAI_DAI_NAME_SIZE 15 39 40 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 41 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 42 43 #define STM_SAI_A_ID 0x0 44 #define STM_SAI_B_ID 0x1 45 46 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 47 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 48 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 49 50 #define SAI_SYNC_NONE 0x0 51 #define SAI_SYNC_INTERNAL 0x1 52 #define SAI_SYNC_EXTERNAL 0x2 53 54 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 55 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 56 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 57 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 58 59 #define SAI_IEC60958_BLOCK_FRAMES 192 60 #define SAI_IEC60958_STATUS_BYTES 24 61 62 #define SAI_MCLK_NAME_LEN 32 63 #define SAI_RATE_11K 11025 64 65 /** 66 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 67 * @pdev: device data pointer 68 * @regmap: SAI register map pointer 69 * @regmap_config: SAI sub block register map configuration pointer 70 * @dma_params: dma configuration data for rx or tx channel 71 * @cpu_dai_drv: DAI driver data pointer 72 * @cpu_dai: DAI runtime data pointer 73 * @substream: PCM substream data pointer 74 * @pdata: SAI block parent data pointer 75 * @np_sync_provider: synchronization provider node 76 * @sai_ck: kernel clock feeding the SAI clock generator 77 * @sai_mclk: master clock from SAI mclk provider 78 * @phys_addr: SAI registers physical base address 79 * @mclk_rate: SAI block master clock frequency (Hz). set at init 80 * @id: SAI sub block id corresponding to sub-block A or B 81 * @dir: SAI block direction (playback or capture). set at init 82 * @master: SAI block mode flag. (true=master, false=slave) set at init 83 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 84 * @fmt: SAI block format. relevant only for custom protocols. set at init 85 * @sync: SAI block synchronization mode. (none, internal or external) 86 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 87 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 88 * @fs_length: frame synchronization length. depends on protocol settings 89 * @slots: rx or tx slot number 90 * @slot_width: rx or tx slot width in bits 91 * @slot_mask: rx or tx active slots mask. set at init or at runtime 92 * @data_size: PCM data width. corresponds to PCM substream width. 93 * @spdif_frm_cnt: S/PDIF playback frame counter 94 * @iec958: iec958 data 95 * @ctrl_lock: control lock 96 * @irq_lock: prevent race condition with IRQ 97 */ 98 struct stm32_sai_sub_data { 99 struct platform_device *pdev; 100 struct regmap *regmap; 101 const struct regmap_config *regmap_config; 102 struct snd_dmaengine_dai_dma_data dma_params; 103 struct snd_soc_dai_driver cpu_dai_drv; 104 struct snd_soc_dai *cpu_dai; 105 struct snd_pcm_substream *substream; 106 struct stm32_sai_data *pdata; 107 struct device_node *np_sync_provider; 108 struct clk *sai_ck; 109 struct clk *sai_mclk; 110 dma_addr_t phys_addr; 111 unsigned int mclk_rate; 112 unsigned int id; 113 int dir; 114 bool master; 115 bool spdif; 116 int fmt; 117 int sync; 118 int synco; 119 int synci; 120 int fs_length; 121 int slots; 122 int slot_width; 123 int slot_mask; 124 int data_size; 125 unsigned int spdif_frm_cnt; 126 struct snd_aes_iec958 iec958; 127 struct mutex ctrl_lock; /* protect resources accessed by controls */ 128 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 129 }; 130 131 enum stm32_sai_fifo_th { 132 STM_SAI_FIFO_TH_EMPTY, 133 STM_SAI_FIFO_TH_QUARTER, 134 STM_SAI_FIFO_TH_HALF, 135 STM_SAI_FIFO_TH_3_QUARTER, 136 STM_SAI_FIFO_TH_FULL, 137 }; 138 139 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 140 { 141 switch (reg) { 142 case STM_SAI_CR1_REGX: 143 case STM_SAI_CR2_REGX: 144 case STM_SAI_FRCR_REGX: 145 case STM_SAI_SLOTR_REGX: 146 case STM_SAI_IMR_REGX: 147 case STM_SAI_SR_REGX: 148 case STM_SAI_CLRFR_REGX: 149 case STM_SAI_DR_REGX: 150 case STM_SAI_PDMCR_REGX: 151 case STM_SAI_PDMLY_REGX: 152 return true; 153 default: 154 return false; 155 } 156 } 157 158 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 159 { 160 switch (reg) { 161 case STM_SAI_DR_REGX: 162 case STM_SAI_SR_REGX: 163 return true; 164 default: 165 return false; 166 } 167 } 168 169 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 170 { 171 switch (reg) { 172 case STM_SAI_CR1_REGX: 173 case STM_SAI_CR2_REGX: 174 case STM_SAI_FRCR_REGX: 175 case STM_SAI_SLOTR_REGX: 176 case STM_SAI_IMR_REGX: 177 case STM_SAI_CLRFR_REGX: 178 case STM_SAI_DR_REGX: 179 case STM_SAI_PDMCR_REGX: 180 case STM_SAI_PDMLY_REGX: 181 return true; 182 default: 183 return false; 184 } 185 } 186 187 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 188 .reg_bits = 32, 189 .reg_stride = 4, 190 .val_bits = 32, 191 .max_register = STM_SAI_DR_REGX, 192 .readable_reg = stm32_sai_sub_readable_reg, 193 .volatile_reg = stm32_sai_sub_volatile_reg, 194 .writeable_reg = stm32_sai_sub_writeable_reg, 195 .fast_io = true, 196 .cache_type = REGCACHE_FLAT, 197 }; 198 199 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 200 .reg_bits = 32, 201 .reg_stride = 4, 202 .val_bits = 32, 203 .max_register = STM_SAI_PDMLY_REGX, 204 .readable_reg = stm32_sai_sub_readable_reg, 205 .volatile_reg = stm32_sai_sub_volatile_reg, 206 .writeable_reg = stm32_sai_sub_writeable_reg, 207 .fast_io = true, 208 .cache_type = REGCACHE_FLAT, 209 }; 210 211 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 212 struct snd_ctl_elem_info *uinfo) 213 { 214 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 215 uinfo->count = 1; 216 217 return 0; 218 } 219 220 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 221 struct snd_ctl_elem_value *uctl) 222 { 223 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 224 225 mutex_lock(&sai->ctrl_lock); 226 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 227 mutex_unlock(&sai->ctrl_lock); 228 229 return 0; 230 } 231 232 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 233 struct snd_ctl_elem_value *uctl) 234 { 235 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 236 237 mutex_lock(&sai->ctrl_lock); 238 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 239 mutex_unlock(&sai->ctrl_lock); 240 241 return 0; 242 } 243 244 static const struct snd_kcontrol_new iec958_ctls = { 245 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 246 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 247 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 248 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 249 .info = snd_pcm_iec958_info, 250 .get = snd_pcm_iec958_get, 251 .put = snd_pcm_iec958_put, 252 }; 253 254 struct stm32_sai_mclk_data { 255 struct clk_hw hw; 256 unsigned long freq; 257 struct stm32_sai_sub_data *sai_data; 258 }; 259 260 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 261 #define STM32_SAI_MAX_CLKS 1 262 263 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 264 unsigned long input_rate, 265 unsigned long output_rate) 266 { 267 int version = sai->pdata->conf.version; 268 int div; 269 270 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 271 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 272 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 273 return -EINVAL; 274 } 275 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 276 277 if (input_rate % div) 278 dev_dbg(&sai->pdev->dev, 279 "Rate not accurate. requested (%ld), actual (%ld)\n", 280 output_rate, input_rate / div); 281 282 return div; 283 } 284 285 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 286 unsigned int div) 287 { 288 int version = sai->pdata->conf.version; 289 int ret, cr1, mask; 290 291 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 292 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 293 return -EINVAL; 294 } 295 296 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 297 cr1 = SAI_XCR1_MCKDIV_SET(div); 298 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 299 if (ret < 0) 300 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 301 302 return ret; 303 } 304 305 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, 306 unsigned int rate) 307 { 308 struct platform_device *pdev = sai->pdev; 309 struct clk *parent_clk = sai->pdata->clk_x8k; 310 int ret; 311 312 if (!(rate % SAI_RATE_11K)) 313 parent_clk = sai->pdata->clk_x11k; 314 315 ret = clk_set_parent(sai->sai_ck, parent_clk); 316 if (ret) 317 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 318 ret, ret == -EBUSY ? 319 "Active stream rates conflict\n" : "\n"); 320 321 return ret; 322 } 323 324 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 325 unsigned long *prate) 326 { 327 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 328 struct stm32_sai_sub_data *sai = mclk->sai_data; 329 int div; 330 331 div = stm32_sai_get_clk_div(sai, *prate, rate); 332 if (div < 0) 333 return div; 334 335 mclk->freq = *prate / div; 336 337 return mclk->freq; 338 } 339 340 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 341 unsigned long parent_rate) 342 { 343 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 344 345 return mclk->freq; 346 } 347 348 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 349 unsigned long parent_rate) 350 { 351 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 352 struct stm32_sai_sub_data *sai = mclk->sai_data; 353 int div, ret; 354 355 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 356 if (div < 0) 357 return div; 358 359 ret = stm32_sai_set_clk_div(sai, div); 360 if (ret) 361 return ret; 362 363 mclk->freq = rate; 364 365 return 0; 366 } 367 368 static int stm32_sai_mclk_enable(struct clk_hw *hw) 369 { 370 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 371 struct stm32_sai_sub_data *sai = mclk->sai_data; 372 373 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 374 375 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 376 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 377 } 378 379 static void stm32_sai_mclk_disable(struct clk_hw *hw) 380 { 381 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 382 struct stm32_sai_sub_data *sai = mclk->sai_data; 383 384 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 385 386 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 387 } 388 389 static const struct clk_ops mclk_ops = { 390 .enable = stm32_sai_mclk_enable, 391 .disable = stm32_sai_mclk_disable, 392 .recalc_rate = stm32_sai_mclk_recalc_rate, 393 .round_rate = stm32_sai_mclk_round_rate, 394 .set_rate = stm32_sai_mclk_set_rate, 395 }; 396 397 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 398 { 399 struct clk_hw *hw; 400 struct stm32_sai_mclk_data *mclk; 401 struct device *dev = &sai->pdev->dev; 402 const char *pname = __clk_get_name(sai->sai_ck); 403 char *mclk_name, *p, *s = (char *)pname; 404 int ret, i = 0; 405 406 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 407 if (!mclk) 408 return -ENOMEM; 409 410 mclk_name = devm_kcalloc(dev, sizeof(char), 411 SAI_MCLK_NAME_LEN, GFP_KERNEL); 412 if (!mclk_name) 413 return -ENOMEM; 414 415 /* 416 * Forge mclk clock name from parent clock name and suffix. 417 * String after "_" char is stripped in parent name. 418 */ 419 p = mclk_name; 420 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 421 *p++ = *s++; 422 i++; 423 } 424 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 425 426 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 427 mclk->sai_data = sai; 428 hw = &mclk->hw; 429 430 dev_dbg(dev, "Register master clock %s\n", mclk_name); 431 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 432 if (ret) { 433 dev_err(dev, "mclk register returned %d\n", ret); 434 return ret; 435 } 436 sai->sai_mclk = hw->clk; 437 438 /* register mclk provider */ 439 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 440 } 441 442 static irqreturn_t stm32_sai_isr(int irq, void *devid) 443 { 444 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 445 struct platform_device *pdev = sai->pdev; 446 unsigned int sr, imr, flags; 447 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 448 449 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 450 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 451 452 flags = sr & imr; 453 if (!flags) 454 return IRQ_NONE; 455 456 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 457 SAI_XCLRFR_MASK); 458 459 if (!sai->substream) { 460 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 461 return IRQ_NONE; 462 } 463 464 if (flags & SAI_XIMR_OVRUDRIE) { 465 dev_err(&pdev->dev, "IRQ %s\n", 466 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 467 status = SNDRV_PCM_STATE_XRUN; 468 } 469 470 if (flags & SAI_XIMR_MUTEDETIE) 471 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 472 473 if (flags & SAI_XIMR_WCKCFGIE) { 474 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 475 status = SNDRV_PCM_STATE_DISCONNECTED; 476 } 477 478 if (flags & SAI_XIMR_CNRDYIE) 479 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 480 481 if (flags & SAI_XIMR_AFSDETIE) { 482 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 483 status = SNDRV_PCM_STATE_XRUN; 484 } 485 486 if (flags & SAI_XIMR_LFSDETIE) { 487 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 488 status = SNDRV_PCM_STATE_XRUN; 489 } 490 491 spin_lock(&sai->irq_lock); 492 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 493 snd_pcm_stop_xrun(sai->substream); 494 spin_unlock(&sai->irq_lock); 495 496 return IRQ_HANDLED; 497 } 498 499 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 500 int clk_id, unsigned int freq, int dir) 501 { 502 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 503 int ret; 504 505 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 506 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 507 SAI_XCR1_NODIV, 508 (unsigned int)~SAI_XCR1_NODIV); 509 if (ret < 0) 510 return ret; 511 512 /* If master clock is used, set parent clock now */ 513 ret = stm32_sai_set_parent_clock(sai, freq); 514 if (ret) 515 return ret; 516 517 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 518 if (ret) { 519 dev_err(cpu_dai->dev, 520 ret == -EBUSY ? 521 "Active streams have incompatible rates" : 522 "Could not set mclk rate\n"); 523 return ret; 524 } 525 526 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 527 sai->mclk_rate = freq; 528 } 529 530 return 0; 531 } 532 533 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 534 u32 rx_mask, int slots, int slot_width) 535 { 536 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 537 int slotr, slotr_mask, slot_size; 538 539 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 540 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 541 return 0; 542 } 543 544 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 545 tx_mask, rx_mask, slots, slot_width); 546 547 switch (slot_width) { 548 case 16: 549 slot_size = SAI_SLOT_SIZE_16; 550 break; 551 case 32: 552 slot_size = SAI_SLOT_SIZE_32; 553 break; 554 default: 555 slot_size = SAI_SLOT_SIZE_AUTO; 556 break; 557 } 558 559 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 560 SAI_XSLOTR_NBSLOT_SET(slots - 1); 561 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 562 563 /* tx/rx mask set in machine init, if slot number defined in DT */ 564 if (STM_SAI_IS_PLAYBACK(sai)) { 565 sai->slot_mask = tx_mask; 566 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 567 } 568 569 if (STM_SAI_IS_CAPTURE(sai)) { 570 sai->slot_mask = rx_mask; 571 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 572 } 573 574 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 575 576 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 577 578 sai->slot_width = slot_width; 579 sai->slots = slots; 580 581 return 0; 582 } 583 584 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 585 { 586 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 587 int cr1, frcr = 0; 588 int cr1_mask, frcr_mask = 0; 589 int ret; 590 591 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 592 593 /* Do not generate master by default */ 594 cr1 = SAI_XCR1_NODIV; 595 cr1_mask = SAI_XCR1_NODIV; 596 597 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 598 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 599 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 600 goto conf_update; 601 } 602 603 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 604 605 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 606 /* SCK active high for all protocols */ 607 case SND_SOC_DAIFMT_I2S: 608 cr1 |= SAI_XCR1_CKSTR; 609 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 610 break; 611 /* Left justified */ 612 case SND_SOC_DAIFMT_MSB: 613 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 614 break; 615 /* Right justified */ 616 case SND_SOC_DAIFMT_LSB: 617 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 618 break; 619 case SND_SOC_DAIFMT_DSP_A: 620 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 621 break; 622 case SND_SOC_DAIFMT_DSP_B: 623 frcr |= SAI_XFRCR_FSPOL; 624 break; 625 default: 626 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 627 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 628 return -EINVAL; 629 } 630 631 cr1_mask |= SAI_XCR1_CKSTR; 632 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 633 SAI_XFRCR_FSDEF; 634 635 /* DAI clock strobing. Invert setting previously set */ 636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 637 case SND_SOC_DAIFMT_NB_NF: 638 break; 639 case SND_SOC_DAIFMT_IB_NF: 640 cr1 ^= SAI_XCR1_CKSTR; 641 break; 642 case SND_SOC_DAIFMT_NB_IF: 643 frcr ^= SAI_XFRCR_FSPOL; 644 break; 645 case SND_SOC_DAIFMT_IB_IF: 646 /* Invert fs & sck */ 647 cr1 ^= SAI_XCR1_CKSTR; 648 frcr ^= SAI_XFRCR_FSPOL; 649 break; 650 default: 651 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 652 fmt & SND_SOC_DAIFMT_INV_MASK); 653 return -EINVAL; 654 } 655 cr1_mask |= SAI_XCR1_CKSTR; 656 frcr_mask |= SAI_XFRCR_FSPOL; 657 658 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 659 660 /* DAI clock master masks */ 661 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 662 case SND_SOC_DAIFMT_CBM_CFM: 663 /* codec is master */ 664 cr1 |= SAI_XCR1_SLAVE; 665 sai->master = false; 666 break; 667 case SND_SOC_DAIFMT_CBS_CFS: 668 sai->master = true; 669 break; 670 default: 671 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 672 fmt & SND_SOC_DAIFMT_MASTER_MASK); 673 return -EINVAL; 674 } 675 676 /* Set slave mode if sub-block is synchronized with another SAI */ 677 if (sai->sync) { 678 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 679 cr1 |= SAI_XCR1_SLAVE; 680 sai->master = false; 681 } 682 683 cr1_mask |= SAI_XCR1_SLAVE; 684 685 conf_update: 686 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 687 if (ret < 0) { 688 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 689 return ret; 690 } 691 692 sai->fmt = fmt; 693 694 return 0; 695 } 696 697 static int stm32_sai_startup(struct snd_pcm_substream *substream, 698 struct snd_soc_dai *cpu_dai) 699 { 700 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 701 int imr, cr2, ret; 702 unsigned long flags; 703 704 spin_lock_irqsave(&sai->irq_lock, flags); 705 sai->substream = substream; 706 spin_unlock_irqrestore(&sai->irq_lock, flags); 707 708 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 709 snd_pcm_hw_constraint_mask64(substream->runtime, 710 SNDRV_PCM_HW_PARAM_FORMAT, 711 SNDRV_PCM_FMTBIT_S32_LE); 712 snd_pcm_hw_constraint_single(substream->runtime, 713 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 714 } 715 716 ret = clk_prepare_enable(sai->sai_ck); 717 if (ret < 0) { 718 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 719 return ret; 720 } 721 722 /* Enable ITs */ 723 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, 724 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 725 726 imr = SAI_XIMR_OVRUDRIE; 727 if (STM_SAI_IS_CAPTURE(sai)) { 728 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 729 if (cr2 & SAI_XCR2_MUTECNT_MASK) 730 imr |= SAI_XIMR_MUTEDETIE; 731 } 732 733 if (sai->master) 734 imr |= SAI_XIMR_WCKCFGIE; 735 else 736 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 737 738 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 739 SAI_XIMR_MASK, imr); 740 741 return 0; 742 } 743 744 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 745 struct snd_pcm_substream *substream, 746 struct snd_pcm_hw_params *params) 747 { 748 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 749 int cr1, cr1_mask, ret; 750 751 /* 752 * DMA bursts increment is set to 4 words. 753 * SAI fifo threshold is set to half fifo, to keep enough space 754 * for DMA incoming bursts. 755 */ 756 regmap_write_bits(sai->regmap, STM_SAI_CR2_REGX, 757 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 758 SAI_XCR2_FFLUSH | 759 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 760 761 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 762 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 763 sai->spdif_frm_cnt = 0; 764 return 0; 765 } 766 767 /* Mode, data format and channel config */ 768 cr1_mask = SAI_XCR1_DS_MASK; 769 switch (params_format(params)) { 770 case SNDRV_PCM_FORMAT_S8: 771 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 772 break; 773 case SNDRV_PCM_FORMAT_S16_LE: 774 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 775 break; 776 case SNDRV_PCM_FORMAT_S32_LE: 777 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 778 break; 779 default: 780 dev_err(cpu_dai->dev, "Data format not supported"); 781 return -EINVAL; 782 } 783 784 cr1_mask |= SAI_XCR1_MONO; 785 if ((sai->slots == 2) && (params_channels(params) == 1)) 786 cr1 |= SAI_XCR1_MONO; 787 788 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 789 if (ret < 0) { 790 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 791 return ret; 792 } 793 794 return 0; 795 } 796 797 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 798 { 799 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 800 int slotr, slot_sz; 801 802 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 803 804 /* 805 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 806 * By default slot width = data size, if not forced from DT 807 */ 808 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 809 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 810 sai->slot_width = sai->data_size; 811 812 if (sai->slot_width < sai->data_size) { 813 dev_err(cpu_dai->dev, 814 "Data size %d larger than slot width\n", 815 sai->data_size); 816 return -EINVAL; 817 } 818 819 /* Slot number is set to 2, if not specified in DT */ 820 if (!sai->slots) 821 sai->slots = 2; 822 823 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 824 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 825 SAI_XSLOTR_NBSLOT_MASK, 826 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 827 828 /* Set default slots mask if not already set from DT */ 829 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 830 sai->slot_mask = (1 << sai->slots) - 1; 831 regmap_update_bits(sai->regmap, 832 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 833 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 834 } 835 836 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 837 sai->slots, sai->slot_width); 838 839 return 0; 840 } 841 842 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 843 { 844 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 845 int fs_active, offset, format; 846 int frcr, frcr_mask; 847 848 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 849 sai->fs_length = sai->slot_width * sai->slots; 850 851 fs_active = sai->fs_length / 2; 852 if ((format == SND_SOC_DAIFMT_DSP_A) || 853 (format == SND_SOC_DAIFMT_DSP_B)) 854 fs_active = 1; 855 856 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 857 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 858 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 859 860 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 861 sai->fs_length, fs_active); 862 863 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 864 865 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 866 offset = sai->slot_width - sai->data_size; 867 868 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 869 SAI_XSLOTR_FBOFF_MASK, 870 SAI_XSLOTR_FBOFF_SET(offset)); 871 } 872 } 873 874 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 875 { 876 unsigned char *cs = sai->iec958.status; 877 878 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 879 cs[1] = IEC958_AES1_CON_GENERAL; 880 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 881 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 882 } 883 884 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 885 struct snd_pcm_runtime *runtime) 886 { 887 if (!runtime) 888 return; 889 890 /* Force the sample rate according to runtime rate */ 891 mutex_lock(&sai->ctrl_lock); 892 switch (runtime->rate) { 893 case 22050: 894 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 895 break; 896 case 44100: 897 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 898 break; 899 case 88200: 900 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 901 break; 902 case 176400: 903 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 904 break; 905 case 24000: 906 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 907 break; 908 case 48000: 909 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 910 break; 911 case 96000: 912 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 913 break; 914 case 192000: 915 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 916 break; 917 case 32000: 918 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 919 break; 920 default: 921 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 922 break; 923 } 924 mutex_unlock(&sai->ctrl_lock); 925 } 926 927 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 928 struct snd_pcm_hw_params *params) 929 { 930 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 931 int div = 0, cr1 = 0; 932 int sai_clk_rate, mclk_ratio, den; 933 unsigned int rate = params_rate(params); 934 int ret; 935 936 if (!sai->sai_mclk) { 937 ret = stm32_sai_set_parent_clock(sai, rate); 938 if (ret) 939 return ret; 940 } 941 sai_clk_rate = clk_get_rate(sai->sai_ck); 942 943 if (STM_SAI_IS_F4(sai->pdata)) { 944 /* mclk on (NODIV=0) 945 * mclk_rate = 256 * fs 946 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 947 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 948 * mclk off (NODIV=1) 949 * MCKDIV ignored. sck = sai_ck 950 */ 951 if (!sai->mclk_rate) 952 return 0; 953 954 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 955 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 956 2 * sai->mclk_rate); 957 if (div < 0) 958 return div; 959 } 960 } else { 961 /* 962 * TDM mode : 963 * mclk on 964 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 965 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 966 * mclk off 967 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 968 * Note: NOMCK/NODIV correspond to same bit. 969 */ 970 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 971 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 972 rate * 128); 973 if (div < 0) 974 return div; 975 } else { 976 if (sai->mclk_rate) { 977 mclk_ratio = sai->mclk_rate / rate; 978 if (mclk_ratio == 512) { 979 cr1 = SAI_XCR1_OSR; 980 } else if (mclk_ratio != 256) { 981 dev_err(cpu_dai->dev, 982 "Wrong mclk ratio %d\n", 983 mclk_ratio); 984 return -EINVAL; 985 } 986 987 regmap_update_bits(sai->regmap, 988 STM_SAI_CR1_REGX, 989 SAI_XCR1_OSR, cr1); 990 991 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 992 sai->mclk_rate); 993 if (div < 0) 994 return div; 995 } else { 996 /* mclk-fs not set, master clock not active */ 997 den = sai->fs_length * params_rate(params); 998 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 999 den); 1000 if (div < 0) 1001 return div; 1002 } 1003 } 1004 } 1005 1006 return stm32_sai_set_clk_div(sai, div); 1007 } 1008 1009 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1010 struct snd_pcm_hw_params *params, 1011 struct snd_soc_dai *cpu_dai) 1012 { 1013 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1014 int ret; 1015 1016 sai->data_size = params_width(params); 1017 1018 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1019 /* Rate not already set in runtime structure */ 1020 substream->runtime->rate = params_rate(params); 1021 stm32_sai_set_iec958_status(sai, substream->runtime); 1022 } else { 1023 ret = stm32_sai_set_slots(cpu_dai); 1024 if (ret < 0) 1025 return ret; 1026 stm32_sai_set_frame(cpu_dai); 1027 } 1028 1029 ret = stm32_sai_set_config(cpu_dai, substream, params); 1030 if (ret) 1031 return ret; 1032 1033 if (sai->master) 1034 ret = stm32_sai_configure_clock(cpu_dai, params); 1035 1036 return ret; 1037 } 1038 1039 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1040 struct snd_soc_dai *cpu_dai) 1041 { 1042 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1043 int ret; 1044 1045 switch (cmd) { 1046 case SNDRV_PCM_TRIGGER_START: 1047 case SNDRV_PCM_TRIGGER_RESUME: 1048 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1049 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1050 1051 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1052 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1053 1054 /* Enable SAI */ 1055 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1056 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1057 if (ret < 0) 1058 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1059 break; 1060 case SNDRV_PCM_TRIGGER_SUSPEND: 1061 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1062 case SNDRV_PCM_TRIGGER_STOP: 1063 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1064 1065 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 1066 SAI_XIMR_MASK, 0); 1067 1068 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1069 SAI_XCR1_SAIEN, 1070 (unsigned int)~SAI_XCR1_SAIEN); 1071 1072 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1073 SAI_XCR1_DMAEN, 1074 (unsigned int)~SAI_XCR1_DMAEN); 1075 if (ret < 0) 1076 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1077 1078 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1079 sai->spdif_frm_cnt = 0; 1080 break; 1081 default: 1082 return -EINVAL; 1083 } 1084 1085 return ret; 1086 } 1087 1088 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1089 struct snd_soc_dai *cpu_dai) 1090 { 1091 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1092 unsigned long flags; 1093 1094 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1095 1096 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 1097 SAI_XCR1_NODIV); 1098 1099 /* Release mclk rate only if rate was actually set */ 1100 if (sai->mclk_rate) { 1101 clk_rate_exclusive_put(sai->sai_mclk); 1102 sai->mclk_rate = 0; 1103 } 1104 1105 clk_disable_unprepare(sai->sai_ck); 1106 1107 spin_lock_irqsave(&sai->irq_lock, flags); 1108 sai->substream = NULL; 1109 spin_unlock_irqrestore(&sai->irq_lock, flags); 1110 } 1111 1112 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1113 struct snd_soc_dai *cpu_dai) 1114 { 1115 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1116 struct snd_kcontrol_new knew = iec958_ctls; 1117 1118 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1119 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1120 knew.device = rtd->pcm->device; 1121 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1122 } 1123 1124 return 0; 1125 } 1126 1127 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1128 { 1129 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1130 int cr1 = 0, cr1_mask, ret; 1131 1132 sai->cpu_dai = cpu_dai; 1133 1134 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1135 /* 1136 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1137 * as it allows bytes, half-word and words transfers. (See DMA fifos 1138 * constraints). 1139 */ 1140 sai->dma_params.maxburst = 4; 1141 if (sai->pdata->conf.fifo_size < 8) 1142 sai->dma_params.maxburst = 1; 1143 /* Buswidth will be set by framework at runtime */ 1144 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1145 1146 if (STM_SAI_IS_PLAYBACK(sai)) 1147 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1148 else 1149 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1150 1151 /* Next settings are not relevant for spdif mode */ 1152 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1153 return 0; 1154 1155 cr1_mask = SAI_XCR1_RX_TX; 1156 if (STM_SAI_IS_CAPTURE(sai)) 1157 cr1 |= SAI_XCR1_RX_TX; 1158 1159 /* Configure synchronization */ 1160 if (sai->sync == SAI_SYNC_EXTERNAL) { 1161 /* Configure synchro client and provider */ 1162 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1163 sai->synco, sai->synci); 1164 if (ret) 1165 return ret; 1166 } 1167 1168 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1169 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1170 1171 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 1172 } 1173 1174 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1175 .set_sysclk = stm32_sai_set_sysclk, 1176 .set_fmt = stm32_sai_set_dai_fmt, 1177 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1178 .startup = stm32_sai_startup, 1179 .hw_params = stm32_sai_hw_params, 1180 .trigger = stm32_sai_trigger, 1181 .shutdown = stm32_sai_shutdown, 1182 }; 1183 1184 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1185 int channel, unsigned long hwoff, 1186 void *buf, unsigned long bytes) 1187 { 1188 struct snd_pcm_runtime *runtime = substream->runtime; 1189 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1190 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 1191 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1192 int *ptr = (int *)(runtime->dma_area + hwoff + 1193 channel * (runtime->dma_bytes / runtime->channels)); 1194 ssize_t cnt = bytes_to_samples(runtime, bytes); 1195 unsigned int frm_cnt = sai->spdif_frm_cnt; 1196 unsigned int byte; 1197 unsigned int mask; 1198 1199 do { 1200 *ptr = ((*ptr >> 8) & 0x00ffffff); 1201 1202 /* Set channel status bit */ 1203 byte = frm_cnt >> 3; 1204 mask = 1 << (frm_cnt - (byte << 3)); 1205 if (sai->iec958.status[byte] & mask) 1206 *ptr |= 0x04000000; 1207 ptr++; 1208 1209 if (!(cnt % 2)) 1210 frm_cnt++; 1211 1212 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1213 frm_cnt = 0; 1214 } while (--cnt); 1215 sai->spdif_frm_cnt = frm_cnt; 1216 1217 return 0; 1218 } 1219 1220 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1221 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1222 .buffer_bytes_max = 8 * PAGE_SIZE, 1223 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1224 .period_bytes_max = PAGE_SIZE, 1225 .periods_min = 2, 1226 .periods_max = 8, 1227 }; 1228 1229 static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1230 .probe = stm32_sai_dai_probe, 1231 .pcm_new = stm32_sai_pcm_new, 1232 .id = 1, /* avoid call to fmt_single_name() */ 1233 .playback = { 1234 .channels_min = 1, 1235 .channels_max = 2, 1236 .rate_min = 8000, 1237 .rate_max = 192000, 1238 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1239 /* DMA does not support 24 bits transfers */ 1240 .formats = 1241 SNDRV_PCM_FMTBIT_S8 | 1242 SNDRV_PCM_FMTBIT_S16_LE | 1243 SNDRV_PCM_FMTBIT_S32_LE, 1244 }, 1245 .ops = &stm32_sai_pcm_dai_ops, 1246 }; 1247 1248 static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1249 .probe = stm32_sai_dai_probe, 1250 .id = 1, /* avoid call to fmt_single_name() */ 1251 .capture = { 1252 .channels_min = 1, 1253 .channels_max = 2, 1254 .rate_min = 8000, 1255 .rate_max = 192000, 1256 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1257 /* DMA does not support 24 bits transfers */ 1258 .formats = 1259 SNDRV_PCM_FMTBIT_S8 | 1260 SNDRV_PCM_FMTBIT_S16_LE | 1261 SNDRV_PCM_FMTBIT_S32_LE, 1262 }, 1263 .ops = &stm32_sai_pcm_dai_ops, 1264 }; 1265 1266 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1267 .pcm_hardware = &stm32_sai_pcm_hw, 1268 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1269 }; 1270 1271 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1272 .pcm_hardware = &stm32_sai_pcm_hw, 1273 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1274 .process = stm32_sai_pcm_process_spdif, 1275 }; 1276 1277 static const struct snd_soc_component_driver stm32_component = { 1278 .name = "stm32-sai", 1279 }; 1280 1281 static const struct of_device_id stm32_sai_sub_ids[] = { 1282 { .compatible = "st,stm32-sai-sub-a", 1283 .data = (void *)STM_SAI_A_ID}, 1284 { .compatible = "st,stm32-sai-sub-b", 1285 .data = (void *)STM_SAI_B_ID}, 1286 {} 1287 }; 1288 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1289 1290 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1291 struct stm32_sai_sub_data *sai) 1292 { 1293 struct device_node *np = pdev->dev.of_node; 1294 struct resource *res; 1295 void __iomem *base; 1296 struct of_phandle_args args; 1297 int ret; 1298 1299 if (!np) 1300 return -ENODEV; 1301 1302 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1303 base = devm_ioremap_resource(&pdev->dev, res); 1304 if (IS_ERR(base)) 1305 return PTR_ERR(base); 1306 1307 sai->phys_addr = res->start; 1308 1309 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1310 /* Note: PDM registers not available for sub-block B */ 1311 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 1312 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1313 1314 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 1315 base, sai->regmap_config); 1316 if (IS_ERR(sai->regmap)) { 1317 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 1318 return PTR_ERR(sai->regmap); 1319 } 1320 1321 /* Get direction property */ 1322 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1323 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1324 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1325 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1326 } else { 1327 dev_err(&pdev->dev, "Unsupported direction\n"); 1328 return -EINVAL; 1329 } 1330 1331 /* Get spdif iec60958 property */ 1332 sai->spdif = false; 1333 if (of_get_property(np, "st,iec60958", NULL)) { 1334 if (!STM_SAI_HAS_SPDIF(sai) || 1335 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1336 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1337 return -EINVAL; 1338 } 1339 stm32_sai_init_iec958_status(sai); 1340 sai->spdif = true; 1341 sai->master = true; 1342 } 1343 1344 /* Get synchronization property */ 1345 args.np = NULL; 1346 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1347 if (ret < 0 && ret != -ENOENT) { 1348 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1349 return ret; 1350 } 1351 1352 sai->sync = SAI_SYNC_NONE; 1353 if (args.np) { 1354 if (args.np == np) { 1355 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1356 of_node_put(args.np); 1357 return -EINVAL; 1358 } 1359 1360 sai->np_sync_provider = of_get_parent(args.np); 1361 if (!sai->np_sync_provider) { 1362 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1363 np); 1364 of_node_put(args.np); 1365 return -ENODEV; 1366 } 1367 1368 sai->sync = SAI_SYNC_INTERNAL; 1369 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1370 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1371 dev_err(&pdev->dev, 1372 "External synchro not supported\n"); 1373 of_node_put(args.np); 1374 return -EINVAL; 1375 } 1376 sai->sync = SAI_SYNC_EXTERNAL; 1377 1378 sai->synci = args.args[0]; 1379 if (sai->synci < 1 || 1380 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1381 dev_err(&pdev->dev, "Wrong SAI index\n"); 1382 of_node_put(args.np); 1383 return -EINVAL; 1384 } 1385 1386 if (of_property_match_string(args.np, "compatible", 1387 "st,stm32-sai-sub-a") >= 0) 1388 sai->synco = STM_SAI_SYNC_OUT_A; 1389 1390 if (of_property_match_string(args.np, "compatible", 1391 "st,stm32-sai-sub-b") >= 0) 1392 sai->synco = STM_SAI_SYNC_OUT_B; 1393 1394 if (!sai->synco) { 1395 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1396 of_node_put(args.np); 1397 return -EINVAL; 1398 } 1399 } 1400 1401 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1402 pdev->name, args.np->full_name); 1403 } 1404 1405 of_node_put(args.np); 1406 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1407 if (IS_ERR(sai->sai_ck)) { 1408 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 1409 return PTR_ERR(sai->sai_ck); 1410 } 1411 1412 if (STM_SAI_IS_F4(sai->pdata)) 1413 return 0; 1414 1415 /* Register mclk provider if requested */ 1416 if (of_find_property(np, "#clock-cells", NULL)) { 1417 ret = stm32_sai_add_mclk_provider(sai); 1418 if (ret < 0) 1419 return ret; 1420 } else { 1421 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 1422 if (IS_ERR(sai->sai_mclk)) { 1423 if (PTR_ERR(sai->sai_mclk) != -ENOENT) 1424 return PTR_ERR(sai->sai_mclk); 1425 sai->sai_mclk = NULL; 1426 } 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int stm32_sai_sub_probe(struct platform_device *pdev) 1433 { 1434 struct stm32_sai_sub_data *sai; 1435 const struct of_device_id *of_id; 1436 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1437 int ret; 1438 1439 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1440 if (!sai) 1441 return -ENOMEM; 1442 1443 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1444 if (!of_id) 1445 return -EINVAL; 1446 sai->id = (uintptr_t)of_id->data; 1447 1448 sai->pdev = pdev; 1449 mutex_init(&sai->ctrl_lock); 1450 spin_lock_init(&sai->irq_lock); 1451 platform_set_drvdata(pdev, sai); 1452 1453 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1454 if (!sai->pdata) { 1455 dev_err(&pdev->dev, "Parent device data not available\n"); 1456 return -EINVAL; 1457 } 1458 1459 ret = stm32_sai_sub_parse_of(pdev, sai); 1460 if (ret) 1461 return ret; 1462 1463 if (STM_SAI_IS_PLAYBACK(sai)) 1464 sai->cpu_dai_drv = stm32_sai_playback_dai; 1465 else 1466 sai->cpu_dai_drv = stm32_sai_capture_dai; 1467 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1468 1469 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1470 IRQF_SHARED, dev_name(&pdev->dev), sai); 1471 if (ret) { 1472 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1473 return ret; 1474 } 1475 1476 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1477 &sai->cpu_dai_drv, 1); 1478 if (ret) 1479 return ret; 1480 1481 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1482 conf = &stm32_sai_pcm_config_spdif; 1483 1484 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1485 if (ret) { 1486 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1487 return ret; 1488 } 1489 1490 return 0; 1491 } 1492 1493 #ifdef CONFIG_PM_SLEEP 1494 static int stm32_sai_sub_suspend(struct device *dev) 1495 { 1496 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1497 1498 regcache_cache_only(sai->regmap, true); 1499 regcache_mark_dirty(sai->regmap); 1500 return 0; 1501 } 1502 1503 static int stm32_sai_sub_resume(struct device *dev) 1504 { 1505 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1506 1507 regcache_cache_only(sai->regmap, false); 1508 return regcache_sync(sai->regmap); 1509 } 1510 #endif /* CONFIG_PM_SLEEP */ 1511 1512 static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1513 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1514 }; 1515 1516 static struct platform_driver stm32_sai_sub_driver = { 1517 .driver = { 1518 .name = "st,stm32-sai-sub", 1519 .of_match_table = stm32_sai_sub_ids, 1520 .pm = &stm32_sai_sub_pm_ops, 1521 }, 1522 .probe = stm32_sai_sub_probe, 1523 }; 1524 1525 module_platform_driver(stm32_sai_sub_driver); 1526 1527 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1528 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1529 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1530 MODULE_LICENSE("GPL v2"); 1531