1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clk-provider.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/regmap.h> 26 27 #include <sound/asoundef.h> 28 #include <sound/core.h> 29 #include <sound/dmaengine_pcm.h> 30 #include <sound/pcm_params.h> 31 32 #include "stm32_sai.h" 33 34 #define SAI_FREE_PROTOCOL 0x0 35 #define SAI_SPDIF_PROTOCOL 0x1 36 37 #define SAI_SLOT_SIZE_AUTO 0x0 38 #define SAI_SLOT_SIZE_16 0x1 39 #define SAI_SLOT_SIZE_32 0x2 40 41 #define SAI_DATASIZE_8 0x2 42 #define SAI_DATASIZE_10 0x3 43 #define SAI_DATASIZE_16 0x4 44 #define SAI_DATASIZE_20 0x5 45 #define SAI_DATASIZE_24 0x6 46 #define SAI_DATASIZE_32 0x7 47 48 #define STM_SAI_FIFO_SIZE 8 49 #define STM_SAI_DAI_NAME_SIZE 15 50 51 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 52 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 53 54 #define STM_SAI_A_ID 0x0 55 #define STM_SAI_B_ID 0x1 56 57 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 58 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 59 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 60 61 #define SAI_SYNC_NONE 0x0 62 #define SAI_SYNC_INTERNAL 0x1 63 #define SAI_SYNC_EXTERNAL 0x2 64 65 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 66 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif) 67 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 68 69 #define SAI_IEC60958_BLOCK_FRAMES 192 70 #define SAI_IEC60958_STATUS_BYTES 24 71 72 #define SAI_MCLK_NAME_LEN 32 73 #define SAI_RATE_11K 11025 74 75 /** 76 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 77 * @pdev: device data pointer 78 * @regmap: SAI register map pointer 79 * @regmap_config: SAI sub block register map configuration pointer 80 * @dma_params: dma configuration data for rx or tx channel 81 * @cpu_dai_drv: DAI driver data pointer 82 * @cpu_dai: DAI runtime data pointer 83 * @substream: PCM substream data pointer 84 * @pdata: SAI block parent data pointer 85 * @np_sync_provider: synchronization provider node 86 * @sai_ck: kernel clock feeding the SAI clock generator 87 * @sai_mclk: master clock from SAI mclk provider 88 * @phys_addr: SAI registers physical base address 89 * @mclk_rate: SAI block master clock frequency (Hz). set at init 90 * @id: SAI sub block id corresponding to sub-block A or B 91 * @dir: SAI block direction (playback or capture). set at init 92 * @master: SAI block mode flag. (true=master, false=slave) set at init 93 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 94 * @fmt: SAI block format. relevant only for custom protocols. set at init 95 * @sync: SAI block synchronization mode. (none, internal or external) 96 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 97 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 98 * @fs_length: frame synchronization length. depends on protocol settings 99 * @slots: rx or tx slot number 100 * @slot_width: rx or tx slot width in bits 101 * @slot_mask: rx or tx active slots mask. set at init or at runtime 102 * @data_size: PCM data width. corresponds to PCM substream width. 103 * @spdif_frm_cnt: S/PDIF playback frame counter 104 * @iec958: iec958 data 105 * @ctrl_lock: control lock 106 * @irq_lock: prevent race condition with IRQ 107 */ 108 struct stm32_sai_sub_data { 109 struct platform_device *pdev; 110 struct regmap *regmap; 111 const struct regmap_config *regmap_config; 112 struct snd_dmaengine_dai_dma_data dma_params; 113 struct snd_soc_dai_driver cpu_dai_drv; 114 struct snd_soc_dai *cpu_dai; 115 struct snd_pcm_substream *substream; 116 struct stm32_sai_data *pdata; 117 struct device_node *np_sync_provider; 118 struct clk *sai_ck; 119 struct clk *sai_mclk; 120 dma_addr_t phys_addr; 121 unsigned int mclk_rate; 122 unsigned int id; 123 int dir; 124 bool master; 125 bool spdif; 126 int fmt; 127 int sync; 128 int synco; 129 int synci; 130 int fs_length; 131 int slots; 132 int slot_width; 133 int slot_mask; 134 int data_size; 135 unsigned int spdif_frm_cnt; 136 struct snd_aes_iec958 iec958; 137 struct mutex ctrl_lock; /* protect resources accessed by controls */ 138 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 139 }; 140 141 enum stm32_sai_fifo_th { 142 STM_SAI_FIFO_TH_EMPTY, 143 STM_SAI_FIFO_TH_QUARTER, 144 STM_SAI_FIFO_TH_HALF, 145 STM_SAI_FIFO_TH_3_QUARTER, 146 STM_SAI_FIFO_TH_FULL, 147 }; 148 149 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 150 { 151 switch (reg) { 152 case STM_SAI_CR1_REGX: 153 case STM_SAI_CR2_REGX: 154 case STM_SAI_FRCR_REGX: 155 case STM_SAI_SLOTR_REGX: 156 case STM_SAI_IMR_REGX: 157 case STM_SAI_SR_REGX: 158 case STM_SAI_CLRFR_REGX: 159 case STM_SAI_DR_REGX: 160 case STM_SAI_PDMCR_REGX: 161 case STM_SAI_PDMLY_REGX: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 169 { 170 switch (reg) { 171 case STM_SAI_DR_REGX: 172 case STM_SAI_SR_REGX: 173 return true; 174 default: 175 return false; 176 } 177 } 178 179 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 180 { 181 switch (reg) { 182 case STM_SAI_CR1_REGX: 183 case STM_SAI_CR2_REGX: 184 case STM_SAI_FRCR_REGX: 185 case STM_SAI_SLOTR_REGX: 186 case STM_SAI_IMR_REGX: 187 case STM_SAI_CLRFR_REGX: 188 case STM_SAI_DR_REGX: 189 case STM_SAI_PDMCR_REGX: 190 case STM_SAI_PDMLY_REGX: 191 return true; 192 default: 193 return false; 194 } 195 } 196 197 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 198 .reg_bits = 32, 199 .reg_stride = 4, 200 .val_bits = 32, 201 .max_register = STM_SAI_DR_REGX, 202 .readable_reg = stm32_sai_sub_readable_reg, 203 .volatile_reg = stm32_sai_sub_volatile_reg, 204 .writeable_reg = stm32_sai_sub_writeable_reg, 205 .fast_io = true, 206 .cache_type = REGCACHE_FLAT, 207 }; 208 209 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 210 .reg_bits = 32, 211 .reg_stride = 4, 212 .val_bits = 32, 213 .max_register = STM_SAI_PDMLY_REGX, 214 .readable_reg = stm32_sai_sub_readable_reg, 215 .volatile_reg = stm32_sai_sub_volatile_reg, 216 .writeable_reg = stm32_sai_sub_writeable_reg, 217 .fast_io = true, 218 .cache_type = REGCACHE_FLAT, 219 }; 220 221 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 222 struct snd_ctl_elem_info *uinfo) 223 { 224 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 225 uinfo->count = 1; 226 227 return 0; 228 } 229 230 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 231 struct snd_ctl_elem_value *uctl) 232 { 233 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 234 235 mutex_lock(&sai->ctrl_lock); 236 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 237 mutex_unlock(&sai->ctrl_lock); 238 239 return 0; 240 } 241 242 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 243 struct snd_ctl_elem_value *uctl) 244 { 245 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 246 247 mutex_lock(&sai->ctrl_lock); 248 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 249 mutex_unlock(&sai->ctrl_lock); 250 251 return 0; 252 } 253 254 static const struct snd_kcontrol_new iec958_ctls = { 255 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 256 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 257 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 258 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 259 .info = snd_pcm_iec958_info, 260 .get = snd_pcm_iec958_get, 261 .put = snd_pcm_iec958_put, 262 }; 263 264 struct stm32_sai_mclk_data { 265 struct clk_hw hw; 266 unsigned long freq; 267 struct stm32_sai_sub_data *sai_data; 268 }; 269 270 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 271 #define STM32_SAI_MAX_CLKS 1 272 273 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 274 unsigned long input_rate, 275 unsigned long output_rate) 276 { 277 int version = sai->pdata->conf->version; 278 int div; 279 280 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 281 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 282 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 283 return -EINVAL; 284 } 285 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 286 287 if (input_rate % div) 288 dev_dbg(&sai->pdev->dev, 289 "Rate not accurate. requested (%ld), actual (%ld)\n", 290 output_rate, input_rate / div); 291 292 return div; 293 } 294 295 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 296 unsigned int div) 297 { 298 int version = sai->pdata->conf->version; 299 int ret, cr1, mask; 300 301 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 302 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 303 return -EINVAL; 304 } 305 306 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 307 cr1 = SAI_XCR1_MCKDIV_SET(div); 308 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 309 if (ret < 0) 310 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 311 312 return ret; 313 } 314 315 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, 316 unsigned int rate) 317 { 318 struct platform_device *pdev = sai->pdev; 319 struct clk *parent_clk = sai->pdata->clk_x8k; 320 int ret; 321 322 if (!(rate % SAI_RATE_11K)) 323 parent_clk = sai->pdata->clk_x11k; 324 325 ret = clk_set_parent(sai->sai_ck, parent_clk); 326 if (ret) 327 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 328 ret, ret == -EBUSY ? 329 "Active stream rates conflict\n" : "\n"); 330 331 return ret; 332 } 333 334 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 335 unsigned long *prate) 336 { 337 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 338 struct stm32_sai_sub_data *sai = mclk->sai_data; 339 int div; 340 341 div = stm32_sai_get_clk_div(sai, *prate, rate); 342 if (div < 0) 343 return div; 344 345 mclk->freq = *prate / div; 346 347 return mclk->freq; 348 } 349 350 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 351 unsigned long parent_rate) 352 { 353 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 354 355 return mclk->freq; 356 } 357 358 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 359 unsigned long parent_rate) 360 { 361 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 362 struct stm32_sai_sub_data *sai = mclk->sai_data; 363 int div, ret; 364 365 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 366 if (div < 0) 367 return div; 368 369 ret = stm32_sai_set_clk_div(sai, div); 370 if (ret) 371 return ret; 372 373 mclk->freq = rate; 374 375 return 0; 376 } 377 378 static int stm32_sai_mclk_enable(struct clk_hw *hw) 379 { 380 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 381 struct stm32_sai_sub_data *sai = mclk->sai_data; 382 383 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 384 385 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 386 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 387 } 388 389 static void stm32_sai_mclk_disable(struct clk_hw *hw) 390 { 391 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 392 struct stm32_sai_sub_data *sai = mclk->sai_data; 393 394 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 395 396 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 397 } 398 399 static const struct clk_ops mclk_ops = { 400 .enable = stm32_sai_mclk_enable, 401 .disable = stm32_sai_mclk_disable, 402 .recalc_rate = stm32_sai_mclk_recalc_rate, 403 .round_rate = stm32_sai_mclk_round_rate, 404 .set_rate = stm32_sai_mclk_set_rate, 405 }; 406 407 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 408 { 409 struct clk_hw *hw; 410 struct stm32_sai_mclk_data *mclk; 411 struct device *dev = &sai->pdev->dev; 412 const char *pname = __clk_get_name(sai->sai_ck); 413 char *mclk_name, *p, *s = (char *)pname; 414 int ret, i = 0; 415 416 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 417 if (!mclk) 418 return -ENOMEM; 419 420 mclk_name = devm_kcalloc(dev, sizeof(char), 421 SAI_MCLK_NAME_LEN, GFP_KERNEL); 422 if (!mclk_name) 423 return -ENOMEM; 424 425 /* 426 * Forge mclk clock name from parent clock name and suffix. 427 * String after "_" char is stripped in parent name. 428 */ 429 p = mclk_name; 430 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 431 *p++ = *s++; 432 i++; 433 } 434 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 435 436 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 437 mclk->sai_data = sai; 438 hw = &mclk->hw; 439 440 dev_dbg(dev, "Register master clock %s\n", mclk_name); 441 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 442 if (ret) { 443 dev_err(dev, "mclk register returned %d\n", ret); 444 return ret; 445 } 446 sai->sai_mclk = hw->clk; 447 448 /* register mclk provider */ 449 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 450 } 451 452 static irqreturn_t stm32_sai_isr(int irq, void *devid) 453 { 454 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 455 struct platform_device *pdev = sai->pdev; 456 unsigned int sr, imr, flags; 457 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 458 459 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 460 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 461 462 flags = sr & imr; 463 if (!flags) 464 return IRQ_NONE; 465 466 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 467 SAI_XCLRFR_MASK); 468 469 if (!sai->substream) { 470 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 471 return IRQ_NONE; 472 } 473 474 if (flags & SAI_XIMR_OVRUDRIE) { 475 dev_err(&pdev->dev, "IRQ %s\n", 476 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 477 status = SNDRV_PCM_STATE_XRUN; 478 } 479 480 if (flags & SAI_XIMR_MUTEDETIE) 481 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 482 483 if (flags & SAI_XIMR_WCKCFGIE) { 484 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 485 status = SNDRV_PCM_STATE_DISCONNECTED; 486 } 487 488 if (flags & SAI_XIMR_CNRDYIE) 489 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 490 491 if (flags & SAI_XIMR_AFSDETIE) { 492 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 493 status = SNDRV_PCM_STATE_XRUN; 494 } 495 496 if (flags & SAI_XIMR_LFSDETIE) { 497 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 498 status = SNDRV_PCM_STATE_XRUN; 499 } 500 501 spin_lock(&sai->irq_lock); 502 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 503 snd_pcm_stop_xrun(sai->substream); 504 spin_unlock(&sai->irq_lock); 505 506 return IRQ_HANDLED; 507 } 508 509 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 510 int clk_id, unsigned int freq, int dir) 511 { 512 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 513 int ret; 514 515 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 516 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 517 SAI_XCR1_NODIV, 518 (unsigned int)~SAI_XCR1_NODIV); 519 if (ret < 0) 520 return ret; 521 522 /* If master clock is used, set parent clock now */ 523 ret = stm32_sai_set_parent_clock(sai, freq); 524 if (ret) 525 return ret; 526 527 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 528 if (ret) { 529 dev_err(cpu_dai->dev, 530 ret == -EBUSY ? 531 "Active streams have incompatible rates" : 532 "Could not set mclk rate\n"); 533 return ret; 534 } 535 536 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 537 sai->mclk_rate = freq; 538 } 539 540 return 0; 541 } 542 543 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 544 u32 rx_mask, int slots, int slot_width) 545 { 546 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 547 int slotr, slotr_mask, slot_size; 548 549 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 550 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 551 return 0; 552 } 553 554 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 555 tx_mask, rx_mask, slots, slot_width); 556 557 switch (slot_width) { 558 case 16: 559 slot_size = SAI_SLOT_SIZE_16; 560 break; 561 case 32: 562 slot_size = SAI_SLOT_SIZE_32; 563 break; 564 default: 565 slot_size = SAI_SLOT_SIZE_AUTO; 566 break; 567 } 568 569 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 570 SAI_XSLOTR_NBSLOT_SET(slots - 1); 571 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 572 573 /* tx/rx mask set in machine init, if slot number defined in DT */ 574 if (STM_SAI_IS_PLAYBACK(sai)) { 575 sai->slot_mask = tx_mask; 576 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 577 } 578 579 if (STM_SAI_IS_CAPTURE(sai)) { 580 sai->slot_mask = rx_mask; 581 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 582 } 583 584 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 585 586 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 587 588 sai->slot_width = slot_width; 589 sai->slots = slots; 590 591 return 0; 592 } 593 594 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 595 { 596 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 597 int cr1, frcr = 0; 598 int cr1_mask, frcr_mask = 0; 599 int ret; 600 601 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 602 603 /* Do not generate master by default */ 604 cr1 = SAI_XCR1_NODIV; 605 cr1_mask = SAI_XCR1_NODIV; 606 607 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 608 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 609 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 610 goto conf_update; 611 } 612 613 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 614 615 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 616 /* SCK active high for all protocols */ 617 case SND_SOC_DAIFMT_I2S: 618 cr1 |= SAI_XCR1_CKSTR; 619 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 620 break; 621 /* Left justified */ 622 case SND_SOC_DAIFMT_MSB: 623 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 624 break; 625 /* Right justified */ 626 case SND_SOC_DAIFMT_LSB: 627 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 628 break; 629 case SND_SOC_DAIFMT_DSP_A: 630 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 631 break; 632 case SND_SOC_DAIFMT_DSP_B: 633 frcr |= SAI_XFRCR_FSPOL; 634 break; 635 default: 636 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 637 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 638 return -EINVAL; 639 } 640 641 cr1_mask |= SAI_XCR1_CKSTR; 642 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 643 SAI_XFRCR_FSDEF; 644 645 /* DAI clock strobing. Invert setting previously set */ 646 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 647 case SND_SOC_DAIFMT_NB_NF: 648 break; 649 case SND_SOC_DAIFMT_IB_NF: 650 cr1 ^= SAI_XCR1_CKSTR; 651 break; 652 case SND_SOC_DAIFMT_NB_IF: 653 frcr ^= SAI_XFRCR_FSPOL; 654 break; 655 case SND_SOC_DAIFMT_IB_IF: 656 /* Invert fs & sck */ 657 cr1 ^= SAI_XCR1_CKSTR; 658 frcr ^= SAI_XFRCR_FSPOL; 659 break; 660 default: 661 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 662 fmt & SND_SOC_DAIFMT_INV_MASK); 663 return -EINVAL; 664 } 665 cr1_mask |= SAI_XCR1_CKSTR; 666 frcr_mask |= SAI_XFRCR_FSPOL; 667 668 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 669 670 /* DAI clock master masks */ 671 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 672 case SND_SOC_DAIFMT_CBM_CFM: 673 /* codec is master */ 674 cr1 |= SAI_XCR1_SLAVE; 675 sai->master = false; 676 break; 677 case SND_SOC_DAIFMT_CBS_CFS: 678 sai->master = true; 679 break; 680 default: 681 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 682 fmt & SND_SOC_DAIFMT_MASTER_MASK); 683 return -EINVAL; 684 } 685 686 /* Set slave mode if sub-block is synchronized with another SAI */ 687 if (sai->sync) { 688 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 689 cr1 |= SAI_XCR1_SLAVE; 690 sai->master = false; 691 } 692 693 cr1_mask |= SAI_XCR1_SLAVE; 694 695 conf_update: 696 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 697 if (ret < 0) { 698 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 699 return ret; 700 } 701 702 sai->fmt = fmt; 703 704 return 0; 705 } 706 707 static int stm32_sai_startup(struct snd_pcm_substream *substream, 708 struct snd_soc_dai *cpu_dai) 709 { 710 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 711 int imr, cr2, ret; 712 unsigned long flags; 713 714 spin_lock_irqsave(&sai->irq_lock, flags); 715 sai->substream = substream; 716 spin_unlock_irqrestore(&sai->irq_lock, flags); 717 718 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 719 snd_pcm_hw_constraint_mask64(substream->runtime, 720 SNDRV_PCM_HW_PARAM_FORMAT, 721 SNDRV_PCM_FMTBIT_S32_LE); 722 snd_pcm_hw_constraint_single(substream->runtime, 723 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 724 } 725 726 ret = clk_prepare_enable(sai->sai_ck); 727 if (ret < 0) { 728 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 729 return ret; 730 } 731 732 /* Enable ITs */ 733 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, 734 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 735 736 imr = SAI_XIMR_OVRUDRIE; 737 if (STM_SAI_IS_CAPTURE(sai)) { 738 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 739 if (cr2 & SAI_XCR2_MUTECNT_MASK) 740 imr |= SAI_XIMR_MUTEDETIE; 741 } 742 743 if (sai->master) 744 imr |= SAI_XIMR_WCKCFGIE; 745 else 746 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 747 748 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 749 SAI_XIMR_MASK, imr); 750 751 return 0; 752 } 753 754 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 755 struct snd_pcm_substream *substream, 756 struct snd_pcm_hw_params *params) 757 { 758 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 759 int cr1, cr1_mask, ret; 760 761 /* 762 * DMA bursts increment is set to 4 words. 763 * SAI fifo threshold is set to half fifo, to keep enough space 764 * for DMA incoming bursts. 765 */ 766 regmap_write_bits(sai->regmap, STM_SAI_CR2_REGX, 767 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 768 SAI_XCR2_FFLUSH | 769 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 770 771 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 772 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 773 sai->spdif_frm_cnt = 0; 774 return 0; 775 } 776 777 /* Mode, data format and channel config */ 778 cr1_mask = SAI_XCR1_DS_MASK; 779 switch (params_format(params)) { 780 case SNDRV_PCM_FORMAT_S8: 781 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 782 break; 783 case SNDRV_PCM_FORMAT_S16_LE: 784 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 785 break; 786 case SNDRV_PCM_FORMAT_S32_LE: 787 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 788 break; 789 default: 790 dev_err(cpu_dai->dev, "Data format not supported"); 791 return -EINVAL; 792 } 793 794 cr1_mask |= SAI_XCR1_MONO; 795 if ((sai->slots == 2) && (params_channels(params) == 1)) 796 cr1 |= SAI_XCR1_MONO; 797 798 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 799 if (ret < 0) { 800 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 801 return ret; 802 } 803 804 return 0; 805 } 806 807 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 808 { 809 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 810 int slotr, slot_sz; 811 812 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 813 814 /* 815 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 816 * By default slot width = data size, if not forced from DT 817 */ 818 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 819 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 820 sai->slot_width = sai->data_size; 821 822 if (sai->slot_width < sai->data_size) { 823 dev_err(cpu_dai->dev, 824 "Data size %d larger than slot width\n", 825 sai->data_size); 826 return -EINVAL; 827 } 828 829 /* Slot number is set to 2, if not specified in DT */ 830 if (!sai->slots) 831 sai->slots = 2; 832 833 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 834 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 835 SAI_XSLOTR_NBSLOT_MASK, 836 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 837 838 /* Set default slots mask if not already set from DT */ 839 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 840 sai->slot_mask = (1 << sai->slots) - 1; 841 regmap_update_bits(sai->regmap, 842 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 843 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 844 } 845 846 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 847 sai->slots, sai->slot_width); 848 849 return 0; 850 } 851 852 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 853 { 854 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 855 int fs_active, offset, format; 856 int frcr, frcr_mask; 857 858 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 859 sai->fs_length = sai->slot_width * sai->slots; 860 861 fs_active = sai->fs_length / 2; 862 if ((format == SND_SOC_DAIFMT_DSP_A) || 863 (format == SND_SOC_DAIFMT_DSP_B)) 864 fs_active = 1; 865 866 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 867 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 868 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 869 870 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 871 sai->fs_length, fs_active); 872 873 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 874 875 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 876 offset = sai->slot_width - sai->data_size; 877 878 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 879 SAI_XSLOTR_FBOFF_MASK, 880 SAI_XSLOTR_FBOFF_SET(offset)); 881 } 882 } 883 884 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 885 { 886 unsigned char *cs = sai->iec958.status; 887 888 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 889 cs[1] = IEC958_AES1_CON_GENERAL; 890 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 891 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 892 } 893 894 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 895 struct snd_pcm_runtime *runtime) 896 { 897 if (!runtime) 898 return; 899 900 /* Force the sample rate according to runtime rate */ 901 mutex_lock(&sai->ctrl_lock); 902 switch (runtime->rate) { 903 case 22050: 904 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 905 break; 906 case 44100: 907 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 908 break; 909 case 88200: 910 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 911 break; 912 case 176400: 913 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 914 break; 915 case 24000: 916 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 917 break; 918 case 48000: 919 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 920 break; 921 case 96000: 922 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 923 break; 924 case 192000: 925 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 926 break; 927 case 32000: 928 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 929 break; 930 default: 931 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 932 break; 933 } 934 mutex_unlock(&sai->ctrl_lock); 935 } 936 937 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 938 struct snd_pcm_hw_params *params) 939 { 940 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 941 int div = 0, cr1 = 0; 942 int sai_clk_rate, mclk_ratio, den; 943 unsigned int rate = params_rate(params); 944 int ret; 945 946 if (!sai->sai_mclk) { 947 ret = stm32_sai_set_parent_clock(sai, rate); 948 if (ret) 949 return ret; 950 } 951 sai_clk_rate = clk_get_rate(sai->sai_ck); 952 953 if (STM_SAI_IS_F4(sai->pdata)) { 954 /* mclk on (NODIV=0) 955 * mclk_rate = 256 * fs 956 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 957 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 958 * mclk off (NODIV=1) 959 * MCKDIV ignored. sck = sai_ck 960 */ 961 if (!sai->mclk_rate) 962 return 0; 963 964 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 965 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 966 2 * sai->mclk_rate); 967 if (div < 0) 968 return div; 969 } 970 } else { 971 /* 972 * TDM mode : 973 * mclk on 974 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 975 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 976 * mclk off 977 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 978 * Note: NOMCK/NODIV correspond to same bit. 979 */ 980 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 981 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 982 rate * 128); 983 if (div < 0) 984 return div; 985 } else { 986 if (sai->mclk_rate) { 987 mclk_ratio = sai->mclk_rate / rate; 988 if (mclk_ratio == 512) { 989 cr1 = SAI_XCR1_OSR; 990 } else if (mclk_ratio != 256) { 991 dev_err(cpu_dai->dev, 992 "Wrong mclk ratio %d\n", 993 mclk_ratio); 994 return -EINVAL; 995 } 996 997 regmap_update_bits(sai->regmap, 998 STM_SAI_CR1_REGX, 999 SAI_XCR1_OSR, cr1); 1000 1001 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1002 sai->mclk_rate); 1003 if (div < 0) 1004 return div; 1005 } else { 1006 /* mclk-fs not set, master clock not active */ 1007 den = sai->fs_length * params_rate(params); 1008 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1009 den); 1010 if (div < 0) 1011 return div; 1012 } 1013 } 1014 } 1015 1016 return stm32_sai_set_clk_div(sai, div); 1017 } 1018 1019 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1020 struct snd_pcm_hw_params *params, 1021 struct snd_soc_dai *cpu_dai) 1022 { 1023 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1024 int ret; 1025 1026 sai->data_size = params_width(params); 1027 1028 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1029 /* Rate not already set in runtime structure */ 1030 substream->runtime->rate = params_rate(params); 1031 stm32_sai_set_iec958_status(sai, substream->runtime); 1032 } else { 1033 ret = stm32_sai_set_slots(cpu_dai); 1034 if (ret < 0) 1035 return ret; 1036 stm32_sai_set_frame(cpu_dai); 1037 } 1038 1039 ret = stm32_sai_set_config(cpu_dai, substream, params); 1040 if (ret) 1041 return ret; 1042 1043 if (sai->master) 1044 ret = stm32_sai_configure_clock(cpu_dai, params); 1045 1046 return ret; 1047 } 1048 1049 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1050 struct snd_soc_dai *cpu_dai) 1051 { 1052 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1053 int ret; 1054 1055 switch (cmd) { 1056 case SNDRV_PCM_TRIGGER_START: 1057 case SNDRV_PCM_TRIGGER_RESUME: 1058 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1059 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1060 1061 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1062 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1063 1064 /* Enable SAI */ 1065 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1066 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1067 if (ret < 0) 1068 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1069 break; 1070 case SNDRV_PCM_TRIGGER_SUSPEND: 1071 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1072 case SNDRV_PCM_TRIGGER_STOP: 1073 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1074 1075 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 1076 SAI_XIMR_MASK, 0); 1077 1078 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1079 SAI_XCR1_SAIEN, 1080 (unsigned int)~SAI_XCR1_SAIEN); 1081 1082 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1083 SAI_XCR1_DMAEN, 1084 (unsigned int)~SAI_XCR1_DMAEN); 1085 if (ret < 0) 1086 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1087 1088 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1089 sai->spdif_frm_cnt = 0; 1090 break; 1091 default: 1092 return -EINVAL; 1093 } 1094 1095 return ret; 1096 } 1097 1098 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1099 struct snd_soc_dai *cpu_dai) 1100 { 1101 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1102 unsigned long flags; 1103 1104 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1105 1106 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 1107 SAI_XCR1_NODIV); 1108 1109 /* Release mclk rate only if rate was actually set */ 1110 if (sai->mclk_rate) { 1111 clk_rate_exclusive_put(sai->sai_mclk); 1112 sai->mclk_rate = 0; 1113 } 1114 1115 clk_disable_unprepare(sai->sai_ck); 1116 1117 spin_lock_irqsave(&sai->irq_lock, flags); 1118 sai->substream = NULL; 1119 spin_unlock_irqrestore(&sai->irq_lock, flags); 1120 } 1121 1122 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1123 struct snd_soc_dai *cpu_dai) 1124 { 1125 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1126 struct snd_kcontrol_new knew = iec958_ctls; 1127 1128 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1129 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1130 knew.device = rtd->pcm->device; 1131 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1138 { 1139 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1140 int cr1 = 0, cr1_mask, ret; 1141 1142 sai->cpu_dai = cpu_dai; 1143 1144 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1145 /* 1146 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1147 * as it allows bytes, half-word and words transfers. (See DMA fifos 1148 * constraints). 1149 */ 1150 sai->dma_params.maxburst = 4; 1151 /* Buswidth will be set by framework at runtime */ 1152 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1153 1154 if (STM_SAI_IS_PLAYBACK(sai)) 1155 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1156 else 1157 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1158 1159 /* Next settings are not relevant for spdif mode */ 1160 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1161 return 0; 1162 1163 cr1_mask = SAI_XCR1_RX_TX; 1164 if (STM_SAI_IS_CAPTURE(sai)) 1165 cr1 |= SAI_XCR1_RX_TX; 1166 1167 /* Configure synchronization */ 1168 if (sai->sync == SAI_SYNC_EXTERNAL) { 1169 /* Configure synchro client and provider */ 1170 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1171 sai->synco, sai->synci); 1172 if (ret) 1173 return ret; 1174 } 1175 1176 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1177 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1178 1179 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 1180 } 1181 1182 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1183 .set_sysclk = stm32_sai_set_sysclk, 1184 .set_fmt = stm32_sai_set_dai_fmt, 1185 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1186 .startup = stm32_sai_startup, 1187 .hw_params = stm32_sai_hw_params, 1188 .trigger = stm32_sai_trigger, 1189 .shutdown = stm32_sai_shutdown, 1190 }; 1191 1192 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1193 int channel, unsigned long hwoff, 1194 void *buf, unsigned long bytes) 1195 { 1196 struct snd_pcm_runtime *runtime = substream->runtime; 1197 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1198 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 1199 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1200 int *ptr = (int *)(runtime->dma_area + hwoff + 1201 channel * (runtime->dma_bytes / runtime->channels)); 1202 ssize_t cnt = bytes_to_samples(runtime, bytes); 1203 unsigned int frm_cnt = sai->spdif_frm_cnt; 1204 unsigned int byte; 1205 unsigned int mask; 1206 1207 do { 1208 *ptr = ((*ptr >> 8) & 0x00ffffff); 1209 1210 /* Set channel status bit */ 1211 byte = frm_cnt >> 3; 1212 mask = 1 << (frm_cnt - (byte << 3)); 1213 if (sai->iec958.status[byte] & mask) 1214 *ptr |= 0x04000000; 1215 ptr++; 1216 1217 if (!(cnt % 2)) 1218 frm_cnt++; 1219 1220 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1221 frm_cnt = 0; 1222 } while (--cnt); 1223 sai->spdif_frm_cnt = frm_cnt; 1224 1225 return 0; 1226 } 1227 1228 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1229 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1230 .buffer_bytes_max = 8 * PAGE_SIZE, 1231 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1232 .period_bytes_max = PAGE_SIZE, 1233 .periods_min = 2, 1234 .periods_max = 8, 1235 }; 1236 1237 static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1238 .probe = stm32_sai_dai_probe, 1239 .pcm_new = stm32_sai_pcm_new, 1240 .id = 1, /* avoid call to fmt_single_name() */ 1241 .playback = { 1242 .channels_min = 1, 1243 .channels_max = 2, 1244 .rate_min = 8000, 1245 .rate_max = 192000, 1246 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1247 /* DMA does not support 24 bits transfers */ 1248 .formats = 1249 SNDRV_PCM_FMTBIT_S8 | 1250 SNDRV_PCM_FMTBIT_S16_LE | 1251 SNDRV_PCM_FMTBIT_S32_LE, 1252 }, 1253 .ops = &stm32_sai_pcm_dai_ops, 1254 }; 1255 1256 static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1257 .probe = stm32_sai_dai_probe, 1258 .id = 1, /* avoid call to fmt_single_name() */ 1259 .capture = { 1260 .channels_min = 1, 1261 .channels_max = 2, 1262 .rate_min = 8000, 1263 .rate_max = 192000, 1264 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1265 /* DMA does not support 24 bits transfers */ 1266 .formats = 1267 SNDRV_PCM_FMTBIT_S8 | 1268 SNDRV_PCM_FMTBIT_S16_LE | 1269 SNDRV_PCM_FMTBIT_S32_LE, 1270 }, 1271 .ops = &stm32_sai_pcm_dai_ops, 1272 }; 1273 1274 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1275 .pcm_hardware = &stm32_sai_pcm_hw, 1276 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1277 }; 1278 1279 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1280 .pcm_hardware = &stm32_sai_pcm_hw, 1281 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1282 .process = stm32_sai_pcm_process_spdif, 1283 }; 1284 1285 static const struct snd_soc_component_driver stm32_component = { 1286 .name = "stm32-sai", 1287 }; 1288 1289 static const struct of_device_id stm32_sai_sub_ids[] = { 1290 { .compatible = "st,stm32-sai-sub-a", 1291 .data = (void *)STM_SAI_A_ID}, 1292 { .compatible = "st,stm32-sai-sub-b", 1293 .data = (void *)STM_SAI_B_ID}, 1294 {} 1295 }; 1296 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1297 1298 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1299 struct stm32_sai_sub_data *sai) 1300 { 1301 struct device_node *np = pdev->dev.of_node; 1302 struct resource *res; 1303 void __iomem *base; 1304 struct of_phandle_args args; 1305 int ret; 1306 1307 if (!np) 1308 return -ENODEV; 1309 1310 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1311 base = devm_ioremap_resource(&pdev->dev, res); 1312 if (IS_ERR(base)) 1313 return PTR_ERR(base); 1314 1315 sai->phys_addr = res->start; 1316 1317 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1318 /* Note: PDM registers not available for H7 sub-block B */ 1319 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 1320 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1321 1322 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 1323 base, sai->regmap_config); 1324 if (IS_ERR(sai->regmap)) { 1325 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 1326 return PTR_ERR(sai->regmap); 1327 } 1328 1329 /* Get direction property */ 1330 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1331 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1332 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1333 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1334 } else { 1335 dev_err(&pdev->dev, "Unsupported direction\n"); 1336 return -EINVAL; 1337 } 1338 1339 /* Get spdif iec60958 property */ 1340 sai->spdif = false; 1341 if (of_get_property(np, "st,iec60958", NULL)) { 1342 if (!STM_SAI_HAS_SPDIF(sai) || 1343 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1344 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1345 return -EINVAL; 1346 } 1347 stm32_sai_init_iec958_status(sai); 1348 sai->spdif = true; 1349 sai->master = true; 1350 } 1351 1352 /* Get synchronization property */ 1353 args.np = NULL; 1354 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1355 if (ret < 0 && ret != -ENOENT) { 1356 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1357 return ret; 1358 } 1359 1360 sai->sync = SAI_SYNC_NONE; 1361 if (args.np) { 1362 if (args.np == np) { 1363 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1364 of_node_put(args.np); 1365 return -EINVAL; 1366 } 1367 1368 sai->np_sync_provider = of_get_parent(args.np); 1369 if (!sai->np_sync_provider) { 1370 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1371 np); 1372 of_node_put(args.np); 1373 return -ENODEV; 1374 } 1375 1376 sai->sync = SAI_SYNC_INTERNAL; 1377 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1378 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1379 dev_err(&pdev->dev, 1380 "External synchro not supported\n"); 1381 of_node_put(args.np); 1382 return -EINVAL; 1383 } 1384 sai->sync = SAI_SYNC_EXTERNAL; 1385 1386 sai->synci = args.args[0]; 1387 if (sai->synci < 1 || 1388 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1389 dev_err(&pdev->dev, "Wrong SAI index\n"); 1390 of_node_put(args.np); 1391 return -EINVAL; 1392 } 1393 1394 if (of_property_match_string(args.np, "compatible", 1395 "st,stm32-sai-sub-a") >= 0) 1396 sai->synco = STM_SAI_SYNC_OUT_A; 1397 1398 if (of_property_match_string(args.np, "compatible", 1399 "st,stm32-sai-sub-b") >= 0) 1400 sai->synco = STM_SAI_SYNC_OUT_B; 1401 1402 if (!sai->synco) { 1403 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1404 of_node_put(args.np); 1405 return -EINVAL; 1406 } 1407 } 1408 1409 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1410 pdev->name, args.np->full_name); 1411 } 1412 1413 of_node_put(args.np); 1414 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1415 if (IS_ERR(sai->sai_ck)) { 1416 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 1417 return PTR_ERR(sai->sai_ck); 1418 } 1419 1420 if (STM_SAI_IS_F4(sai->pdata)) 1421 return 0; 1422 1423 /* Register mclk provider if requested */ 1424 if (of_find_property(np, "#clock-cells", NULL)) { 1425 ret = stm32_sai_add_mclk_provider(sai); 1426 if (ret < 0) 1427 return ret; 1428 } else { 1429 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 1430 if (IS_ERR(sai->sai_mclk)) { 1431 if (PTR_ERR(sai->sai_mclk) != -ENOENT) 1432 return PTR_ERR(sai->sai_mclk); 1433 sai->sai_mclk = NULL; 1434 } 1435 } 1436 1437 return 0; 1438 } 1439 1440 static int stm32_sai_sub_probe(struct platform_device *pdev) 1441 { 1442 struct stm32_sai_sub_data *sai; 1443 const struct of_device_id *of_id; 1444 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1445 int ret; 1446 1447 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1448 if (!sai) 1449 return -ENOMEM; 1450 1451 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1452 if (!of_id) 1453 return -EINVAL; 1454 sai->id = (uintptr_t)of_id->data; 1455 1456 sai->pdev = pdev; 1457 mutex_init(&sai->ctrl_lock); 1458 spin_lock_init(&sai->irq_lock); 1459 platform_set_drvdata(pdev, sai); 1460 1461 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1462 if (!sai->pdata) { 1463 dev_err(&pdev->dev, "Parent device data not available\n"); 1464 return -EINVAL; 1465 } 1466 1467 ret = stm32_sai_sub_parse_of(pdev, sai); 1468 if (ret) 1469 return ret; 1470 1471 if (STM_SAI_IS_PLAYBACK(sai)) 1472 sai->cpu_dai_drv = stm32_sai_playback_dai; 1473 else 1474 sai->cpu_dai_drv = stm32_sai_capture_dai; 1475 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1476 1477 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1478 IRQF_SHARED, dev_name(&pdev->dev), sai); 1479 if (ret) { 1480 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1481 return ret; 1482 } 1483 1484 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1485 &sai->cpu_dai_drv, 1); 1486 if (ret) 1487 return ret; 1488 1489 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1490 conf = &stm32_sai_pcm_config_spdif; 1491 1492 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1493 if (ret) { 1494 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1495 return ret; 1496 } 1497 1498 return 0; 1499 } 1500 1501 #ifdef CONFIG_PM_SLEEP 1502 static int stm32_sai_sub_suspend(struct device *dev) 1503 { 1504 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1505 1506 regcache_cache_only(sai->regmap, true); 1507 regcache_mark_dirty(sai->regmap); 1508 return 0; 1509 } 1510 1511 static int stm32_sai_sub_resume(struct device *dev) 1512 { 1513 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1514 1515 regcache_cache_only(sai->regmap, false); 1516 return regcache_sync(sai->regmap); 1517 } 1518 #endif /* CONFIG_PM_SLEEP */ 1519 1520 static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1521 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1522 }; 1523 1524 static struct platform_driver stm32_sai_sub_driver = { 1525 .driver = { 1526 .name = "st,stm32-sai-sub", 1527 .of_match_table = stm32_sai_sub_ids, 1528 .pm = &stm32_sai_sub_pm_ops, 1529 }, 1530 .probe = stm32_sai_sub_probe, 1531 }; 1532 1533 module_platform_driver(stm32_sai_sub_driver); 1534 1535 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1536 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1537 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1538 MODULE_LICENSE("GPL v2"); 1539